Composite operational circuit in integrated circuit

Abstract

The utility model provides a composite operational circuit in an integrated circuit. The composite operational circuit comprises a first register group, a second register group, a third register, a multiplication module and an addition module. The first register group is used for caching a plurality of filter coefficients or a plurality of convolution coefficients. And the second register group caches a plurality of to-be-filtered data which are input in sequence. And the third register receives and caches the input data to be convolved. The multiplication module and the addition module perform multiplication and addition operation based on the to-be-filtered data and the filtering coefficient when performing filtering operation, and perform multiplication and addition operation based on the convolution coefficient and the to-be-convolved data when performing convolution operation. Therefore, the filtering operation and the convolution operation are performed through the time division multiplexing multiplication module and the addition module, and the resource overhead of hardware is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of hardware operation especially relates to a composite operation circuit in integrated circuit.

BACKGROUND TECHNIQUE

[0002] In the existing integrated circuit, FIR (Finite Impulse Response) filter and convolution operation unit are usually designed respectively, and the hardware resource occupation is high.

[0003] Therefore, a new technical scheme is needed to solve the above problems.

UTILITY MODEL CONTENT

[0004] One of the purposes of the utility model is to provide a composite operation circuit in integrated circuit, which can not only realize filter operation, but also realize convolution operation, and reduce the resource consumption of hardware.

[0005] According to one aspect of the utility model, the utility model provides a composite operation circuit in integrated circuit, which comprises: a first register group, which is used to cache a plurality of filter coefficients when performing filter operation and cache a plurality of convolution coefficients when performing convolution operation; a second register group, which is used to receive and shift a plurality of to-be-filtered data input in sequence when performing filter operation; a third register, which is used to receive and cache to-be-convoluted data input when performing convolution operation; a multiplication module and an addition module, wherein the multiplication module and the addition module perform multiplication and addition operation based on the to-be-filtered data and the filter coefficients when performing filter operation, and perform multiplication and addition operation based on the convolution coefficients and the to-be-convoluted data when performing convolution operation.

[0006] In one embodiment, the first register group caches multiple convolution coefficients each time when performing the convolution operation, and the third register caches one data to be convolved each time when performing the convolution operation, wherein the multiple convolution coefficients in the first register group are updated multiple times and the data to be convolved in the third register is updated multiple times when performing the convolution operation; the multiplication module performs multiplication operation on each data to be filtered in the second register group and the corresponding filter coefficient in the first register group to obtain multiple filter product data when performing the filtering operation, and performs multiplication operation on the data to be convolved in the third register and each convolution coefficient in the first register group to obtain multiple convolution product data when performing the convolution operation; the addition module adds the multiple filter product data obtained by the multiplication module to obtain filter result data when performing the filtering operation, and adds the multiple convolution product data currently obtained by the multiplication module to the previous multiple convolution temporary result data to obtain the current multiple convolution temporary result data when performing the convolution operation, wherein the convolution coefficient in the first register group and the data to be convolved in the third register are updated once, and the current multiple convolution temporary result data is obtained based on the updated convolution coefficient and the updated data to be convolved when performing the convolution operation, and the multiple convolution temporary result data obtained last time is output as the multiple convolution final result data after the convolution coefficient and the data to be convolved are updated to a predetermined threshold number of times.

[0007] Compared with the prior art, the utility model discloses through time division multiplexing multiplication module and the addition module perform filtering operation and convolution operation, reduce the resource consumption of hardware.

DRAWINGS

[0008] In order to more clearly illustrate the technical scheme of the embodiments of the utility model, the drawings needed in the embodiment description will be briefly introduced as follows, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without paying the creative labor, wherein:

[0009] Figure 1 It is the partial structure block diagram of the composite operation circuit in the integrated circuit in the utility model, and

[0010] Figure 2 It is another partial structure block diagram of the composite operation circuit in the integrated circuit in the utility model.

CONCRETE IMPLEMENTATION

[0011] In order to make the above purpose, features and advantages of the utility model more apparent and easy to understand, the utility model will be further explained in detail in combination with the drawings and specific implementation.

[0012] The term "one embodiment" or "an embodiment" as may appear in various places of the specification is not necessarily referring to the same embodiment, nor is it necessary that all embodiments include the same features. In the description of the present application, unless otherwise specified and limited, the terms "connected", "connected to", "coupled to" and the like should be interpreted broadly, for example, can be direct electrical connection, or can be indirectly connected through an intermediate medium, and the intermediate medium can be electronic components, functional circuits, etc. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0013] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "front", "back", "left", "right", "vertical", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the present application.

[0014] The present application provides a composite operation circuit in an integrated circuit, which can not only realize filtering operation, but also realize convolution operation, and reduce the resource consumption of hardware.

[0015] Figure 1 Part of the structure block diagram of the composite operation circuit in the integrated circuit in the present application. Figure 2 Another part of the structure block diagram of the composite operation circuit in the integrated circuit in the present application.

[0016] As Figure 1 And 2As shown, the composite operation circuit in the integrated circuit includes a first register group 110, a second register group 120, a third register 130, a multiplication module 150, and an addition module 170. The first register group 110 is configured to buffer a plurality of filter coefficients when performing a filter operation, and buffer a plurality of convolution coefficients when performing a convolution operation. The second register group 120 is configured to receive and shift a plurality of to-be-filtered data input in sequence when performing the filter operation. The third register 130 is configured to receive and buffer input to-be-convoluted data when performing the convolution operation. The multiplication module 150 and the addition module 170 are configured to perform multiplication and addition operations based on the to-be-filtered data and the filter coefficients when performing the filter operation, and perform multiplication and addition operations based on the convolution coefficients and the to-be-convoluted data when performing the convolution operation. In this way, the filter operation and the convolution operation are performed by time-sharing the multiplication module and the addition module, thereby reducing the resource overhead of hardware. That is, in a single integrated circuit (or chip), the composite operation circuit can work as a filter and as a convolution operation unit. The composite operation circuit is time-shared to work as a filter or as a convolution operation unit by using efficient instructions, without interference.

[0017] In one embodiment, the first register group 110 buffers a plurality of convolution coefficients each time when performing the convolution operation, and the third register 130 buffers a to-be-convoluted data each time when performing the convolution operation. When performing the convolution operation, the plurality of convolution coefficients in the first register group 110 are updated multiple times, and the to-be-convoluted data in the third register 130 are updated multiple times. The multiplication module 150 performs multiplication operations on each to-be-filtered data in the second register group 120 and a corresponding filter coefficient in the first register group 110 to obtain a plurality of filter product data when performing the filter operation, and performs multiplication operations on the to-be-convoluted data in the third register 130 and each convolution coefficient in the first register group 110 to obtain a plurality of convolution product data when performing the convolution operation. The addition module 170 adds the plurality of filter product data obtained by the multiplication module 150 to obtain filter result data when performing the filter operation, and adds the plurality of convolution product data obtained by the multiplication module 150 to the previous plurality of convolution temporary result data to obtain the current plurality of convolution temporary result data when performing the convolution operation. When performing the convolution operation, the convolution coefficients in the first register group 110 and the to-be-convoluted data in the third register are updated each time, and the current plurality of convolution temporary result data is obtained based on the updated convolution coefficients and the updated to-be-convoluted data. After the convolution coefficients are updated to a predetermined number of times threshold, the last obtained plurality of convolution temporary result data is output as a plurality of convolution final result data.

[0018] In one embodiment, the composite operation circuit further comprises a fourth register group 160, a fifth register group 180 and a sixth register 190. The fourth register group 160 is used to buffer a plurality of filter product data obtained by the multiplication module 150 during filter operation, and to buffer a plurality of convolution product data obtained by the multiplication module 150 during convolution operation. During convolution operation, the addition module 170 adds the previous plurality of convolution temporary result data buffered in the fifth register group 180 with the plurality of convolution product data currently obtained by the multiplication module 150 respectively to obtain a plurality of current convolution temporary result data, and buffers the obtained plurality of current convolution temporary result data into the fifth register group 180. The sixth register 190 is used to buffer the filter result data obtained by the addition module 170 during filter operation.

[0019] It can be seen that the filter operation and the convolution operation time-division multiplex the first register group 110, the multiplication module 150, the addition module 170 and the fourth register group 160, so that the hardware cost is saved.

[0020] In one embodiment, the composite operation circuit further comprises a random access memory 140. The random access memory 140 is used to buffer the plurality of filter coefficients into the first register group 110 during filter operation, and to update the plurality of convolution coefficients to the first register group 110 during convolution operation.

[0021] The first register group 110 comprises a plurality of first registers 111. Each first register is used to buffer one of the plurality of filter coefficients during filter operation, and to buffer one of the plurality of convolution coefficients during convolution operation. The second register group 120 comprises a plurality of second registers 121, which correspond to the plurality of first registers respectively. The plurality of second registers are arranged in sequence to form a shift register. A first second register in the shift register sequentially receives inputted filter data. After receiving a new filter data, each second register in the shift register shifts the filter data buffered therein to the next second register. The first second register in the shift register buffers the new filter data, and a last second register in the shift register outputs or deletes the filter data buffered therein. The fourth register group 160 comprises a plurality of fourth registers 161. Each fourth register is used to buffer one filter product data obtained by the multiplication module during filter operation, and to buffer one convolution product data obtained by the multiplication module during convolution operation. The fifth register group 180 comprises a plurality of fifth registers 181. Each fifth register 181 is used to buffer one convolution temporary result data obtained by the addition module during convolution operation.

[0022] AsFigure 1 The example shown illustrates eight first registers 111, eight second registers 121, eight fourth registers 161, and eight fifth registers 181. In other embodiments, there can be m first registers, m second registers, m fourth registers, and m fifth registers, with m filtering coefficients and m convolution coefficients, where m is a natural number greater than or equal to 2. The filtering operation is an FIR filtering operation, and the first, second, and third registers are all n-bit registers, where n is a natural number greater than or equal to 2. Preferably, both the first and second register groups are vector registers, which can improve data loading speed and operation speed.

[0023] like Figure 1 As shown, the multiplication module 150 includes multiple multiplication units 151, such as m multiplication units ( Figure 1 (where m=8). Each multiplication unit corresponds to a first register 111 and a second register 121. When performing filtering operations, each multiplication unit multiplies the filtering coefficients cached in the corresponding first register 111 with the data to be filtered cached in the corresponding second register 121 to obtain a filtered product. Each fourth register 161 caches a filtered product obtained by a corresponding multiplication unit 151. When performing convolution operations, each multiplication unit 151 multiplies the convolution coefficients cached in the corresponding first register 111 with the data to be convolved cached in the third register 130 to obtain a convolution product. Each fourth register 161 caches a convolution product obtained by a corresponding multiplication unit.

[0024] like Figure 1 As shown, the addition module 170 includes multiple addition units 171, such as m addition units ( Figure 1 (m=8). Each addition unit 171 corresponds to a multiplication unit 151. Each addition unit is used to add the previous convolution temporary result data and the convolution product data obtained by the multiplication unit to obtain the current convolution temporary result data when performing convolution operation. Each fifth register 181 caches the convolution temporary result data obtained by the corresponding addition unit 171.

[0025] like Figure 1 As shown, part or all of the addition unit 171 is used to add the multiple filtered product data obtained from each multiplication unit to obtain the filtered result data during filtering operations, and the sixth register 190 caches the filtered result data obtained by the addition module. Figure 1In the example shown, m = 8, and there are 8 addition units, in which the addition unit addO adds the 0th and 4th filter product data obtained by the multiplication units (MulO, Mul4), the addition unit addl adds the 1st and 5th filter product data obtained by the multiplication units (Mul1, Mul5), the addition unit add2 adds the 2nd and 6th filter product data obtained by the multiplication units (Mul2, Mul6), the addition unit add3 adds the 3rd and 7th filter product data obtained by the multiplication units (Mul3, Mul7), the addition unit add4 adds the result of the addition unit addO and the result of the addition unit addl, the addition unit add5 adds the result of the addition unit add2 and the result of the addition unit add3. The addition unit add6 adds the result of the addition unit add4 and the result of the addition unit add5 to obtain the final filter result data, which is finally output to the sixth register 190. The addition unit add7 is not used in the filter operation.

[0026] When the composite operation circuit performs the FIR filter operation, i.e., is used as a FIR filter, the following FIR filter operation is performed:

[0027] where x t-i is the to-be-filtered data cached at a past time; w i is a fixed filter coefficient, y t is the filter result data (i.e., the data after FIR filtering) output at the current t time, which is stored in the sixth register 190, and i is the position or serial number of the corresponding unit, parameter, or data, i.e., 0-7 in the example shown in FIG. 1. Figure 1 That is, in the FIR filter operation, the m filter coefficients w i are respectively cached in the m first registers 111 (i is respectively 0-7), the m to-be-filtered data x t-i are respectively cached in the m second registers 121 (i is respectively 0-7), the multiplication module 150 performs the multiplication operation, and the addition module 170 performs the addition operation.

[0028] When the composite operation circuit performs the convolution operation, i.e., is used as a convolution operation unit, the following convolution operation is performed:

[0029]

[0030] where x k is the k+1th input to-be-convolved data, which is cached in the third register 130, The convolution coefficient for the k+1th update is stored in the corresponding first register [i], and in the operation process, is updated as k changes, and K+1 is a predetermined number threshold of the update number of the convolution coefficient; y i is the ith convolution temporary result data, which is stored in the fifth register [i], where [i] is the position or serial number of the corresponding unit, parameter or data.

[0031] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0032] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications and variations to the above embodiments within the scope of the present application.

Claims

1. A composite operational circuit in an integrated circuit, characterized in that, It comprises: a first register group for buffering a plurality of filter coefficients when performing a filtering operation and a plurality of convolution coefficients when performing a convolution operation; a second register group for receiving and shifting a plurality of to-be-filtered data input in sequence when performing a filtering operation; a third register for receiving and buffering input to-be-convoluted data when performing a convolution operation; a multiplication module and an addition module, wherein the multiplication module and the addition module perform multiplication and addition operations based on the to-be-filtered data and the filter coefficients when performing a filtering operation, and perform multiplication and addition operations based on the convolution coefficients and the to-be-convoluted data when performing a convolution operation.

2. The composite operation circuit according to claim 1, wherein the first register group buffers a plurality of convolution coefficients each time when performing a convolution operation, and the third register buffers a to-be-convoluted data each time when performing a convolution operation, wherein the plurality of convolution coefficients in the first register group are updated multiple times, and the to-be-convoluted data in the third register are updated multiple times when performing a convolution operation; the multiplication module performs multiplication operations on each to-be-filtered data in the second register group and a corresponding filter coefficient in the first register group to obtain a plurality of filter product data when performing a filtering operation, and performs multiplication operations on the to-be-convoluted data in the third register and each convolution coefficient in the first register group to obtain a plurality of convolution product data when performing a convolution operation; the addition module adds the plurality of filter product data obtained by the multiplication module to obtain filter result data when performing a filtering operation, and adds the plurality of convolution product data currently obtained by the multiplication module to the previous plurality of convolution temporary result data to obtain the current plurality of convolution temporary result data when performing a convolution operation, wherein the convolution coefficients in the first register group and the to-be-convoluted data in the third register are updated once each time to obtain the current plurality of convolution temporary result data based on the updated convolution coefficients and the updated to-be-convoluted data when performing a convolution operation, and the plurality of convolution temporary result data obtained the last time are output as the plurality of convolution final result data after the convolution coefficients and the to-be-convoluted data are updated to a predetermined threshold number of times.

3. The composite arithmetic circuit according to claim 2, wherein It further comprises: a fourth register group for buffering the plurality of filter product data obtained by the multiplication module when performing a filtering operation, and buffering the plurality of convolution product data obtained by the multiplication module when performing a convolution operation; a fifth register group, and the addition module adds the current plurality of convolution temporary result data obtained by the multiplication module to the previous plurality of convolution temporary result data buffered in the fifth register group to obtain the current plurality of convolution temporary result data when performing a convolution operation, and buffers the obtained current plurality of convolution temporary result data into the fifth register group; a sixth register for buffering the filter result data obtained by the addition module when performing a filtering operation.

4. The composite operation circuit according to claim 3, wherein the filtering operation and the convolution operation time-division multiplex the first register group, the multiplication module, the addition module, and the fourth register group.

5. The composite arithmetic circuit according to claim 3, wherein It further comprises: A random access memory is used to cache the plurality of filter coefficients into the first register set when performing the filter operation, and update the plurality of convolution coefficients into the first register set when performing the convolution operation.

6. The composite operation circuit of claim 3, wherein, The first register set comprises a plurality of first registers, each of which is used to cache one of the plurality of filter coefficients when performing the filter operation, and cache one of the plurality of convolution coefficients when performing the convolution operation. The second register set comprises a plurality of second registers, each of which corresponds to one of the plurality of first registers, and the plurality of second registers are sequentially arranged to form a shift register, a first second register in the shift register sequentially receives inputted filter data, and each of the second registers sequentially shifts the filter data cached therein to the next second register after receiving a new filter data, the first second register in the shift register caches the new filter data, and a last second register in the shift register outputs or deletes the filter data cached therein. The fourth register set comprises a plurality of fourth registers, each of which is used to cache one filter product data obtained by the multiplication module when performing the filter operation, and cache one convolution product data obtained by the multiplication module when performing the convolution operation. The fifth register set comprises a plurality of fifth registers, each of which is used to cache one convolution temporary result data obtained by the addition module when performing the convolution operation.

7. The composite operation circuit of claim 6, wherein, The multiplication module comprises a plurality of multiplication units, each of which corresponds to one first register and one second register, each multiplication unit performs multiplication operation on the filter coefficient cached in the corresponding first register and the filter data cached in the corresponding second register to obtain one filter product data when performing the filter operation, each fourth register caches one filter product data obtained by the corresponding multiplication unit, and each multiplication unit performs multiplication operation on the convolution coefficient cached in the corresponding first register and the convolution data cached in the third register to obtain one convolution product data when performing the convolution operation, each fourth register caches one convolution product data obtained by the corresponding multiplication unit.

8. The composite operation circuit of claim 7, wherein, The addition module comprises a plurality of addition units, each of which corresponds to one multiplication unit, each addition unit is used to add one previous convolution temporary result data and one convolution product data currently obtained by the multiplication unit to obtain one current convolution temporary result data when performing the convolution operation, and each fifth register caches one convolution temporary result data obtained by the corresponding addition unit. Some or all of the addition units are used to add a plurality of filter product data obtained by the multiplication units to obtain filter result data when performing the filter operation, and the sixth register caches the filter result data obtained by the addition module.

9. The composite arithmetic circuit according to claim 3, wherein The filter operation is a FIR filter operation. The first register, the second register and the third register are n-bit registers, n is a natural number greater than or equal to 2, The first register group and the second register group are vector registers.

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