Multi-input channel AND gate circuit, signal processing device and robot
By designing multi-input channels and gate circuits, and utilizing a combination of controllable switches and load resistors to achieve logic control, the problem of logic gate chips being unable to adapt to high voltages is solved, thereby improving the sensor signal processing efficiency and interface resource utilization of the capsule endoscopy robot.
Patent Information
- Application Number
- CN202422777613.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-11-13
AI Technical Summary
In existing technologies, logic gate chips cannot adapt to high-voltage environments, resulting in low efficiency of sensor signal processing and insufficient utilization of interface resources in capsule endoscopy robots.
Design a multi-input channel AND gate circuit that uses first and second controllable switches, combined with load resistors and base resistors, and implements logic control through transistors to adapt to different voltage environments.
It improves sensor signal processing efficiency, enhances interface resource utilization, ensures the accuracy of logic output, and adapts to various voltage environments.
Smart Images
Figure CN223567608U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of signal processing, and in particular to a multi-input channel AND gate circuit, a signal processing device, and a robot. Background Technology
[0002] In capsule endoscopy robots, numerous sensors are typically installed inside the robotic arm to achieve positioning and limiting functions, capturing its positional status. To obtain the output signals from these sensors, logic devices are sometimes needed to perform simple processing, reducing the number of signals entering the robot's data processing center and improving the utilization of interface resources. Current technology often uses integrated circuits (ICs) to facilitate logic output functions in circuit design, such as logic gate chips. Different numbers of input channels and logic output functions can be selected based on the specific requirements to achieve the desired logic function. However, these logic gate chips typically operate at power supplies below ±18V, with most below 5.5V, suitable for low-voltage systems but incompatible with high-voltage systems. Utility Model Content
[0003] The purpose of this invention is to provide a multi-input channel AND gate circuit, a signal processing device, and a robot. The first and second controllable switches are turned on and off according to the signals of the input channels, thereby realizing AND gate logic. The controllable switches can be adjusted according to the actual voltage requirements to adapt to more types of voltage environments.
[0004] To solve the above technical problems, this application provides a multi-input channel AND gate circuit, including a first load resistor, a first controllable switch, a second load resistor and a plurality of second controllable switches, wherein the number of second controllable switches is equal to the number of input channels, and the second controllable switches correspond one-to-one with the input channels;
[0005] The first end of the first load resistor is connected to the power supply. The second end of the first load resistor is connected to the first end of the first controllable switch, and the common terminal of the connection is used as the output channel. The second end of the first controllable switch is grounded. The control terminal of each second controllable switch is connected to the corresponding input channel. The first end of each second controllable switch is connected to the power supply. The second end of each second controllable switch is connected to the control terminal of the first controllable switch and the first end of the second load resistor. The second end of the second load resistor is grounded.
[0006] The first load resistor and the second load resistor are used for current limiting. The second controllable switch is turned off when the voltage input to the corresponding input channel is not lower than the first preset voltage. The first controllable switch is used to turn off when both the first and second controllable switches are turned off.
[0007] On the other hand, it also includes a first base resistor and a plurality of second base resistors, the number of the second base resistors being equal to the number of the second controllable switches, and the second base resistors and the second controllable switches corresponding one-to-one with the input channels;
[0008] The first end of the first base resistor is connected to the second end of a plurality of second controllable switches, and the second end of the first base resistor is connected to the control end of the first controllable switch;
[0009] The first end of each second base resistor is connected to the corresponding input channel, and the second end of each second base resistor is connected to the control end of the corresponding second controllable switch;
[0010] The first base resistor is used to protect the first controllable switch, and each of the second base resistors is used to protect the second controllable switch.
[0011] On the other hand, when the first controllable switch is an NPN transistor and the second controllable switch is a PNP transistor;
[0012] The base of the NPN transistor serves as the control terminal of the first controllable switch, the collector of the NPN transistor serves as the first terminal of the controllable switch, and the emitter of the NPN transistor serves as the second terminal of the controllable switch.
[0013] The base of each PNP transistor serves as the control terminal of the second controllable switch, the emitter of each PNP transistor serves as the first terminal of the second controllable switch, and the collector of each PNP transistor serves as the second terminal of the second controllable switch.
[0014] Each of the PNP transistors is turned off when the base input voltage is not lower than a first preset voltage, and the NPN transistor is turned off when all of the PNP transistors are turned off.
[0015] On the other hand, it also includes a first pull-down resistor, the number of which is equal to the number of the second controllable switches, and the first pull-down resistor, the second controllable switch and the input channel correspond one-to-one;
[0016] The first terminal of each first pull-down resistor is connected to the corresponding input channel, and the second terminal of each first pull-down resistor is grounded.
[0017] The first pull-down resistor is used to pull down the voltage input to the input channel.
[0018] On the other hand, it also includes a first pull-up resistor, the number of which is equal to the number of the second controllable switches, and the first pull-up resistor, the second controllable switch and the input channel correspond one-to-one;
[0019] The first end of each first pull-up resistor is connected to the power supply, and the second end of each first pull-up resistor is connected to the corresponding input channel.
[0020] The first pull-up resistor is used to increase the voltage input to the input channel.
[0021] On the other hand, when the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor, it also includes an inverter. The number of inverters is equal to the number of the second controllable switches, and the inverters, the second controllable switches and the input channels correspond one-to-one.
[0022] The base of the PNP transistor serves as the control terminal of the first controllable switch, the emitter of the PNP transistor serves as the first terminal of the controllable switch, and the collector of the PNP transistor serves as the second terminal of the controllable switch.
[0023] The base of each NPN transistor serves as the control terminal of the second controllable switch, the collector of each NPN transistor serves as the first terminal of the second controllable switch, and the emitter of each NPN transistor serves as the second terminal of the second controllable switch.
[0024] The input terminal of each inverter is connected to the corresponding input channel, and the output terminal of each inverter is connected to the base of the corresponding NPN transistor.
[0025] Each of the NPN transistors is turned off when the base input voltage is 0, and the PNP transistor is turned off when all of the NPN transistors are turned off.
[0026] On the other hand, it also includes a second pull-down resistor, the number of which is equal to the number of the second controllable switches, and the second pull-down resistor and the second controllable switch correspond one-to-one with the input channel;
[0027] The first terminal of each second pull-down resistor is connected to the corresponding input channel, and the second terminal of each second pull-down resistor is grounded.
[0028] The second pull-down resistor is used to pull down the voltage input to the input channel.
[0029] On the other hand, it also includes a second pull-up resistor, the number of which is equal to the number of the second controllable switches, and the second pull-down resistor, the second controllable switch and the input channel correspond one-to-one;
[0030] The first end of each second pull-up resistor is connected to the power supply, and the second end of each second pull-up resistor is connected to the corresponding input channel.
[0031] The second pull-up resistor is used to increase the voltage input to the input channel.
[0032] To address the aforementioned technical problems, this application also provides a signal processing apparatus, including the aforementioned multi-input channel and gate circuit.
[0033] To address the aforementioned technical problems, this application also provides a robot, wherein the robot's robotic arm includes the aforementioned signal processing device for processing the output signals of various sensors in the robotic arm.
[0034] This application provides a multi-input channel AND gate circuit, a signal processing device, and a robot, relating to the field of signal processing. It includes a first load resistor, a first controllable switch, a second load resistor, and multiple second controllable switches. The first terminal of the first load resistor is connected to a power supply. The second terminal of the first load resistor is connected to the first terminal of the first controllable switch, and their common terminal serves as an output channel. The second terminal of the first controllable switch is grounded. The control terminal of each second controllable switch is connected to its corresponding input channel. The first terminal of each second controllable switch is connected to a power supply, and the second terminal of each second controllable switch is connected to both the control terminal of the first controllable switch and the first terminal of the second load resistor. The second terminal of the second load resistor is grounded. The first and second controllable switches are turned on and off according to the signals from the input channels, thereby implementing AND gate logic. The controllable switches can be adjusted according to the required voltage to adapt to various voltage environments. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This application provides a schematic diagram of the structure of a multi-input channel AND gate circuit;
[0037] Figure 2 A schematic diagram of a multi-input channel AND gate circuit provided in this application, wherein the first controllable switch is an NPN transistor and the second controllable switch is a PNP transistor;
[0038] Figure 3 A schematic diagram of a multi-input channel AND gate circuit when the first controllable switch is an NPN transistor and the second controllable switch is a PNP transistor, provided in this application;
[0039] Figure 4A schematic diagram of a multi-input channel AND gate circuit provided in this application, wherein the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor;
[0040] Figure 5 A schematic diagram of a multi-input channel AND gate circuit when the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor, provided in this application;
[0041] Figure 6 A schematic diagram of a multi-input channel AND gate circuit where the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor, provided in this application. Detailed Implementation
[0042] The core of this utility model is to provide a multi-input channel AND gate circuit, a signal processing device, and a robot. The first and second controllable switches are turned on and off according to the signals of the input channels, thereby realizing AND gate logic. The controllable switches can be adjusted according to the actual voltage requirements to adapt to more types of voltage environments.
[0043] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0044] Figure 1 The present application provides a schematic diagram of a multi-input channel AND gate circuit. The multi-input channel AND gate circuit includes a first load resistor, a first controllable switch, a second load resistor, and a plurality of second controllable switches. The number of second controllable switches is equal to the number of input channels, and the second controllable switches correspond one-to-one with the input channels.
[0045] The first end of the first load resistor is connected to the power supply. The second end of the first load resistor is connected to the first end of the first controllable switch, and the common terminal of the connection is used as the output channel. The second end of the first controllable switch is grounded. The control terminal of each second controllable switch is connected to the corresponding input channel. The first end of each second controllable switch is connected to the power supply. The second end of each second controllable switch is connected to the control terminal of the first controllable switch and the first end of the second load resistor. The second end of the second load resistor is grounded.
[0046] The first load resistor and the second load resistor are used for current limiting. The second controllable switch is turned off when the voltage input to the corresponding input channel is not lower than the first preset voltage. The first controllable switch is used to turn off when both the second controllable switches are turned off.
[0047] Considering the logic of an AND gate, it outputs 1 when all inputs are 1, and outputs 0 when the input includes 0. In practical applications, such as capsule endoscopy robots, to achieve positioning and limiting of the robotic arm, a large number of sensors are usually installed inside the robotic arm to obtain its position status. To obtain the output signals of these sensors, it is sometimes necessary to use logic devices to perform simple processing on the sensor output signals, thereby reducing the number of signals entering the robot's data processing center and improving the utilization of interface resources. When all sensor output signals are logic 1, the AND gate will output logic 1. Specifically, in this application, logic 1 can be a high level, and logic 0 can be a low level. The distinction between high and low levels is based on voltage; for example, a voltage not lower than a first preset voltage value is logic 1, and a voltage of 0 is logic 0.
[0048] Therefore, in this application, the sensor's output signal is input to a multi-input channel AND gate circuit via multiple input channels. After being judged by the AND gate, the multi-input channel AND gate circuit outputs the signal through the output channel. The overall logic is that when all input signals of the input channels are high, the output signal is high; when a low level is present in the input signals of the input channels, the output signal is low.
[0049] by Figure 1 For example, Figure 1 In the diagram, Q21, Q22, Q23 to Q2x are x second controllable switches, corresponding to x input channels INPUT1, INPUT2, INPUT3 to INPUTx respectively, and Q1 is the first controllable switch.
[0050] The second controllable switch corresponds one-to-one with the input signal of the input channel. The input signal of the input channel can directly control the conduction and de-conduction of the second controllable switch, and thus the conduction and de-conduction of the first controllable switch is controlled by the conduction and de-conduction of multiple second controllable switches. Specifically, the second controllable switch is turned off when the voltage of the input signal is not lower than the first preset voltage. The first controllable switch is turned off only when all the second controllable switches are turned off, and the output channel is then connected to the power supply, i.e., at a high level.
[0051] This application provides a multi-input channel AND gate circuit, relating to the field of signal processing, including a first load resistor, a first controllable switch, a second load resistor, and multiple second controllable switches. The first terminal of the first load resistor is connected to a power supply, and the second terminal of the first load resistor is connected to the first terminal of the first controllable switch, with the common terminal serving as an output channel. The second terminal of the first controllable switch is grounded. The control terminal of each second controllable switch is connected to its corresponding input channel. The first terminal of each second controllable switch is connected to a power supply, and the second terminal of each second controllable switch is connected to both the control terminal of the first controllable switch and the first terminal of the second load resistor. The second terminal of the second load resistor is grounded. The first and second controllable switches are turned on and off according to the signals from the input channels, thereby implementing AND gate logic. The controllable switches can be adjusted in model according to the actual voltage requirements to adapt to more diverse voltage environments.
[0052] Based on the above embodiments:
[0053] In some embodiments, the system further includes a first base resistor and a plurality of second base resistors, the number of second base resistors being equal to the number of second controllable switches, and the second base resistors and the second controllable switches corresponding one-to-one with the input channels.
[0054] The first end of the first base resistor is connected to the second end of a plurality of second controllable switches, and the second end of the first base resistor is connected to the control end of the first controllable switch.
[0055] The first end of each second base resistor is connected to the corresponding input channel, and the second end of each second base resistor is connected to the control end of the corresponding second controllable switch.
[0056] The first base resistor is used to protect the first controllable switch, and each second base resistor is used to protect the second controllable switch.
[0057] For ease of circuit connection, both the first and second controllable switches can be transistors. In practical setups, a base resistor can be placed at the base of the transistor to protect the controllable switches. Figure 1 For example, Figure 1 In the diagram, Rbn is the first base resistor, and Rbp1, Rbp2, Rbp3 to Rbpx are all second base resistors.
[0058] Figure 2 A schematic diagram of a multi-input channel AND gate circuit provided in this application, wherein the first controllable switch is an NPN transistor and the second controllable switch is a PNP transistor;
[0059] In some embodiments, when the first controllable switch is an NPN transistor and the second controllable switch is a PNP transistor;
[0060] The base of the NPN transistor serves as the control terminal of the first controllable switch, the collector of the NPN transistor serves as the first terminal of the controllable switch, and the emitter of the NPN transistor serves as the second terminal of the controllable switch.
[0061] The base of each PNP transistor serves as the control terminal of the second controllable switch, the emitter of each PNP transistor serves as the first terminal of the second controllable switch, and the collector of each PNP transistor serves as the second terminal of the second controllable switch.
[0062] Each PNP transistor is used to turn off when the base input voltage is not lower than a first preset voltage, and the NPN transistor is used to turn off when all PNP transistors are turned off.
[0063] Since transistors include NPN transistors and PNP transistors, there are several options for implementing logic control. The first option is to use an NPN transistor as the first controllable switch and a PNP transistor as the second controllable switch.
[0064] Each input signal INPUTx is connected to one end of the base resistor Rbpx of the corresponding PNP transistor, and the other end of the base resistor Rbpx is connected to the base of the corresponding PNP transistor Qpx, where x=1,2,3…, corresponding to the number of each input channel; one end of resistor RLp is grounded, and the other end is connected in parallel to the collectors of all PNP transistors Qpx; the emitters of all PNP transistors Qpx are connected in parallel to the system power supply VCC; the collectors of all PNP transistors Qpx are also connected to one end of the base resistor Rbn of NPN transistor Qn, and the other end of resistor Rbn is connected to the base of NPN transistor Qn; the emitter of NPN transistor Qn is grounded; the collector of NPN transistor Qn is connected to one end of the load resistor RLn, and the other end of RLn is connected to the system power supply VCC; the output signal terminal is connected to the collector of NPN transistor Qn, and simultaneously connected to the output signal detection terminal PLC input interface OUTPUT.
[0065] The specific implementation process of the logical AND operation is as follows:
[0066] (1) When all input signals INPUT1, INPUT2, ..., INPUTx are high, i.e. logic 1, all PNP transistors Qp1, Qp2, ..., Qpx are cut off because there is no forward bias between their bases and emitters. All transistors are not conducting. Since the collector of the PNP transistor is pulled down to ground by the load resistor RLp, the collector of the PNP transistor is at a low level. Since the collector of the PNP transistor is connected to the base of the NPN transistor through the resistor Rbn, the base of the NPN transistor is also at a low level. Since there is no forward bias between the base and emitter of the NPN transistor Qn, the transistor Qn is not conducting. At this time, the output signal OUTPUT is pulled up to a high level by the load resistor RLn, and the output is in logic 1 state.
[0067] (2) When one or more of the input signals INPUT1, INPUT2, ..., INPUTx are low, i.e. logic 0, the base and emitter of the corresponding PNP transistor Qpx are forward biased and turned on. The collector voltage of the corresponding transistor Qpx is approximately equal to the power supply voltage. At this time, the base and emitter of the NPN transistor Qn are forward biased and turned on. The output signal OUTPUT is pulled down to low by the collector of the NPN transistor, and the output is in logic 0 state.
[0068] In some embodiments, the system further includes a first pull-down resistor, the number of which is equal to the number of the second controllable switches, and the first pull-down resistor, the second controllable switch, and the input channel are corresponding one-to-one.
[0069] The first terminal of each first pull-down resistor is connected to the corresponding input channel, and the second terminal of each first pull-down resistor is grounded.
[0070] The first pull-down resistor is used to pull down the input voltage of the input channel.
[0071] Each input signal INPUT1, INPUT2, ..., INPUTx has one end of a corresponding pull-down resistor RL1, RL2, ..., RLx connected in parallel, and the other end of the pull-down resistor RL1, RL2, ..., RLx is grounded. When the input signals INPUT1, INPUT2, ..., INPUTx are PNP open-drain outputs, the input signal has a logic 1 state (i.e., the voltage can reach the first preset voltage) and no logic 0 state (i.e., the voltage cannot reach 0V). The input signal in a logic 0 state exhibits a high impedance state, at which point the input signal is pulled down to ground by the load resistors RL1, RL2, ..., RLx at the input terminal, ensuring the accuracy of the output logic.
[0072] It should also be noted that the pull-down resistor does not affect the logic 1 state of the input signal.
[0073] Figure 3A schematic diagram of a multi-input channel AND gate circuit when the first controllable switch is an NPN transistor and the second controllable switch is a PNP transistor, provided in this application;
[0074] In some embodiments, the system further includes a first pull-up resistor, the number of which is equal to the number of the second controllable switches, and the first pull-up resistor, the second controllable switch, and the input channel are corresponding one-to-one.
[0075] The first end of each first pull-up resistor is connected to the power supply, and the second end of each first pull-up resistor is connected to the corresponding input channel.
[0076] The first pull-up resistor is used to increase the input voltage of the input channel.
[0077] Each input signal INPUT1, INPUT2, ..., INPUTx has a corresponding pull-up resistor RL1, RL2, ..., RLx connected in parallel at one end, and the other end of the pull-up resistor RL1, RL2, ..., RLx connected to the system power supply VCC. When the input signals INPUT1, INPUT2, ..., INPUTx are NPN open-drain outputs, the input signal has a logic 0 state (i.e., the voltage can reach 0V) and no logic 1 state (i.e., the voltage cannot reach the first preset voltage). The input signal in the logic 1 state exhibits a high impedance state. At this time, the input signal is pulled up to the power supply by the load resistors RL1, RL2, ..., RLx at the input terminal, which ensures the accuracy of the output logic.
[0078] It should also be noted that the pull-up resistor does not affect the logic 0 state of the input signal.
[0079] Figure 4 A schematic diagram of a multi-input channel AND gate circuit provided in this application, wherein the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor;
[0080] In some embodiments, when the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor, an inverter is also included. The number of inverters is equal to the number of the second controllable switches, and the inverters, the second controllable switches and the input channels correspond one-to-one.
[0081] The base of the PNP transistor serves as the control terminal of the first controllable switch, the emitter of the PNP transistor serves as the first terminal of the controllable switch, and the collector of the PNP transistor serves as the second terminal of the controllable switch.
[0082] The base of each NPN transistor serves as the control terminal of the second controllable switch, the collector of each NPN transistor serves as the first terminal of the second controllable switch, and the emitter of each NPN transistor serves as the second terminal of the second controllable switch.
[0083] The input terminal of each inverter is connected to the corresponding input channel, and the output terminal of each inverter is connected to the base of the corresponding NPN transistor.
[0084] Each NPN transistor is used to turn off when the base input voltage is 0, and the PNP transistor is used to turn off when all NPN transistors are turned off.
[0085] The second type is where the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor.
[0086] Each input signal INPUTx is connected to the input terminal of the corresponding inverter Vx. The output terminal of the inverter Vx is connected to one end of the base resistor Rbpx of the corresponding NPN transistor. The other end of the base resistor Rbnx of the NPN transistor is connected to the base of the corresponding NPN transistor Qnx, where x=1,2,3..., corresponding to the number of each input channel. One end of the resistor RLn is connected to the power supply, and the other end is connected in parallel with the collector of all NPN transistors Qnx. The emitters of all NPN transistors Qnx are connected in parallel to ground. The collectors of all NPN transistors Qnx are connected to one end of the base resistor Rbp of PNP transistor Qp, and the other end of resistor Rbp is connected to the base of PNP transistor Qp; the collector of PNP transistor Qp is grounded; the emitter of PNP transistor Qp is connected to one end of the load resistor RLp, and the other end of RLp is connected to the system power supply VCC; the output signal terminal is connected to the emitter of PNP transistor Qp, and is also connected to the output signal detection terminal PLC input interface OUTPUT.
[0087] The specific implementation process of the logical AND operation is as follows:
[0088] (1) When all input signals INPUT1, INPUT2, ..., INPUTx are high, i.e. logic 1, they are converted to logic 0 after passing through the inverter. All NPN transistors Qn1, Qn2, ..., Qnx are cut off because there is no forward bias between their bases and emitters. All transistors are not conducting. Since the collector of the NPN transistor is pulled up to the power supply VCC by the load resistor RLn, the collector of the NPN transistor is at a high level. Since the collector of the NPN transistor is connected to the base of the PNP transistor through the resistor Rbp, the base of the PNP transistor is also at a high level. Since there is no forward bias between the base and emitter of the PNP transistor Qp, the transistor Qp is not conducting. At this time, the output signal OUTPUT is pulled up to a high level by the load resistor RLp, and the output is in logic 1 state.
[0089] (2) When one or more of the input signals INPUT1, INPUT2, ..., INPUTx are low, i.e. logic 0, they are converted to logic 1 after passing through the inverter. The base and emitter of the corresponding NPN transistor Qnx are forward biased and turned on, and the collector of the corresponding transistor Qnx is grounded. At this time, the base and emitter of the PNP transistor Qp are forward biased and turned on, and the output signal OUTPUT is pulled down to low level by the collector of the PNP transistor, outputting logic 0.
[0090] Figure 5 A schematic diagram of a multi-input channel AND gate circuit when the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor, provided in this application;
[0091] In some embodiments, a second pull-down resistor is further included, the number of which is equal to the number of the second controllable switches, and the second pull-down resistor and the second controllable switch correspond one-to-one with the input channel;
[0092] The first terminal of each second pull-down resistor is connected to the corresponding input channel, and the second terminal of each second pull-down resistor is grounded.
[0093] The second pull-down resistor is used to pull down the input voltage of the input channel.
[0094] Each input signal INPUT1, INPUT2, ..., INPUTx has one end of a corresponding pull-down resistor RL1, RL2, ..., RLx connected in parallel, and the other end of the pull-down resistor RL1, RL2, ..., RLx is grounded. When the input signals INPUT1, INPUT2, ..., INPUTx are PNP open-drain outputs, the input signal has a logic 1 state (i.e., the voltage can reach the first preset voltage) and no logic 0 state (i.e., the voltage cannot reach 0V). The input signal in a logic 0 state exhibits a high impedance state, at which point the input signal is pulled down to ground by the load resistors RL1, RL2, ..., RLx at the input terminal, ensuring the accuracy of the output logic.
[0095] It should also be noted that the pull-down resistor does not affect the logic 1 state of the input signal.
[0096] Figure 6 A schematic diagram of a multi-input channel AND gate circuit when the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor, provided in this application;
[0097] In some embodiments, a second pull-up resistor is further included, the number of which is equal to the number of the second controllable switches, and the second pull-down resistor, the second controllable switch and the input channel correspond one-to-one.
[0098] The first end of each second pull-up resistor is connected to the power supply, and the second end of each second pull-up resistor is connected to the corresponding input channel.
[0099] The second pull-up resistor is used to increase the input voltage of the input channel.
[0100] This application also provides a signal processing apparatus, including the aforementioned multi-input channel and gate circuit.
[0101] The description of the signal processing device provided in this application is based on the above embodiments and will not be repeated here.
[0102] Each input signal INPUT1, INPUT2, ..., INPUTx has a corresponding pull-up resistor RL1, RL2, ..., RLx connected in parallel at one end, and the other end of the pull-up resistor RL1, RL2, ..., RLx connected to the system power supply VCC. When the input signals INPUT1, INPUT2, ..., INPUTx are NPN open-drain outputs, the input signal has a logic 0 state (i.e., the voltage can reach 0V) and no logic 1 state (i.e., the voltage cannot reach the first preset voltage). The input signal in the logic 1 state exhibits a high impedance state. At this time, the input signal is pulled up to the power supply by the load resistors RL1, RL2, ..., RLx at the input terminal, which ensures the accuracy of the output logic.
[0103] It should also be noted that the pull-up resistor does not affect the logic 0 state of the input signal.
[0104] This application also provides a robot, the robotic arm of which includes the aforementioned signal processing device for processing the output signals of various sensors in the robotic arm.
[0105] The robot provided in this application is described in the above embodiments and will not be repeated here.
[0106] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0107] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0108] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A multi-input channel AND gate circuit, characterized in that, It includes a first load resistor, a first controllable switch, a second load resistor, and multiple second controllable switches. The number of second controllable switches is equal to the number of input channels, and each second controllable switch corresponds to one of the input channels. The first end of the first load resistor is connected to the power supply. The second end of the first load resistor is connected to the first end of the first controllable switch, and the common terminal of the connection is used as the output channel. The second end of the first controllable switch is grounded. The control terminal of each second controllable switch is connected to the corresponding input channel. The first end of each second controllable switch is connected to the power supply. The second end of each second controllable switch is connected to the control terminal of the first controllable switch and the first end of the second load resistor. The second end of the second load resistor is grounded. The first load resistor and the second load resistor are used for current limiting. The second controllable switch is turned off when the voltage input to the corresponding input channel is not lower than the first preset voltage. The first controllable switch is used to turn off when both the first and second controllable switches are turned off.
2. The multi-input channel AND gate circuit as described in claim 1, characterized in that, It also includes a first base resistor and multiple second base resistors, the number of which is equal to the number of the second controllable switches, and the second base resistors and the second controllable switches correspond one-to-one with the input channels; The first end of the first base resistor is connected to the second end of a plurality of second controllable switches, and the second end of the first base resistor is connected to the control end of the first controllable switch; The first end of each second base resistor is connected to the corresponding input channel, and the second end of each second base resistor is connected to the control end of the corresponding second controllable switch; The first base resistor is used to protect the first controllable switch, and each of the second base resistors is used to protect the second controllable switch.
3. The multi-input channel AND gate circuit as described in claim 1 or 2, characterized in that, When the first controllable switch is an NPN transistor and the second controllable switch is a PNP transistor; The base of the NPN transistor serves as the control terminal of the first controllable switch, the collector of the NPN transistor serves as the first terminal of the controllable switch, and the emitter of the NPN transistor serves as the second terminal of the controllable switch. The base of each PNP transistor serves as the control terminal of the second controllable switch, the emitter of each PNP transistor serves as the first terminal of the second controllable switch, and the collector of each PNP transistor serves as the second terminal of the second controllable switch. Each of the PNP transistors is turned off when the base input voltage is not lower than a first preset voltage, and the NPN transistor is turned off when all of the PNP transistors are turned off.
4. The multi-input channel AND gate circuit as described in claim 3, characterized in that, It also includes a first pull-down resistor, the number of which is equal to the number of the second controllable switches, and the first pull-down resistor, the second controllable switch and the input channel correspond one-to-one; The first terminal of each first pull-down resistor is connected to the corresponding input channel, and the second terminal of each first pull-down resistor is grounded. The first pull-down resistor is used to pull down the voltage input to the input channel.
5. The multi-input channel AND gate circuit as described in claim 3, characterized in that, It also includes a first pull-up resistor, the number of which is equal to the number of the second controllable switches, and the first pull-up resistor, the second controllable switch and the input channel correspond one-to-one; The first end of each first pull-up resistor is connected to the power supply, and the second end of each first pull-up resistor is connected to the corresponding input channel. The first pull-up resistor is used to increase the voltage input to the input channel.
6. The multi-input channel AND gate circuit as described in claim 1 or 2, characterized in that, When the first controllable switch is a PNP transistor and the second controllable switch is an NPN transistor, it also includes an inverter. The number of inverters is equal to the number of the second controllable switches. The inverters, the second controllable switches and the input channels correspond one-to-one. The base of the PNP transistor serves as the control terminal of the first controllable switch, the emitter of the PNP transistor serves as the first terminal of the controllable switch, and the collector of the PNP transistor serves as the second terminal of the controllable switch. The base of each NPN transistor serves as the control terminal of the second controllable switch, the collector of each NPN transistor serves as the first terminal of the second controllable switch, and the emitter of each NPN transistor serves as the second terminal of the second controllable switch. The input terminal of each inverter is connected to the corresponding input channel, and the output terminal of each inverter is connected to the base of the corresponding NPN transistor. Each of the NPN transistors is turned off when the base input voltage is 0, and the PNP transistor is turned off when all of the NPN transistors are turned off.
7. The multi-input channel AND gate circuit as described in claim 6, characterized in that, It also includes a second pull-down resistor, the number of which is equal to the number of the second controllable switches, and the second pull-down resistor and the second controllable switch correspond one-to-one with the input channel; The first terminal of each second pull-down resistor is connected to the corresponding input channel, and the second terminal of each second pull-down resistor is grounded. The second pull-down resistor is used to pull down the voltage input to the input channel.
8. The multi-input channel AND gate circuit as described in claim 6, characterized in that, It also includes a second pull-up resistor, the number of which is equal to the number of the second controllable switches, and the second pull-up resistor and the second controllable switch correspond one-to-one with the input channel; The first end of each second pull-up resistor is connected to the power supply, and the second end of each second pull-up resistor is connected to the corresponding input channel. The second pull-up resistor is used to increase the voltage input to the input channel.
9. A signal processing apparatus, characterized in that, Includes the multi-input channel AND gate circuit as described in any one of claims 1 to 8.
10. A robot, characterized in that, The robot's robotic arm includes a signal processing device as described in claim 9, used to process the output signals of each sensor in the robotic arm.