Layout structure of semiconductor device
By introducing partially overlapping deep trench and shallow trench isolation regions, as well as rhomboid or elliptical deep trench auxiliary patterns in the semiconductor device layout, the problems of reduced pattern density and uneven etching in DTI structures are solved, achieving a more uniform etching effect.
Patent Information
- Application Number
- CN202423116444.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-12-17
AI Technical Summary
In high-voltage BCD process, as device complexity increases, the active area increases, and the DTI structure area also increases, resulting in reduced pattern density, inconsistent etching performance, and the DTI structure width is affected by the yellow light and etching load effect, resulting in a larger CD.
By employing partially overlapping deep trench isolation zones and shallow trench isolation zones, combined with several deep trench auxiliary patterns, especially rhomboid or elliptical deep trench auxiliary patterns, located in the shallow trench isolation zone and at least on one side of the deep trench isolation zone, the pattern density is increased and the etching performance is improved.
By increasing the pattern density, consistent etching performance was achieved at all locations within the etching surface of the isolation zone, avoiding any impact on the function of the deep trench isolation zone and improving the uniformity and precision of the etching.
Smart Images
Figure CN223567992U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a layout structure of a semiconductor device. Background Technology
[0002] As IC integration density increases, the market demands higher performance from BCD (Bipolar CMOS DMOS, monolithic integrated circuit technology) products. With increasing voltage requirements, the effective area needs to increase accordingly. To address this issue, DTI (Deep Trench Isolation) structures are adopted, which can achieve higher voltage withstand capabilities within a smaller lateral dimension.
[0003] As devices become increasingly complex, the area of the active region of the device becomes larger and larger. Since the DTI structure needs to surround the active region, the area of the DTI structure will become larger and larger. Figure 1 This is a schematic diagram of chip design and layout in existing technology. Please refer to it. Figure 1 Chip 10 includes several modules 20. Figure 1 The diagram illustrates four modules 20, typically high-voltage modules. Each module 20 includes an active region 21 and a DTI structure 22, with the DTI structure 22 surrounding the active region 21. As the area of the active region 22 increases, such as... Figure 1 The active region 21 of module 20, shown in the dashed box, has an increased area compared to the other modules 20. This corresponds to an increased area of the DTI structure 22 shown in the dashed box. Consequently, the number of modules 20 within a single chip 10 decreases, the pattern density of the DTI structure 22 decreases, and the distribution of the DTI structure 22 becomes uneven. This situation can result in a large area around the DTI structure 22 where there are no patterns (e.g., ...). Figure 1 (There is no graphic on the right side of the dashed box). At this time, the width of the DTI structure 22 will be affected by two factors. First, the optical effect of yellow light will cause the ADI (After Develop Inspection) CD (Critical Dimension) of the DTI structure 22 to be larger. Second, due to the etching loading effect, the AEI (After Etch Inspection) CD of the DTI structure 22 will also be larger. Figure 2 This is a schematic diagram of chip inspection after etching in existing technology. Please refer to it. Figure 2 ,because Figure 2 There are no graphics within a large distance of the two upper modules 20 (no graphics on the right side), which affects the width of the DTI structure 22. Specifically, the AEI CD of the DTI structure 22 is larger in the area near the region without graphics (e.g.,Figure 2 The above-mentioned influences will cause the etching performance of the DTI structure 22 at different positions in the etching surface to be inconsistent. Practical new type content
[0004] The utility model discloses a layout structure of semiconductor device, realize the etching performance of improvement isolation area.
[0005] In order to reach the above-mentioned purpose, the utility model provides a layout structure of semiconductor device, including:
[0006] Functional area;
[0007] Isolation area, surrounds the functional area, the isolation area includes the deep trench isolation area and shallow trench isolation area of partial overlap, and the deep trench isolation area and the shallow trench isolation area all surround the functional area;
[0008] A plurality of deep trench auxiliary patterns are located in the shallow trench isolation area and at least one side of the deep trench isolation area.
[0009] Optionally, the shape of the deep trench auxiliary pattern includes a rhombus or an ellipse.
[0010] Optionally, when the deep trench auxiliary pattern is a rhombus, a short diagonal line of the deep trench auxiliary pattern is less than the width of the deep trench isolation area; when the deep trench auxiliary pattern is an ellipse, a minor axis of the deep trench auxiliary pattern is less than the width of the deep trench isolation area.
[0011] Optionally, the shallow trench isolation area includes a first shallow trench isolation area and a second shallow trench isolation area, the first shallow trench isolation area and the second shallow trench isolation area sequentially surround the functional area from inside to outside, and a gap is arranged between the first shallow trench isolation area and the second shallow trench isolation area, and the deep trench isolation area partially overlaps the first shallow trench isolation area and the second shallow trench isolation area.
[0012] Optionally, the deep trench auxiliary pattern is located in the first shallow trench isolation area and at one side of the deep trench isolation area close to the functional area.
[0013] Optionally, the deep trench auxiliary pattern is located in the second shallow trench isolation area and at one side of the deep trench isolation area away from the functional area.
[0014] Optionally, the deep trench auxiliary pattern is located in the first shallow trench isolation area and the second shallow trench isolation area and at both sides of the deep trench isolation area.
[0015] Optionally, a plurality of deep trench auxiliary patterns are arranged in a ring shape.
[0016] Optionally, the interval between two adjacent deep trench auxiliary patterns is the same.
[0017] Optionally, a gap is formed between the deep trench auxiliary pattern and the deep trench isolation region.
[0018] In the layout structure of the semiconductor device, the isolation region surrounds the functional region, the isolation region comprises a deep trench isolation region and a shallow trench isolation region which are partially overlapped, and the deep trench isolation region and the shallow trench isolation region both surround the functional region, and the plurality of deep trench auxiliary patterns are located in the shallow trench isolation region and at least on one side of the deep trench isolation region. The plurality of deep trench auxiliary patterns are located in the shallow trench isolation region and at least on one side of the deep trench isolation region, so that the pattern density of the isolation region is increased, the etching performance of the isolation region is improved, the etching performance of each position in the etching surface of the isolation region is consistent, and the plurality of deep trench auxiliary patterns are located in the shallow trench isolation region and do not affect the function of the deep trench isolation region. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 It is a schematic diagram of a chip in the prior art when a layout is designed.
[0020] Figure 2 It is a schematic diagram of a chip in the prior art when etching is detected.
[0021] Figures 3-5 It is a schematic diagram of the layout structure of the semiconductor device provided by an embodiment of the utility model.
[0022] Wherein, Figure 1 And Figure 2 The reference signs are:
[0023] 10-chip; 20-module; 21-active region; 22-DTI structure.
[0024] Figures 3-5 The reference signs are:
[0025] 100-functional region; 200-isolation region; 210-deep trench isolation region; 220-shallow trench isolation region; 221-first shallow trench isolation region; 222-second shallow trench isolation region; 300-deep trench auxiliary pattern. DETAILED DESCRIPTION
[0026] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.
[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present application.
[0028] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly understood by those skilled in the art, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0029] In addition, the relational terms such as "first" and "second" and the like are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the article or device including the element. The above terms can be specifically understood in the context of the present application.
[0030] Figures 3-5 The schematic diagram of the layout structure of the semiconductor device provided in the present embodiment is shown in FIG. 1. Please refer to Figures 3-5The embodiment provides a layout structure of a semiconductor device, which comprises a functional area 100, an isolation area 200 and a plurality of deep trench auxiliary patterns 300. The functional area 100 comprises a device structure (not shown in the figure), and the isolation area 200 is used for high-voltage devices. The isolation area 200 surrounds the functional area 100 to realize device isolation. The isolation area 200 comprises a partially-overlapped deep trench isolation area 210 and a shallow trench isolation area 220 (in order to clearly show that the deep trench isolation area 210 and the shallow trench isolation area 220 are partially overlapped, the deep trench isolation area 210 is set to be transparent in the figure), and both the deep trench isolation area 210 and the shallow trench isolation area 220 surround the functional area 100. The deep trench isolation area 210 and the shallow trench isolation area 220 are prepared by first forming a shallow trench, then filling insulating material in the shallow trench to form the shallow trench isolation area 220, etching the shallow trench isolation area 220 to form a deep trench in the shallow trench isolation area 220, which divides the shallow trench isolation area 220 into two parts, then forming an insulating layer on the sidewall of the deep trench, and filling semiconductor material (for example, polysilicon or amorphous silicon) in the deep trench to form the deep trench isolation area 210.
[0031] In the embodiment, the shallow trench isolation area 220 comprises a first shallow trench isolation area 221 and a second shallow trench isolation area 222, and the first shallow trench isolation area 221 and the second shallow trench isolation area 222 successively surround the functional area 100 from inside to outside (from the functional area 100 to outside). Specifically, the first shallow trench isolation area 221 is in contact with the functional area 100 and surrounds the functional area 100, and the second shallow trench isolation area 222 surrounds the first shallow trench isolation area 221, and the first shallow trench isolation area 221 and the second shallow trench isolation area 222 have a gap S1. As viewed from the top (Fig. 1), Figures 3-5 )As viewed from the top, the deep trench isolation area 210, the first shallow trench isolation area 221 and the second shallow trench isolation area 222 are all annular. As viewed from the cross section, the cross section of the deep trench isolation area 210 is in the shape of an inverted trapezoid. As viewed from each direction of the top, the deep trench isolation area 210 is partially overlapped with the first shallow trench isolation area 221 and the second shallow trench isolation area 222. Specifically, the deep trench isolation area 210 is partially overlapped with the outer side of the first shallow trench isolation area 221 and the inner side of the second shallow trench isolation area 222. The outer side of the first shallow trench isolation area 221 is the side of the first shallow trench isolation area 221 close to the second shallow trench isolation area 222, and the inner side of the second shallow trench isolation area 222 is the side of the second shallow trench isolation area 222 close to the first shallow trench isolation area 221.
[0032] Several deep trench auxiliary patterns 300 are located in the shallow trench isolation region 220 and at least on one side of the deep trench isolation region 210. In this embodiment, the shape of the deep trench auxiliary pattern 300 includes a rhombus or an ellipse (only the rhombus is shown in the figure, and when the shape of the deep trench auxiliary pattern 300 is an ellipse, the arrangement is also as shown in the rhombus), the short diagonal of the rhombus or the short axis of the ellipse is shorter than the side length of other shapes (such as a square), and the area of the rhombus or the ellipse is smaller than that of other shapes with the same perimeter, and the effective area of the chip is less occupied. When the deep trench auxiliary pattern 300 is a rhombus, the short diagonal S3 of the deep trench auxiliary pattern 300 is smaller than the width S2 of the deep trench isolation region 210; when the deep trench auxiliary pattern 300 is an ellipse, the short axis of the deep trench auxiliary pattern 300 is smaller than the width S2 of the deep trench isolation region 210. By controlling the short diagonal S3 of the deep trench auxiliary pattern 300 or the short axis of the deep trench auxiliary pattern 300 to be smaller than the width S2 of the deep trench isolation region 210, under the influence of the etching load effect, the depth of the deep trench auxiliary pattern 300 will be smaller than the depth of the deep trench isolation region 210, and in this embodiment, the depth of the deep trench isolation region 210 can be greater than 20 μm, preferably greater than 30 μm, and the depth of the deep trench isolation region 210 is greater than the depth of the deep trench auxiliary pattern 300 and the shallow trench isolation region 220; and the deep trench auxiliary pattern 300 is located in the shallow trench isolation region 220, and the deep trench auxiliary pattern 300 will not affect the function of the deep trench isolation region 210.
[0033] In this embodiment, referring to Figure 3 , the deep trench auxiliary pattern 300 is located in the second shallow trench isolation region 222 and on the side of the deep trench isolation region 210 away from the functional region 100. Referring to Figure 4 , the deep trench auxiliary pattern 300 is located in the first shallow trench isolation region 221 and on the side of the deep trench isolation region 210 close to the functional region 100. Referring to Figure 5 , the deep trench auxiliary pattern 300 is located in the first shallow trench isolation region 221 and the second shallow trench isolation region 222 and on both sides of the deep trench isolation region 210.
[0034] In this embodiment, the deep trench auxiliary patterns 300 are arranged in a ring shape, referring to Figure 3 , the deep trench auxiliary patterns 300 are arranged in a ring shape and surround the adjacent deep trench isolation region 210; referring to Figure 4 , the deep trench auxiliary patterns 300 are arranged in a ring shape and surround the adjacent functional region 100; referring to Figure 5, the deep trench auxiliary patterns 300 are arranged in two rings, one of which surrounds the adjacent deep trench isolation region 210, and the other of which surrounds the adjacent functional region 100. In the embodiment, the distance between the two adjacent deep trench auxiliary patterns 300 is preferably the same, which is beneficial to the preparation and control of the pattern density; and the deep trench auxiliary pattern 300 and the deep trench isolation region 210 have a gap therebetween, so as to avoid the influence of the deep trench auxiliary pattern 300 on the deep trench isolation region 210. In the embodiment, by arranging the deep trench auxiliary patterns 300 in the shallow trench isolation region 220 and at least on one side of the deep trench isolation region 210, the pattern density of the isolation region 200 can be increased, the etching performance of the isolation region 200 is improved, and the etching performance of each position in the etching surface of the isolation region 200 is consistent.
[0035] In conclusion, in the layout structure of the semiconductor device provided by the utility model, it comprises a functional region, an isolation region and a plurality of deep trench auxiliary patterns, wherein the isolation region surrounds the functional region, the isolation region comprises a deep trench isolation region and a shallow trench isolation region which are partially overlapped, and the deep trench isolation region and the shallow trench isolation region both surround the functional region, and the plurality of deep trench auxiliary patterns are located in the shallow trench isolation region and at least on one side of the deep trench isolation region. The utility model can increase the pattern density of the isolation region, improve the etching performance of the isolation region, and make the etching performance of each position in the etching surface of the isolation region consistent by arranging the plurality of deep trench auxiliary patterns in the shallow trench isolation region and at least on one side of the deep trench isolation region; and the plurality of deep trench auxiliary patterns in the shallow trench isolation region will not affect the function of the deep trench isolation region.
[0036] The above is only the preferred embodiment of the utility model, and does not limit the utility model in any way. Any person skilled in the art, without departing from the technical scheme of the utility model, can make any form of equivalent replacement or modification of the technical scheme and technical content disclosed by the utility model, and the variation still belongs to the protection scope of the utility model.
Claims
1. A layout structure of a semiconductor device, characterized by, The application relates to a semiconductor structure, comprising: a functional region; an isolation region surrounding the functional region, the isolation region comprising a partially-overlapped deep trench isolation region and a shallow trench isolation region, and the deep trench isolation region and the shallow trench isolation region both surrounding the functional region; a plurality of deep trench auxiliary patterns located in the shallow trench isolation region and at least on one side of the deep trench isolation region.
2. The layout structure of a semiconductor device according to claim 1, wherein The shape of the deep trench auxiliary pattern comprises a rhombus or an ellipse.
3. The layout structure of a semiconductor device according to claim 2, wherein When the deep trench auxiliary pattern is a rhombus, the short diagonal of the deep trench auxiliary pattern is smaller than the width of the deep trench isolation region; when the deep trench auxiliary pattern is an ellipse, the minor axis of the deep trench auxiliary pattern is smaller than the width of the deep trench isolation region.
4. The layout structure of a semiconductor device according to claim 1, wherein The shallow trench isolation region comprises a first shallow trench isolation region and a second shallow trench isolation region, the first shallow trench isolation region and the second shallow trench isolation region successively surrounding the functional region from inside to outside, and the first shallow trench isolation region and the second shallow trench isolation region having a gap therebetween, and the deep trench isolation region partially overlapping the first shallow trench isolation region and the second shallow trench isolation region.
5. The layout structure of a semiconductor device according to claim 4, wherein The deep trench auxiliary pattern is located in the first shallow trench isolation region and on one side of the deep trench isolation region close to the functional region.
6. The layout structure of a semiconductor device according to claim 4, wherein The deep trench auxiliary pattern is located in the second shallow trench isolation region and on one side of the deep trench isolation region away from the functional region.
7. The layout structure of a semiconductor device according to claim 4, wherein The deep trench auxiliary pattern is located in the first shallow trench isolation region and the second shallow trench isolation region and on both sides of the deep trench isolation region.
8. The layout structure of a semiconductor device according to claim 1, wherein The plurality of deep trench auxiliary patterns are arranged in a ring shape.
9. The layout structure of a semiconductor device according to claim 8, wherein The distance between two adjacent deep trench auxiliary patterns is the same.
10. The layout structure of a semiconductor device according to claim 1, wherein The deep trench auxiliary pattern and the deep trench isolation region have a gap therebetween.