Rapid control power supply system architecture based on DSP and FPGA

Abstract

The utility model discloses a DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array)-based rapid control power supply system architecture, which comprises a bottom plate, an empty chip substrate, an FPGA control system and a DSP control system, the empty chip substrate is arranged on the bottom plate, the FPGA control system and the DSP control system are arranged on the bottom plate or the empty chip substrate, and the DSP control system is arranged on the FPGA control system and the DSP control system. The FPGA control system interacts with the DSP control system through an XINTF bus, an XA address bus and an XD data bus, and the DSP control system comprises a DSP logic control output conversion circuit; according to the utility model, the FPGA is used to carry out reverse solution and filtering on a large amount of data so as to share DSP storage and operation space resources, and the DSP is used to carry out rapid logic operation so as to meet the requirement of a system for rapidly controlling a DC / DC conversion switch tube, so that the stability and rapidity of the rapid power supply DC / DC converter are improved; the problems of stable operation of the rapid power supply, rapid data processing and rapid main power logic control are solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of quick power DC / DC conversion control, in particular to a kind of quick control power system architecture based on DSP and FPGA. BACKGROUND

[0002] With the actual demand of DC / DC converter stability and rapidity, some conventional single ARM, single FPGA and single DSP control system architecture cannot meet a large amount of data processing, fault data storage, communication, voltage value and current value rapid calculation, PID control and fast feedforward to realize voltage loop and current loop logic control main function, in order to ensure that the control system can be stably operated, and also can realize the function of main power conversion rapid control, a kind of quick control power system architecture based on DSP and FPGA is proposed. UTILITY MODEL CONTENT

[0003] The utility model aims at providing a kind of quick control power system architecture based on DSP and FPGA, to solve the problems presented in the above background technology.

[0004] To achieve the above object, the utility model provides the following technical scheme: a kind of quick control power system architecture based on DSP and FPGA, including bottom plate, empty chip matrix, FPGA control system and DSP control system, the empty chip matrix is set on bottom plate, the FPGA control system and DSP control system are installed on bottom plate or empty chip matrix, the FPGA control system and DSP control system are interacted by XINTF bus, division XA address bus, XD data bus, and DSP control system includes DSP logic control output conversion circuit, the DSP logic control output conversion circuit is controlled conversion circuit by control drive enable port, the DSP logic control output conversion circuit includes DSP chip, and the output end of DSP chip exports power PWM wave.

[0005] Further, the output end of the DSP logic control output conversion circuit exports PWM signal output signal to actuator.

[0006] Further, the resistance R1, resistance R2, resistance R3 are connected in parallel between the OE pin and the DIR pin of the DSP chip, and four groups of capacitors are connected in parallel to the VCC pin end of the DSP chip.

[0007] The beneficial effects of this utility model are as follows: This utility model uses FPGA to perform reverse calculation and filtering on a large amount of data to share the storage and running space resources of DSP, and uses DSP to perform fast logic operations to solve the system's need for fast control of DC / DC converter switching transistors, so as to achieve the purpose of fast high voltage absorption and low voltage charging of busbars, ensuring the stable operation and fast control of the power conversion control system, improving the stability and speed of the fast power DC / DC converter, and solving the problems of stable operation of fast power supply, fast data processing, and fast main power logic control. Attached Figure Description

[0008] Fig. 1 This is a circuit diagram of the DSP logic control output conversion circuit of this utility model;

[0009] Fig. 2 This is a schematic diagram of the principle of this utility model.

[0010] In the diagram: 1 DSP control system, 11 DSP logic control output conversion circuit, 111 DSP chip, 2 FPGA control system, 3 baseboard, 4 empty chip substrate. Detailed Implementation

[0011] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0012] Please see Figs. 1-2This invention provides a technical solution for a fast-control power supply system architecture based on DSP and FPGA, including a base plate 3, a blank chip substrate 4, an FPGA control system 2, and a DSP control system 1. The blank chip substrate 4 is mounted on the base plate 3. The FPGA control system 2 and the DSP control system 1 are mounted on the base plate 3 or the blank chip substrate 4. The FPGA control system 2 and the DSP control system 1 interact through the XINTF bus, the XA address bus, and the XD data bus. The DSP control system 1 includes a DSP logic control output conversion circuit 11, which controls the conversion circuit through a control drive enable port. The DSP logic control output conversion circuit 11 includes a DSP chip 111, and the output terminal of the DSP chip 111 outputs a power PWM wave. The output terminal of the DSP logic control output conversion circuit 11 outputs a signal to the actuator through the PWM signal. Resistors R1, R2, and R3 are connected in parallel between the OE pin and the DIR pin of the DSP chip 111, and four sets of capacitors are connected in parallel between the VCC pin of the DSP chip 111.

[0013] In this embodiment, the DSP and FPGA-based fast control power supply system architecture, to meet the requirements of reverse computation and filtering of analog data, connects a specific I / O port of the FPGA control system 2 and an external ADC bus port with a 16-bit data connection. This enables the acquired data to be transmitted to the FPGA control system 2 in parallel via a bus. All data is then processed in parallel within the FPGA control system 2. Key data is transmitted to the DSP control system 1 via the XINTF bus, while other data, non-main control logic data, and other data information are stored in the external Flash memory of the FPGA control system 2. The DSP control system 1 and the FPGA control system 2 are connected via XINTF... The INTF bus is divided into an XA address bus and an XD data bus for data addressing and transmission. It has a 32-bit floating-point digital computing capability and a DSP with a single instruction execution cycle of up to 6.7ns. It performs fast logic operations and logic control on key analog quantities transmitted in parallel from the FPGA control system 2 and outputs them directly through the PWM interface. At the same time, the DSP logic control output conversion circuit 11 is configured to output signals to the actuator. Since the FPGA is a logic gate array with a multi-threaded parallel working mode, its working stability is extremely high. Therefore, the designed external watchdog circuit only resets the DSP chip 111. The DSP control system 1 can be reset by external device failure and can quickly control the switching of the main power within 2ms.

[0014] The DSP logic control output conversion circuit 11 controls the operation of the conversion circuit through the control drive enable port, converting the 3.3V drive PWM wave into a 5V power supply PWM wave with stronger drive capability. Finally, corresponding pull-up and pull-down resistors are set on the PWM control line to adapt to the non-triggering malfunction of the control signal in the initial state and working state. The highly stable FPGA is used to perform reverse calculation and filtering on the acquired data, and the key analog data is quickly transmitted to the DSP via XINTF parallel communication. The DSP performs fast calculation and logic control on the key data, which mainly involves FPGA peripheral storage, bus transmission, and DSP signal output circuit.

[0015] In summary, this DSP and FPGA-based fast power supply system architecture is used to control the fast DC / DC converter. The FPGA performs inverse calculations and filtering on large amounts of data, sharing the storage and runtime space resources of the DSP. Furthermore, the DSP performs fast logic operations to meet the system's need for rapid control of the DC / DC converter switching transistors, achieving rapid high-voltage absorption and low-voltage charging of the busbars. The highly stable FPGA, capable of calculating high-precision floating-point numbers, is used for data processing and storage. The DSP performs fast logic calculations and control. The DSP control system 1 and the FPGA control system 2 enhance the stability and speed of the fast DC / DC converter.

[0016] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0017] The above embodiments only illustrate preferred embodiments of the present utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be understood that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present utility model, and these all fall within the protection scope of the present utility model. In the present utility model, unless otherwise explicitly specified and limited, the terms "installation", "connection", "joining", "fixing", etc. should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components. Among them, there are various ways of detachable installation, such as by plugging and snapping, or by bolt connection, etc.

[0018] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A fast power supply system architecture based on DSP and FPGA, characterized in that: It includes a bottom plate, a hollow chip base, an FPGA control system and a DSP control system, the hollow chip base is arranged on the bottom plate, the FPGA control system and the DSP control system are installed on the bottom plate or the hollow chip base, the FPGA control system and the DSP control system interact through an XINTF bus, a XA address bus and an XD data bus, the DSP control system comprises a DSP logic control output conversion circuit, the DSP logic control output conversion circuit controls a conversion circuit through a control driving enable port, the DSP logic control output conversion circuit comprises a DSP chip, and an output end of the DSP chip outputs a power supply PWM wave.

2. The DSP and FPGA-based fast control power supply system architecture of claim 1, wherein: An output end of the DSP logic control output conversion circuit outputs a PWM signal to an actuator.

3. The DSP and FPGA based fast control power supply system architecture of claim 1, wherein: The OE pin and the DIR pin of the DSP chip are connected in parallel with a resistor R1, a resistor R2 and a resistor R3, and the VCC pin end of the DSP chip is connected in parallel with four groups of capacitors.

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