Flip LED chip
By setting an attachment enhancement layer in the flip-chip and creating pits on it, the contact area between the pad electrode layer and the attachment enhancement layer is increased, solving the problem of pad electrode detachment and improving the stability and reliability of the chip.
Patent Information
- Application Number
- CN202520281545.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2035-02-21
AI Technical Summary
The pad electrodes of flip-chip LEDs are prone to detachment, resulting in poor chip reliability.
An adhesion reinforcement layer is provided between the contact electrode layer and the pad electrode layer. The adhesion reinforcement layer has pits. The pad electrode layer is deposited in the pits and on the adhesion reinforcement layer. The uneven structure of the adhesion reinforcement layer increases the contact area between the pad electrode layer and the adhesion reinforcement layer, thereby improving the bonding strength.
The mechanical bonding between the pad electrode layer and the attached reinforcement layer is enhanced, avoiding detachment due to stress mismatch or loose bonding, and improving the stability and reliability of flip-chip LEDs.
Smart Images
Figure CN223584645U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor, especially relates to a flip LED chip. BACKGROUND
[0002] The flip LED chip becomes the current mainstream LED chip development direction because of its superior heat dissipation performance, compact structure design and excellent optical performance. The electrode of the flip LED chip needs to be designed into a large-area solder pad structure and is inverted and welded on the solder pad of the corresponding substrate. If the light emitted by the active region does not pass through the treatment and directly reaches the welding area, most of the light will be absorbed by the bottom welding material and cannot escape, so it is necessary to set a reflective passivation layer to reflect the light and emit it from the side far away from the welding area. However, the electrode of the flip LED chip is a metal material, the reflective passivation layer is an oxide material and the surface is flat. In the use process, the electrode metal material and the reflective passivation layer often fall off because of insufficient adhesion between them, thereby causing the flip LED chip to fail. SUMMARY
[0003] The technical problem to be solved by the utility model lies in providing a flip LED chip, reducing the probability of solder pad electrode falling off and improving the reliability of the flip LED chip.
[0004] In order to solve the above technical problem, the utility model provides a flip LED chip, which comprises a substrate and an epitaxial layer, a current blocking layer, a transparent conductive layer, a contact electrode layer, a reflective passivation layer, an adhesion enhancement layer and a solder pad electrode layer arranged on the substrate in sequence; the reflective passivation layer and the adhesion enhancement layer are provided with a through hole, the solder pad electrode layer is connected with the contact electrode layer through the through hole; and the side of the adhesion enhancement layer close to the solder pad electrode layer is provided with a pit.
[0005] As an improvement of the above scheme, the pit is arranged in the projection area of the solder pad electrode layer on the adhesion enhancement layer.
[0006] As an improvement of the above scheme, at least two pits are arranged along the length direction and / or the width direction of the adhesion enhancement layer.
[0007] As an improvement of the above scheme, the depth of the pit is 20nm-500nm.
[0008] As an improvement of the above scheme, the width of the opening of the pit is 3um-20um.
[0009] As an improvement of the above scheme, the distance between the adjacent pits is 3um-20um.
[0010] As the improvement of the above-mentioned scheme, the thickness of the adhesion enhancement layer at the position without the recess is 0.5-1.5 microns.
[0011] As the improvement of the above-mentioned scheme, the recess sidewall of the adhesion enhancement layer has a preset angle with the horizontal plane, and the preset angle is 120-150 degrees.
[0012] As the improvement of the above-mentioned scheme, the total area of the recess accounts for 45-65% of the projection area of the pad electrode layer on the adhesion enhancement layer.
[0013] As the improvement of the above-mentioned scheme, the adhesion enhancement layer is one or more of SiO2 layer, TiO2 layer, Si3N4 layer and Al2O3 layer.
[0014] The present application has the following beneficial effects:
[0015] The present application sets the adhesion enhancement layer between the contact electrode layer and the pad electrode layer, the upper surface of the adhesion enhancement layer is provided with the recess, the pad electrode layer is deposited in the recess of the adhesion enhancement layer and on the adhesion enhancement layer, the contact area of the pad electrode layer and the adhesion enhancement layer is increased, the mechanical engagement is enhanced, the pad electrode layer can be prevented from falling off due to the stress mismatch or the loose combination in the use process, and thus the stability and reliability of the flip LED chip in the use process are improved. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 is the structure schematic view of the flip LED chip provided by the present application;
[0017] Figure 2 is the top view structure schematic view of the flip LED chip before the pad electrode layer is set by the present application;
[0018] Figure 3 is Figure 1 the enlarged view of A part of DETAILED DESCRIPTION
[0019] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings. It is hereby declared that the up, down, left, right, front, back, inner and outer directions of the present application appearing or about to appear in the text are based on the drawings of the present application, and are not the specific limitation of the present application.
[0020] As Figures 1 to 3The utility model discloses an inverted LED chip, including substrate 1 and the epitaxial layer 2, current barrier layer 3, transparent conductive layer 4, contact electrode layer, reflection passivation layer 6, attachment enhancement layer 7 and pad electrode layer that are equipped on substrate 1 in proper order, the reflection passivation layer 6 and attachment enhancement layer 7 are equipped with through -hole 71, and the pad electrode layer is connected with contact electrode layer through through -hole 71, and the one side of attachment enhancement layer 7 is close to pad electrode layer and is equipped with pit 72.
[0021] The utility model discloses an inverted LED chip, including substrate 1 and the epitaxial layer 2, current barrier layer 3, transparent conductive layer 4, contact electrode layer, reflection passivation layer 6, attachment enhancement layer 7 and pad electrode layer that are equipped on substrate 1 in proper order, the reflection passivation layer 6 and attachment enhancement layer 7 are equipped with through -hole 71, and the pad electrode layer is connected with contact electrode layer through through -hole 71, and the one side of attachment enhancement layer 7 is close to pad electrode layer and is equipped with pit 72.
[0022] It can be understood that the pit 72 is arranged in the projection area of the pad electrode layer on the attachment enhancement layer 7, so that the bonding force between the pad electrode layer and the attachment enhancement layer 7 is improved, and the remaining area of the attachment enhancement layer 7 is a smooth surface structure, which can reduce the preparation difficulty and improve the preparation efficiency while ensuring the bonding force between the pad electrode layer and the attachment enhancement layer 7.
[0023] Specifically, the pit 72 is arranged in at least two along the length direction and / or width direction of the attachment enhancement layer 7, so as to ensure the bonding strength between the pad electrode layer and the attachment enhancement layer 7.
[0024] It can be understood that the shape, size and distribution of the pit 72 have a significant influence on improving the adhesion of the pad electrode layer. In a preferred embodiment, the depth d of the pit 72 is 20-500 nm, and the exemplary values are 50 nm, 100 nm, 200 nm, 300 nm or 400 nm, but not limited to this. If the depth d of the pit 72 is less than 20 nm, the bonding between the pad electrode layer and the attachment enhancement layer 7 is weak, and it is difficult to avoid the occurrence of the pad electrode layer falling off; if the depth d of the pit 72 is greater than 500 nm, the overall thickness of the attachment enhancement layer 7 needs to be increased accordingly, which is not conducive to the miniaturization of the inverted LED chip.
[0025] In a preferred embodiment, the width l of the opening of the recess 72 is 3 μm to 20 μm, and is exemplarily 5 μm, 8 μm, 10 μm, 14 μm or 18 μm, but is not limited thereto. If the width l of the opening of the recess 72 is less than 3 μm, the contact area of the pad electrode layer and the adhesion enhancement layer 7 is small; if the width l of the opening of the recess 72 is greater than 20 μm, the number of the recesses 72 on the adhesion enhancement layer 7 is correspondingly reduced, which is also not conducive to the increase of the bonding strength of the pad electrode layer and the adhesion enhancement layer 7.
[0026] In a preferred embodiment, the distance s between adjacent recesses 72 is 3 μm to 20 μm, and is exemplarily 5 μm, 8 μm, 10 μm, 14 μm or 18 μm, but is not limited thereto. Controlling the distance s between adjacent recesses 72 within the preferred range can further improve the bonding strength of the pad electrode layer and the adhesion enhancement layer 7.
[0027] In a preferred embodiment, the thickness h of the adhesion enhancement layer 7 at the position without the recess 72 is 0.5 μm to 1.5 μm, and is exemplarily 0.6 μm, 0.8 μm, 1 μm, 1.2 μm or 1.4 μm, but is not limited thereto. On the premise of not affecting the performance of the chip, the bonding strength of the pad electrode layer and the adhesion enhancement layer 7 is effectively improved.
[0028] It can be understood that the recess 72 can be a straight recess 72 or an inclined recess 72. In a preferred embodiment, the recess 72 side wall of the adhesion enhancement layer 7 has a preset angle α with the horizontal plane, and the preset angle α is 120° to 150°, and is exemplarily 125°, 130°, 135°, 140° or 145°, but is not limited thereto. The structure of the recess 72 with an inclined side wall can increase the contact area of the pad electrode layer and the adhesion enhancement layer 7, and further ensure the firmness of the bonding of the pad electrode layer and the adhesion enhancement layer 7.
[0029] The total area of the recess 72 accounts for 45% to 65% of the projection area of the pad electrode layer on the adhesion enhancement layer 7, and is exemplarily 48%, 50%, 55%, 58% or 60%, but is not limited thereto. If the total area of the recess 72 is too small, the pad electrode layer cannot be closely combined with the adhesion enhancement layer 7; if the total area of the recess 72 is too large, it may have an adverse effect on the strength of the adhesion enhancement layer 7.
[0030] In order to ensure the performance of the flip LED chip, the adhesion enhancement layer 7 is an insulating layer. In a preferred embodiment, the adhesion enhancement layer 7 is one or more of a SiO2 layer, a TiO2 layer, a Si3N4 layer and an Al2O3 layer, but is not limited thereto.
[0031] It can be understood that the shape of the recess 72 can be one or more of a cylindrical type, a prism type, a circular truncated cone type, and a trapezoidal truncated cone type, but is not limited thereto, and the specific shape of the recess 72 can be selected according to actual conditions.
[0032] In addition to the adhesion enhancement layer 7, the other layered structures of the flip LED chip provided in the embodiments of the present application are as follows.
[0033] The substrate 1 can be selected from one of a sapphire substrate, a SiC substrate, a ZnO substrate, and a Si substrate, but is not limited thereto.
[0034] The epitaxial layer 2 includes, but is not limited to, a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23 deposited on the substrate 1 in sequence. The first semiconductor layer 21 can be an N-type GaN layer or an N-type AlGaN layer, but is not limited thereto, has a thickness of 3 μm to 8 μm, and an N-type doping concentration of 5×10 18 cm -3 ~ 1×10 19 cm -3 The multiple quantum well layer 22 can be one of an InGaN / GaN multiple quantum well layer 22, an InGaN / AlGaN multiple quantum well layer, and an AlGaN / AlGaN multiple quantum well layer, but is not limited thereto, has a thickness of 50 nm to 300 nm. The second semiconductor layer 23 can be a P-type GaN layer or a P-type AlGaN layer, but is not limited thereto, has a thickness of 200 nm to 300 nm, and a P-type doping concentration of 5×10 17 cm -3 ~ 1×10 20 cm -3 .
[0035] The current blocking layer 3 can be one or more of a SiO2 layer, an Al2O3 layer, a Si3N4 layer, and a TiO2 layer, but is not limited thereto, and has a thickness of 100 nm to 500 nm.
[0036] The transparent conductive layer 4 can be one or more of an ITO layer, a ZnO layer, an AZO layer, and an FTO layer, but is not limited thereto, and has a thickness of 10 nm to 150 nm.
[0037] The contact electrode layer includes a first contact electrode layer 51 and a second contact electrode layer 52, the first contact electrode layer 51 is arranged on the first semiconductor layer 21, and the second contact electrode layer 52 is arranged on the second semiconductor layer 23. The material of the contact electrode layer can be one or more of Cr, Al, Ti, Pt, Ni, Au, Cu, and Ag.
[0038] The flip LED chip usually adopts a distributed Bragg reflector structure of insulating oxide as the reflective passivation layer 6. The reflective passivation layer 6 is a periodic structure layer formed by alternately growing two different refractive index materials, and the growth period can be 5-15. The material of the reflective passivation layer 6 can be one or more of SiO2, Al2O3, Si3N4 and TiO2, but is not limited thereto. For example, the reflective passivation layer 6 can be a SiO2 / Ti3O5 reflective passivation layer or a SiO2 / TiO2 reflective passivation layer. Compared with a traditional metal material (such as Al or Ag) as a reflector, the DBR reflective passivation layer has higher reflectivity.
[0039] The pad electrode layer includes a first pad electrode layer 81 and a second pad electrode layer 82, the first pad electrode layer 81 is arranged above the first contact electrode layer 51 and electrically connected with the first contact electrode layer 51, and the second pad electrode layer 82 is arranged above the second contact electrode layer 52 and electrically connected with the second contact electrode layer 52. The material of the pad electrode layer can be one or more of Cr, Al, Ti, Pt, Ni, Au, Cu and Ag, and the composition of the pad electrode layer can be the same as or different from that of the contact electrode layer.
[0040] The embodiments of the utility model will be further described in combination with the preparation method.
[0041] S1, epitaxial layer 2 is grown on substrate 1, after completion, through yellow light and dry etching, first semiconductor layer 21 is exposed, and cutting channel is formed;
[0042] S2, through yellow light and dry etching, isolation groove is formed at cutting channel position;
[0043] S3, the current blocking layer material is deposited, and the current blocking layer 3 is formed on the second semiconductor layer 23 by yellow light and wet etching;
[0044] S4, the transparent conductive layer material is deposited, and the transparent conductive layer 4 is formed on the second semiconductor layer 23 and the current blocking layer 3 by yellow light and wet etching;
[0045] S5, through yellow light and metal plating equipment, contact electrode layer is prepared;Wherein first contact electrode layer 51 is located on first semiconductor layer 21, and second contact electrode layer 52 is located on transparent conductive layer 4, and second contact electrode layer 52 is arranged directly above current blocking layer 3;
[0046] S6, the reflective passivation layer 6 is deposited on the above structure;
[0047] S7, the adhesion enhancement layer 7 is deposited on the reflective passivation layer 6;
[0048] S8, at the positions corresponding to the first contact electrode layer 81 and the second contact electrode layer 82, through yellow light and dry etching, a through hole 71 penetrating the reflection passivation layer 6 and the adhesion enhancement layer 7 is formed, and the first contact electrode layer 51 and the second contact electrode layer 52 are exposed respectively;
[0049] S9, at the positions corresponding to the pad electrode layer, through yellow light and dry etching, a recess 72 is formed on the surface of the adhesion enhancement layer 7;
[0050] S10, through yellow light and metal plating equipment, the pad electrode layer is prepared; wherein the first pad electrode layer 81 is arranged above the first contact electrode layer 51 and is electrically connected with the first contact electrode layer 51, and the second pad electrode layer 82 is arranged above the second contact electrode layer 52 and is electrically connected with the second contact electrode layer 52.
[0051] The preferred embodiments of the present application are described above, and it should be pointed out that, for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements are also considered to be within the protection scope of the present application.
Claims
1. A flip-chip LED, characterized in that, The device includes a substrate and an epitaxial layer, a current blocking layer, a transparent conductive layer, a contact electrode layer, a reflective passivation layer, an adhesion enhancement layer, and a pad electrode layer sequentially disposed on the substrate. The reflective passivation layer and the adhesion enhancement layer are provided with vias, and the pad electrode layer is connected to the contact electrode layer through the vias. The adhesion enhancement layer is provided with a pit on the side near the pad electrode layer.
2. The flip-chip LED as described in claim 1, characterized in that, The recess is located within the projection area of the pad electrode layer on the adhesion reinforcement layer.
3. The flip-chip LED as described in claim 1, characterized in that, At least two pits are provided along the length and / or width direction of the attachment reinforcement layer.
4. The flip-chip LED as described in claim 1, characterized in that, The depth of the pit is 20nm to 500nm.
5. The flip-chip LED as described in claim 1, characterized in that, The width of the opening of the pit is 3μm to 20μm.
6. The flip-chip LED as described in claim 1, characterized in that, The distance between adjacent pits is 3μm to 20μm.
7. The flip-chip LED as described in claim 1, characterized in that, The thickness of the adhesion reinforcement layer in areas without recesses is 0.5 μm to 1.5 μm.
8. The flip-chip LED as described in claim 1, characterized in that, The recessed sidewall of the attached reinforcing layer has a preset angle with the horizontal plane, the preset angle being 120° to 150°.
9. The flip-chip LED as described in claim 2, characterized in that, The total area of the pits accounts for 45% to 65% of the projected area of the pad electrode layer on the adhesion reinforcement layer.
10. The flip-chip LED as described in claim 1, characterized in that, The adhesion enhancement layer is one or more of the following: SiO2 layer, TiO2 layer, Si3N4 layer, and Al2O3 layer.