Adapter plate and test equipment
By setting specific pads and circuit coupling on the adapter board, the problem of signal interference on the adapter board was solved, and stable transmission and accurate testing of high-frequency signals were achieved.
Patent Information
- Application Number
- CN202423054130.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2034-12-10
AI Technical Summary
The test point wiring of the existing adapter board is unreasonable, which causes signal interference to the chip during the test, especially under high frequency signal conditions, affecting the accuracy of the test results.
Design an adapter board that simplifies circuit design, avoids signal interference, and improves signal clarity and stability by setting a first pad, a second pad, and a third pad on a substrate and utilizing the coupling of the first line and the second line.
It simplifies the circuit routing design, avoids interference from high-frequency signals, improves the accuracy of chip testing and the stability of signals, and reduces the chip's operating frequency.
Smart Images
Figure CN223597735U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip testing, in particular to a conversion board and a testing device. BACKGROUND
[0002] With the rapid development of integrated circuit technology, the functions and performance of chips are continuously improved, and the working frequency and signal transmission rate are also greatly improved. At the same time, the importance of chip testing is increasingly prominent, and the accuracy and effectiveness of the testing process directly affect the quality and reliability of the product.
[0003] In chip testing, due to the design of the test board, corresponding signal lines and test points cannot be left for measurement. In order to analyze the corresponding signals and improve the efficiency of chip testing, test points can be set through a conversion board, and the chip and the testing device are connected to realize signal transmission and testing.
[0004] However, the wiring of the test points of the existing conversion board is unreasonable, and the chip will cause signal interference during testing, especially in the case of high-frequency signals. This signal interference will cause the working frequency of the chip to decrease, resulting in inaccurate test results, and thus affecting the test results of the chip. CONTENT OF THE INVENTION
[0005] In view of this, the present application provides a conversion board and a testing device, which can improve the problem that the unreasonable layout of the test lines of the conversion board causes signal interference during chip testing and reduces the working frequency.
[0006] The conversion board provided by the present application comprises:
[0007] a substrate having a first surface and a second surface arranged oppositely;
[0008] a first pad arranged on the first surface;
[0009] a second pad arranged on the second surface and configured to be coupled with a first electronic component;
[0010] a third pad arranged on the first surface, the first pad and the third pad being arranged at intervals, and one of them being configured to be coupled with a test probe and the other being configured to be coupled with a second electronic component;
[0011] a first circuit arranged in the substrate, one end of which extends to the first surface and is coupled with the first pad, and the other end of which extends to the second surface and is coupled with the second pad;
[0012] a second circuit arranged in the substrate, one end of which extends to the first surface and is coupled with the third pad, and the other end of which is located in the substrate and is coupled with the first circuit.
[0013] Optionally, the substrate is provided with a first via penetrating therethrough, and the first circuit is located in the first via.
[0014] Optionally, the first circuit is a first conductive pillar, and the first conductive pillar is located in the first via.
[0015] Optionally, the second circuit includes a second conductive pillar and a preset trace provided between layers of the substrate, the preset trace is coupled with the first circuit; the substrate is provided with a second via penetrating from the first surface to the preset trace, the second conductive pillar is located in the second via, and one end of the second conductive pillar is coupled with the third pad and the other end is coupled with the preset trace.
[0016] Optionally, the substrate is provided with a back-drilling hole, and an opening of the back-drilling hole is located on the second surface and exposes the preset trace.
[0017] Optionally, in a direction perpendicular to the first surface and the second surface, a projection of the back-drilling hole falls within a projection of the second conductive pillar.
[0018] Optionally, the second circuit is a trace provided on a surface layer of the substrate, and an insulating layer covers the second circuit, one end of the second circuit is coupled with the third pad, and the other end is coupled with the first trace.
[0019] Optionally, the adapter board further includes a ground wire provided in the substrate, the ground wire is located between the first pad and the third pad, and a distance between the ground wire and the first pad and the third pad is equal.
[0020] Optionally, the adapter board further includes a first ground wire and a second ground wire provided in the substrate, a distance between the first ground wire and the first pad is equal to a distance between the second ground wire and the first pad.
[0021] The application provides a test device, which includes a first electronic element, a second electronic element, and the adapter board as any one of the above, the first electronic element is coupled with the second pad, and the second electronic element is coupled with one of the first pad and the third pad.
[0022] Optionally, the second electronic element is coupled with the third pad, and the first pad is configured to be coupled with a test probe.
[0023] Optionally, the second electronic element is coupled with the first pad, and the third pad is configured to be coupled with a test probe.
[0024] As described above, in the adapter board and test device of the present application, one end of the second line extends to the first surface of the substrate and is coupled with the third pad, and the other end is located in the substrate and is coupled with the first line, which is equivalent to that the second line shares a part of the line with the first line, and the relevant test signals can be led out to the second line through the first line, so that the present application can simplify the second line, avoid the interference of the simplified part of the second line on the relevant signals including high-frequency signals during testing, improve the clarity and stability of the signals, avoid reducing the working frequency of the tested chip, and be beneficial to improving the accuracy of the test results. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 is a structural schematic diagram of an adapter board of a first embodiment of the present application;
[0026] Figure 2 is a first coupling schematic diagram of the adapter board shown in Figure 1 during chip testing;
[0027] Figure 3 is a second coupling schematic diagram of the adapter board shown in Figure 1 during chip testing;
[0028] Figure 4 is a structural schematic diagram of an adapter board of a second embodiment of the present application;
[0029] Figure 5 is a top view of an electrically conductive area of an adapter board of a third embodiment of the present application;
[0030] Figure 6 is a top view of an electrically conductive area of an adapter board of a fourth embodiment of the present application.
[0031] Adapter board 10, substrate 11, first surface 11a, second surface 11b, back-drilling hole 11c, first pad 121, second pad 122, third pad 123, isolation pad 124, first line 131, first conductive pillar 131, second line 132, second conductive pillar 1321, preset wiring 1322, ground wire 14;
[0032] First electronic element 21, second electronic element 22, test probe 23. DETAILED DESCRIPTION
[0033] To solve the above problems existing in the prior art, in the adapter plate and test equipment of the present application, the first surface of the substrate is provided with a first pad and a third pad, the second surface of the substrate is provided with a second pad, one end of the first circuit extends to the first surface of the substrate and is coupled with the first pad, the other end extends to the second surface of the substrate and is coupled with the second pad, one end of the second circuit extends to the first surface of the substrate and is coupled with the third pad, the other end is located in the substrate and is coupled with the first circuit, which is equivalent to the second circuit sharing a part of the first circuit, the first circuit is coupled with the first pad and the second pad, so that the relevant test signals can be led out to the second circuit through the first circuit, thus the design of the circuit layout can be simplified, thereby avoiding the interference of the simplified part on the relevant signals including high-frequency signals during testing, avoiding the reduction of the working frequency of the chip, and improving the accuracy of the test results.
[0034] Among them, the shape, number, size, etc. of any of the adapter plate, first circuit, second circuit and each pad can be adapted according to actual needs, which is not limited by the present application.
[0035] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly below in combination with specific embodiments and corresponding drawings. Obviously, the following described embodiments are only a part of the embodiments of the present application, not all the embodiments. In the case of no conflict, each of the following embodiments and its technical features can be combined with each other, and also belongs to the technical scheme of the present application.
[0036] First embodiment
[0037] Figure 1 is a structural schematic diagram of the adapter plate of the first embodiment of the present application. Please refer to Figure 1 As shown, the adapter plate 10 includes a substrate 11, three pads, and two circuits, namely a first pad 121, a second pad 122 and a third pad 123, and a first circuit 131 and a second circuit 132.
[0038] The substrate 11 has a first surface 11a and a second surface 11b oppositely arranged along the thickness direction thereof, and according to the placement orientation shown in the figure and the placement orientation of the substrate 11 in the actual use scene, the first surface 11a can be called the upper surface 11a, and the second surface 11b can be called the lower surface 11b.
[0039] The first pad 121 and the third pad 123 are both arranged on the first surface 11a of the substrate 11, and on the first surface 11a, the first pad 121 and the third pad 123 are arranged at intervals. By interval arrangement, it means that the minimum distance between two main bodies is not equal to zero, that is, they are not in contact.
[0040] The second pad 122 is disposed on the second surface 11b of the substrate 11.
[0041] The first line 131 is disposed in the substrate 11, one end of the first line 131 extends to the first surface 11a of the substrate 11 and is coupled with the first pad 121, the coupling includes electrical connection, the other end of the first line 131 extends to the second surface 11b of the substrate 11 and is coupled with the second pad 122.
[0042] The second line 132 is disposed in the substrate 11, one end of the second line 132 extends to the first surface 11a of the substrate 11 and is coupled with the third pad 123, the other end of the second line 132 is located in the substrate 11, that is, does not extend to any surface of the substrate 11, and is coupled with the first line 131.
[0043] When the adapter plate 10 is applied to a test scene, in combination with Figure 1 and Figure 2 It is shown that the second pad 122 is configured to be coupled with the first electronic element 21, the first pad 121 is configured to be coupled with the second electronic element 22, and the third pad 123 is configured to be coupled with the test probe 23. The first line 131 can be realized as a conductive line for coupling the first electronic element 21 and the second electronic element 22 to transmit test-related signals between the first electronic element 21 and the second electronic element 22. The second line 132 and a part of the first line 131 (i.e. the part between the first pad 121 and the coupling point with the second line 132) together realize a test line for at least realizing the coupling between the test probe 23 and the second electronic element 22, allowing the test probe 23 to obtain relevant data generated by the second electronic element 22 during the test process, which can be referred to as "test data", via the second line 132.
[0044] Taking a chip test scene as an example, the first electronic element 21 can be a test board connected with an external test device such as a PC (Personal Computer), and the second electronic element 22 can be a chip to be tested, or a test seat for coupling the chip to be tested. When the first pad 121 is coupled with the chip to be tested and the second pad 122 is coupled with the external test device, the external test device can transmit control instructions to the chip to be tested through the first line 131, and the signals generated by the chip according to the control instructions are transmitted to the third pad 123 through a part of the first line 131 and the second line 132, and then collected by the test probe 23 via the third pad 123, and the test probe 23 analyzes the collected signals to complete the chip test.
[0045] In the adapter plate 10 of the present embodiment, the second line 132 shares a part of the line with the first line 131, and the first line 131 is coupled with the first pad 121 and the second pad 122, so that the relevant test signal can be led out to the second line 132 via the first line 131. The present application can simplify the second line 132, thereby simplifying the line routing design of the entire adapter plate 10. For example, in the existing adapter plate, the other end of the second line 132 extends to the first surface 11a of the substrate 11 and is coupled with the chip to be tested. In the signal transmission, the structure layer provided for the second line 132 in the existing adapter plate absorbs and reflects the test-related signal, especially in high-speed signal transmission, which can cause serious signal distortion and interference problems. The present application simplifies the structure layer of the second line 132, which can avoid the interference of the simplified structure layer to the relevant signal including high-frequency signal during testing, improve the clarity and stability of the signal, thereby avoiding the reduction of the working frequency of the chip, and is conducive to improving the accuracy of the test result.
[0046] In actual scenarios, the substrate 11 includes but is not limited to a circuit board such as a PCB (Printed Circuit Board), which has multiple layers of lines (i.e., copper cladding) inside, and the adjacent two layers of lines are insulated by the material of the substrate 11, and the different layers of lines are coupled by a via and a conductive column arranged in the via, i.e., the so-called interlayer coupling. Based on this, the specific forms of the first line 131 and the second line 132 can be adapted according to the line design of the substrate 11.
[0047] For example, the substrate 11 can be provided with a first via (not shown in the figure), which penetrates the substrate 11 along the thickness direction of the substrate 11, i.e., the first via is a through hole penetrating the entire substrate 11, and at this time, one opening of the first via is exposed to the first surface 11a of the substrate 11, and the other opening is exposed to the second surface 11b of the substrate 11; the first line 131 can be a conductive column, referred to as a "first conductive column" 131, and the first conductive column 131 is located in the first via. The use of a conductive column design can reduce the impedance of the first line 131.
[0048] In an example, the second circuit 132 can include a second conductive pillar 1321 and a preset trace 1322 disposed between layers of the substrate 11, the preset trace 1322 being coupled with the first circuit 131; the substrate 11 is provided with a second via (not shown in the figure), the second via penetrating through the first surface 11a of the substrate 11 to the layer where the preset trace 1322 is located, i.e., the second via is a blind via with a certain depth, so as to expose the preset trace 1322; the second conductive pillar 1321 is located in the second via, and one end of the second conductive pillar 1321 is coupled with the third pad 123, and the other end of the second conductive pillar 1321 is coupled with the preset trace 1322. By using the combination of the conductive pillar and the original trace of the substrate 11, the impedance of the second circuit 132 can be reduced.
[0049] In other examples, the second circuit 132 can be a trace disposed on the outermost layer of the substrate 11, and of course the outermost layer of the substrate 11 is also provided with other traces, and the second circuit 132 is only a part of the traces on the outermost layer, and the second circuit 132 is covered with an insulating layer, such as an ink layer, one end of the second circuit 132 is coupled with the third pad 123, and the other end of the second circuit 132 is coupled with the first trace 131. The second circuit 132 can not be provided with the aforementioned second conductive pillar 1321, and in this case, the substrate 11 can not need to be provided with the second via, which is more conducive to simplifying the circuit trace design.
[0050] Please refer to Figure 1 and Figure 3 It is shown that the first pad 121 can also be configured to be coupled with a test probe 23, and the third pad 123 is configured to be coupled with a second electronic element 22.
[0051] When the adapter board 10 of the present embodiment is applied to a test scene, the second pad 122 is coupled with a first electronic element 21, the first pad 121 is coupled with a test probe 23, and the third pad 123 is coupled with a second electronic element 22. Still taking a chip test scene as an example, in combination with Figure 3 It is shown that the first electronic element 21 can be a test board connected with a PC or other external test equipment, and the second electronic element 22 can be a chip to be tested, or a test seat for coupling the chip. When the third pad 123 is coupled with the chip to be tested, and the second pad 122 is coupled with the external test equipment, the external test equipment can transmit control instructions to the chip to be tested through the second pad 122, the first circuit 131 and the third pad 123 in sequence, and the signals generated by the chip according to the control instructions are transmitted to the first pad 121 through a part of the first circuit 131 and the second circuit 132, and then collected by the test probe 23 through the first pad 121, and the test probe 23 analyzes the collected signals, so as to complete the chip test.
[0052] When the test probe 23 contacts the third pad 123, the impedance of the test probe 23 will reflect a signal to the chip to be tested through the long branch second line 132.
[0053] Therefore, the first pad 121 is coupled to the test probe 23, the third pad 123 is coupled to the second electronic element 22, the impedance of the test probe 23 is placed at the end of the short branch first line 131, and the degree of influence of the reflection is reduced compared to being placed at the long branch second line 132.
[0054] In Figure 3 In the adapter board 10 shown, the second line 132 shares a part of the line with the first line 131, and the beneficial effects of the first embodiment described above can also be achieved, which will not be described here.
[0055] Second embodiment
[0056] For structural elements with the same name, the same reference numbers are used in various embodiments. Figure 4 is a structural schematic diagram of the adapter board of the second embodiment of the present application, please refer to Figure 4 The substrate 11 is provided with a back-drilled hole 11c, which refers to a hole drilled from the second surface 11b to the first surface 11a on the substrate 11 by a back-drilling process, but does not penetrate the substrate 11, but is open at the second surface 11b of the substrate 11 and exposes the preset trace 1322 of the second line 132.
[0057] The specific principles and processes of the back-drilling process can be referred to the prior art, which will not be described here. In short, it is to drill a hole from the back of the already completed multilayer circuit board (i.e. the substrate 11) to accurately remove the unnecessary circuit structure layer in the back-drilled hole 11c (PTH, Plated-Through Holes). The part of the circuit structure layer removed is called "stub". By removing the stub, the present application can significantly reduce the reflection and interference of the signal in the transmission process, further improve the clarity and stability of the signal, and can optimize the circuit design, allow more flexible arrangement of the traces and element positions of the substrate 11, thereby realizing more compact and efficient circuit design, in addition, it can also reduce the use of buried blind holes, reduce the manufacturing precision of the entire substrate 11, thereby reducing the manufacturing difficulty and cost.
[0058] Optionally, along a direction perpendicular to the first surface 11a and the second surface 11b, i.e., along a direction perpendicular to the thickness of the substrate 11, the orthographic projection of the back-drilled hole 11c falls within the orthographic projection of the second conductive post 1321. Here, while achieving a larger diameter for the back-drilled hole 11c, damage to other traces on the substrate 11 is avoided. Through this larger diameter back-drilled hole 11c, this example can remove more stubs, significantly reducing signal reflection and interference.
[0059] Third Embodiment
[0060] Based on the description of the first embodiment above, but with the difference that, in combination with Figure 5 As shown, the adapter plate 10 also includes a grounding wire 14 disposed within the substrate 11. This grounding wire 14 can be embodied as a conductive post; for example, the substrate 11... Figure 1 A via is provided between the first pad 121 and the third pad 123, bypassing the preset trace 1322. The via is configured as a grounding conductor 14 of a conductive post, coupled to the trace of the first line 131 in the relevant layers of the substrate 11, thus forming a complete return path, referred to as the "first return path". Additionally, the grounding conductor 14 in the via is coupled to the trace of the second line 132 in the relevant layers of the substrate 11, thus forming a complete return path, referred to as the "second return path". The first and second return paths can guide reflected and interfering signals out of the substrate 11 and ultimately to ground via the grounding conductor 14, thereby significantly reducing signal reflection and interference.
[0061] Figure 5 This is a top view of an electrically conductive area of a substrate 11, which has multiple electrically conductive areas. Figure 5 As shown, an isolation pad 124 can be provided around the first pad 121. This isolation pad 124 surrounds the first pad 121 to insulate the first pad 121 from the traces between certain layers of the substrate 11, ultimately enabling the conduction of specific circuit portions between different layers of the substrate 11. One end of the first line 131 (e.g., the endpoint of the first conductive post 131 adjacent to the first surface 11a) and a via accommodating one end of the first line 131 are provided within the orthogonal projection of the first pad 121. Similarly, the isolation pad 124 can also be provided around the third pad 123 to achieve the same effect.
[0062] It should be noted that the grounding wire 14 can be disposed within the layer of the circuit board as a buried via. One end of the grounding wire 14 adjacent to the first surface 11a of the substrate 11 may not be exposed to the first surface 11a, or it may be exposed to the first surface 11a as a blind via. This application does not limit this.Figure 5 As an example, one end of the ground wire 14 is exposed to the first surface 11a, the ground wire 14 is located between the first pad 121 and the third pad 123, the distance between the ground wire 14 and the first pad 121 is D1, the distance between the ground wire 14 and the third pad 123 is D2, and D1 and D2 can be equal. In this example, the impedance of the first line 131 and the second line 132 can be matched, which can improve the signal quality during testing of the adapter board 10.
[0063] The ground wire 14 can also be applied to the second embodiment described above and produce the same technical effects.
[0064] Fourth embodiment
[0065] Unlike Figure 5 The first line 131 and the second line 132 of the example share the ground wire 14, and the first line 131 and the second line 132 of the fourth embodiment each have a ground wire. In combination with Figure 6 As shown, the adapter board 10 further includes a first ground wire 141 and a second ground wire 142 disposed in the substrate 11, either of the first ground wire 141 and the second ground wire 142 can be a conductive column, for example, the substrate 11 is provided with a first via and a second via, the two vias bypass the preset trace 1322, the first line 131 and the second line 132, the first ground wire 141 and the second ground wire 142, which are conductive columns, are disposed in the corresponding vias, the first ground wire 141 is coupled to the trace between the first line 131 and the corresponding layer of the substrate 11, thereby forming a complete first reflow path with the first line 131, in addition, the second ground wire 142 disposed in the via is coupled to the trace between the second line 132 and the corresponding layer of the substrate 11, thereby forming a complete second reflow path with the second line 132. The first reflow path and the second reflow path can guide the reflected and interference signals out of the substrate 11 through the corresponding ground wire and ultimately to the ground, thereby greatly reducing the reflection and interference of the signals.
[0066] Either of the first ground wire 141 and the second ground wire 142, one end adjacent to the first surface 11a of the substrate 11 can not be exposed to the first surface 11a, or can be exposed to the first surface 11a, which is not limited by the present application. Figure 6For example, the first ground wire 141 and the second ground wire 142 are exposed at one end on the first surface 11a, the distance between the first ground wire 141 and the first pad 121 is D1, the distance between the second ground wire 142 and the third pad 123 is D2, and D1 and D2 can be equal. In this way, the first line 131 and the second line 132 can have matched impedance, which can improve the signal quality during testing of the adapter plate 10.
[0067] The embodiments of the present application also provide a testing device, which includes a first electronic component, a second electronic component, and an adapter plate. The adapter plate can have the structural design of the adapter plate 10 of any of the preceding embodiments, and thus can have the beneficial effects of any of the preceding embodiments. For example, the first electronic component is coupled to the second pad of the adapter plate, and the second electronic component is coupled to one of the first pad and the third pad of the adapter plate. Specifically, the second electronic component is coupled to the third pad, and the first pad is configured to be coupled to a test probe. Alternatively, the second electronic component is coupled to the first pad, and the third pad is configured to be coupled to a test probe. In this way, the first pad and the test probe, and the third pad and the test probe are not fixedly coupled, and an operator can perform "blind connection".
[0068] The above description is only some embodiments of the present application, and does not limit the patent scope of the present application. For those skilled in the art, any equivalent structural transformation based on the content of the specification and the drawings is also included in the patent protection scope of the present application.
[0069] In the description of the embodiments of the present application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the technical solutions of the corresponding embodiments, and do not indicate or imply that the device or element must have a particular orientation, be constructed and operated in a particular orientation, and cannot be understood as a limitation of the present application.
[0070] Although the terms "first", "second", and the like are used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. In addition, the singular forms "one", "a", and "the" are intended to include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.
Claims
1. An adapter plate, characterized by The adapter board comprises: a substrate having a first surface and a second surface arranged oppositely; a first pad arranged on the first surface; a second pad arranged on the second surface and configured to be coupled with a first electronic component; a third pad arranged on the first surface, the first pad and the third pad being arranged at a distance and one of them being configured to be coupled with a test probe and the other being configured to be coupled with a second electronic component; a first line arranged in the substrate and having one end extending to the first surface and coupled with the first pad and the other end extending to the second surface and coupled with the second pad; a second line arranged in the substrate and having one end extending to the first surface and coupled with the third pad and the other end arranged in the substrate and coupled with the first line.
2. The adapter plate of claim 1, wherein, The substrate is provided with a first via hole through which the first line passes.
3. The adapter plate of claim 1, wherein, The second line comprises a second conductive pillar and a preset trace arranged between layers of the substrate, the preset trace being coupled with the first line; the substrate is provided with a second via hole through which the preset trace passes from the first surface to the second surface, the second conductive pillar being arranged in the second via hole and having one end coupled with the third pad and the other end coupled with the preset trace.
4. The adapter plate of claim 3, wherein, The substrate is provided with a back-drilling hole, an opening of the back-drilling hole being arranged on the second surface and exposing the preset trace.
5. The adapter plate of claim 4, wherein, In a direction perpendicular to the first surface and the second surface, a projection of the back-drilling hole falls within a projection of the second conductive pillar.
6. The adapter plate of claim 1, wherein, The second line is a trace arranged on a surface layer of the substrate, and the second line is covered with an insulating layer, one end of the second line being coupled with the third pad and the other end being coupled with the first line.
7. The adapter plate of any one of claims 1 to 6, wherein, The adapter board further comprises a ground wire arranged in the substrate, the ground wire being arranged between the first pad and the third pad, and the distance between the ground wire and the first pad and the third pad being equal.
8. The adapter plate of any one of claims 1 to 6, wherein, The adapter board further comprises a first ground wire and a second ground wire arranged in the substrate, the distance between the first ground wire and the first pad being equal to the distance between the second ground wire and the first pad.
9. A test apparatus, characterized by The adapter board comprises a first electronic component, a second electronic component, and any one of claims 1 to 8, the first electronic component being coupled with the second pad, and the second electronic component being coupled with one of the first pad and the third pad.
10. The test apparatus of claim 9, wherein, The second electronic component is coupled with the third pad, and the first pad is configured to be coupled with a test probe; or the second electronic component is coupled with the first pad, and the third pad is configured to be coupled with a test probe.