Circuit for testing power supply reliability of chip

Abstract

The utility model discloses a circuit for testing power supply reliability of a chip. The circuit comprises an MH1905 serving as a main control chip, a power input port, a power conversion chip, a sampling resistor, a power port, a configuration port and a communication port, the GP IO pin is connected with an enabling pin of the power conversion chip; the ADC positive electrode pin is connected with the output end of the power supply conversion chip; the negative electrode pin of the ADC is connected with the output end of the sampling resistor; the configuration pin is connected with the configuration port; the communication pin is connected with the communication port; the power supply input port is connected with the main control chip and the power supply conversion chip respectively; the power supply conversion chip is connected with the sampling resistor; the sampling resistor is connected with the power supply port; the power supply port is connected with the tested chip; and the communication port is connected with the tested chip. According to the utility model, through a highly integrated mode, reliability tests of various power-on and power-off time sequence combinations of the chip can be completed at the same time, the running state of the tested chip can be read in real time, and the measured data can be stored in real time.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of circuit for testing chip power supply reliability, belong to chip test technical field. BACKGROUND

[0002] Power supply reliability test is crucial to the manufacturing and design process of chip, through comprehensive and strict power supply reliability test, potential design defects, manufacturing problems or environmental sensitivity can be found and solved in advance, so as to ensure the performance and reliability of chip in long-term use. At the same time, power supply reliability test has important significance for providing chip instantaneous power consumption, working power supply conditions and other electrical parameter indexes.

[0003] In the Chinese patent with publication number CN203519804U, a device for testing chip power supply reliability is disclosed. The device includes a first contact for connecting the chip power supply pin, a second contact for connecting the power supply, a attenuator for reducing voltage, the attenuator is installed on the substrate, and its pins are respectively electrically connected with the first contact and the second contact. The device can test the power supply reliability of each chip power supply separately, and find out the weak point of chip power supply.

[0004] But its test function is single, cannot realize the extraction of chip instantaneous power consumption and other electrical indexes, real-time monitoring of measured chip running state and other functions while reliability testing. SUMMARY

[0005] The technical problem to be solved by the utility model lies in providing a kind of circuit for testing chip power supply reliability.

[0006] To achieve the above technical purpose, the utility model adopts the following technical scheme:

[0007] A kind of circuit for testing chip power supply reliability, including as main control chip MH1905, still include: power input port, n power conversion chip, n sampling resistance, n power port, configuration port and communication port, n is positive integer;

[0008] The main control chip includes: n GPIO pins, n ADC positive electrode pins, n ADC negative electrode pins, configuration input pin, configuration output pin, communication input pin and communication output pin;Wherein,

[0009] The nth GPIO pin is connected with the enable pin of the nth power conversion chip; the nth ADC positive pin is connected with the output end of the nth power conversion chip; the nth ADC negative pin is connected with the output end of the nth sampling resistor; the configuration input pin is connected with the output end of the configuration port; the configuration output pin is connected with the input end of the configuration port; the communication input pin is connected with the output end of the communication port; the communication output pin is connected with the input end of the communication port; the power input port is connected with the input end of the master control chip and the nth power conversion chip respectively; the output end of the nth power conversion chip is connected with the input end of the nth sampling resistor; the output end of the nth sampling resistor is connected with the input end of the nth power port; the output end of the nth power port is connected with the measured chip; the communication port is connected with the measured chip;

[0010] The nth ADC positive pin and the nth ADC negative pin collect voltage at both ends of the nth sampling resistor;

[0011] The configuration port sends configuration information to the master control chip through the configuration input pin and the configuration output pin;

[0012] The master control chip and the measured chip are connected through the communication port and information interaction is carried out to monitor the running state of the measured chip.

[0013] Preferably, the circuit further comprises a USB port; the master control chip further comprises a VBUS pin, a DP pin, a DM pin and an ID pin.

[0014] The VBUS pin, the DP pin, the DM pin and the ID pin are connected with the USB port respectively, and are used for external storage device to save test data.

[0015] Preferably, the circuit further comprises a display port; the master control chip further comprises a display input pin and a display output pin.

[0016] The display input pin is connected with the output end of the display port; the display output pin is connected with the input end of the display port, and is used for external display device to display test data and the running state of the measured chip in real time.

[0017] Preferably, the preset power-on and power-off time sequence combination and test times are sent to the master control chip through the configuration port to test the measured chip.

[0018] Preferably, the master control chip receives the collected voltage value, calculates the corresponding current value and the instantaneous power consumption of the measured chip.

[0019] Preferably, the resistance of the sampling resistor is greater than or equal to 20 milliohms and less than or equal to 200 milliohms.

[0020] Preferably, the power conversion chip is any one of TLV62569, SY8120 and APW7080.

[0021] Preferably, when the GPIO pin is high, the power conversion chip is enabled; when the GPIO pin is low, the power conversion chip is turned off; the time interval between the GPIO pin being high and low satisfies the test requirement of traversing different power-on sequences of the chip under test, so as to complete the reliability test of various power-on and power-off sequence combinations of the chip under test.

[0022] Compared with existing technologies, this utility model, through a highly integrated approach, can simultaneously perform reliability testing of various power-on / off timing combinations of chips, measure the instantaneous power consumption of each power supply of the chip under test, read the operating status of the chip under test in real time, and store the measurement data in real time. Attached Figure Description

[0023] Figure 1 A schematic diagram of a circuit for testing the power supply reliability of a chip, provided by this utility model;

[0024] Figure 2 for Figure 1 The flowchart of the circuit's operation is shown. Detailed Implementation

[0025] The technical content of this utility model will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] like Figure 1 As shown in the figure, an embodiment of this utility model provides a circuit for testing the reliability of chip power supply, including: a power input port, a main control chip, n power conversion chips, n sampling resistors, n power ports, a USB port, a configuration port, a display port, and a communication port.

[0027] In one embodiment of this utility model, the main control chip is model MH 1905. MH 1905 is an asymmetric multi-core processor consisting of two processing subsystems: an application subsystem built around the ARM Cortex-A5 core, featuring an ARM NEON SIMD engine and a floating-point unit (FPU), optimized for applications based on rich operating systems; and a real-time subsystem built around a 32-bit processor, with enhanced security features and optimized for low-power applications.

[0028] The chip includes: n GPIO pins, n ADC positive pins, n ADC negative pins, VBUS pin, DP pin, DM pin, ID pin, configuration output pin, configuration input pin, display input pin, display output pin, communication input pin, and communication output pin.

[0029] The nth GPIO pin is connected to the enable pin (EN) of the nth power converter chip. The positive pin (ADC+) of the nth ADC is connected to the output (VOUT) of the nth power converter chip; the negative pin (ADC-) of the nth ADC is connected to the output of the nth sampling resistor. The VBUS, DP, DM, and ID pins are connected to the USB port. The configuration input pin (CIN) is connected to the output of the configuration port; the configuration output pin (COUT) is connected to the input of the configuration port. The display input pin (DIN) is connected to the output of the display port; the display output pin (DOUT) is connected to the input of the display port. The communication input pin (RXD) is connected to the output of the communication port; the communication output pin (TXD) is connected to the input of the communication port. The power input ports are connected to the inputs of the main control chip and the nth power converter chip. The output of the nth power converter chip is connected to the input of the nth sampling resistor. The output of the nth sampling resistor is connected to the input of the nth power port. The output of the nth power port is connected to the chip under test (DUT). The communication port is connected to the DUT.

[0030] In one embodiment of this invention, the GPIO pins can be set high and low (when set high, the power conversion chip is enabled and outputs normally; conversely, when set low, the power conversion chip is turned off and has no output). Simultaneously, the time interval between setting high and low can be set through these GPIO pins, thereby meeting the testing requirements of traversing different power-on sequences of the chip under test, and enabling simultaneous reliability testing of multiple power-on / off sequence combinations of the chip under test.

[0031] In one embodiment of this invention, the positive and negative pins of the ADC are connected to the two ends of the sampling resistor respectively to collect the voltage difference between the two ends. The main control chip then calculates the current value of this channel and the instantaneous power consumption of the chip under test. The reason for distinguishing between the positive and negative terminals of the ADC in this invention is that a typical ADC has only one signal line, so it can only collect one voltage value, namely the voltage difference between the measured point voltage and GND (0V). An ADC with two signal lines, positive and negative, can collect the voltage difference between the positive and negative terminals.

[0032] In an embodiment of the utility model, the VBUS pin, the DP pin, the DM pin and the ID pin in main control chip connect USB port, its role is external U disk and so on storage device, realizes real time storage of test data. The role of configuration port is that configuration information is sent to main control chip through the port, for example, different power on and off time sequence combination is configured. Display port can be connected with display device, for real time display of test data. The role of communication port is that information interaction is carried out with the chip under test through the port, thereby real time monitoring the running state of the chip under test. For example, the power on flag bit of the chip under test is read.

[0033] In an embodiment of the utility model, the output end VOUT of power conversion chip is connected with the input end of sampling resistance, and the role is that different voltage combinations can be outputted through the power conversion chip to meet the needs of different chips under test. The model of power conversion chip includes but is not limited to any one of TLV62569, SY8120, APW7080 and the like.

[0034] In an embodiment of the utility model, the output end of sampling resistance is connected with the input end of power port. The resistance value of sampling resistance is greater than or equal to 20 milliohm and less than or equal to 200 milliohm. The output end of power port is connected with the input end of the chip under test.

[0035] It should be noted that in the utility model, the number of GPIO pin, power conversion chip, sampling resistance and power port is determined according to the actual scene demand, and the utility model does not limit this.

[0036] As shown in Figure 2 The working process of the test chip power supply reliability circuit provided by the utility model is as follows:

[0037] S1: power on the test chip power supply reliability circuit through the power input port.

[0038] S2: set the power on and off time sequence combination and test times.

[0039] The power on and off time sequence combination refers to, for example, the reliability of the measured chip time sequence combination 1~measured chip time sequence combination n in multiple cases is to be traversed, then the circuit will test in turn according to the set order.

[0040] The test times refer to the number of times of power on and off test of the chip under test in each time sequence combination.

[0041] The utility model sets different power on and off time sequence combinations and times, checks whether the chip under test can start normally in these different combinations, and verifies the reliability of the chip under test according to this, that is, the power on and off time sequence combination in which the chip can start reliably. This is also an important electrical indicator of the chip under test.

[0042] S3: the circuit powers on the measured chip once, collects the instantaneous current of each power port, then calculates the instantaneous power consumption, and stores and displays each test data in real time.

[0043] S4: after the current power-on is completed, the circuit reads the power-on flag bit of the measured chip through the communication port. If the reading is successful, the measured chip starts normally, and enters step S5. If the reading fails, the measured chip starts abnormally, the test ends, and the test result is reported as test failure.

[0044] S5: determine whether the test times of the current timing combination reach the set times. If yes, enter step S6. If no, repeat steps S3-S4.

[0045] S6: determine whether the test times of all timing combinations reach the set times. If yes, the test ends, and the test result is reported as test pass. If no, repeat steps S2-S4.

[0046] In an embodiment of the present application, step S3 connects the positive and negative poles of the ADC to the two ends of the sampling resistor respectively to collect the voltage difference between the two ends, and then calculates the current value and the instantaneous power consumption of the measured chip through the master control chip.

[0047] It should be noted that the above multiple embodiments are only illustrative. The technical solutions of each embodiment can be combined, and all are within the protection scope of the present application.

[0048] The circuit for testing the power supply reliability of the chip provided by the present application is described in detail above. For those skilled in the art, any obvious modification made without departing from the essential content of the present application shall constitute an infringement of the patent right of the present application, and shall bear the corresponding legal responsibility.

Claims

1. A circuit for testing the power supply reliability of a chip, comprising an MH 1905 as master chip, characterized in that The circuit further comprises a power input port, n power conversion chips, n sampling resistors, n power ports, a configuration port and a communication port, n being a positive integer; The main control chip comprises n GPIO pins, n ADC positive pins, n ADC negative pins, a configuration input pin, a configuration output pin, a communication input pin and a communication output pin; wherein, The n-th GPIO pin is connected with an enable pin of the n-th power conversion chip; the n-th ADC positive pin is connected with an output terminal of the n-th power conversion chip; the n-th ADC negative pin is connected with an output terminal of the n-th sampling resistor; the configuration input pin is connected with an output terminal of the configuration port; the configuration output pin is connected with an input terminal of the configuration port; the communication input pin is connected with an output terminal of the communication port; the communication output pin is connected with an input terminal of the communication port; the power input port is connected with input terminals of the main control chip and the n-th power conversion chip respectively; an output terminal of the n-th power conversion chip is connected with an input terminal of the n-th sampling resistor; an output terminal of the n-th sampling resistor is connected with an input terminal of the n-th power port; an output terminal of the n-th power port is connected with the chip under test; and the communication port is connected with the chip under test; The n-th ADC positive pin and the n-th ADC negative pin collect voltage across the n-th sampling resistor; The configuration port sends configuration information to the main control chip through the configuration input pin and the configuration output pin; The main control chip is connected with the chip under test through the communication port and exchanges information to monitor the running state of the chip under test.

2. The circuit of claim 1, wherein The circuit further comprises a USB port; and the main control chip further comprises a VBUS pin, a DP pin, a DM pin and an ID pin. The VBUS pin, the DP pin, the DM pin and the ID pin are connected with the USB port respectively, and are used for externally connecting a storage device to save test data.

3. The circuit of claim 1, wherein The circuit further comprises a display port; and the main control chip further comprises a display input pin and a display output pin. The display input pin is connected with an output terminal of the display port; and the display output pin is connected with an input terminal of the display port, and is used for externally connecting a display device to display test data and the running state of the chip under test in real time.

4. The circuit of claim 1, wherein The configuration port is used for sending a preset power-on / off timing combination and test times to the main control chip to test the chip under test.

5. The circuit of claim 1, wherein The main control chip receives the collected voltage value, calculates the voltage value to obtain corresponding current value and instantaneous power consumption of the chip under test.

6. The circuit of claim 1, wherein The resistance value of the sampling resistor is greater than or equal to 20 mΩ and less than or equal to 200 mΩ.

7. The circuit of claim 1, wherein The power conversion chip is any one of TLV62569, SY8120 and APW7080.

8. The circuit of claim 1, wherein The GPIO pin is high, the power conversion chip is enabled; the GPIO pin is low, the power conversion chip is closed; the time interval of the GPIO pin being high and low meets the test requirements of traversing different power-on sequences of the tested chip, to complete the reliability test of various power-on and power-off sequence combinations of the tested chip.

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