System reset controller
The system reset controller, designed with a four-level synchronization method and a state machine, solves the problems of external reset pin jitter and asynchronous reset, achieving stable response and fast recovery of the SoC chip, and ensuring the reliability and consistency of the system.
Patent Information
- Application Number
- CN202423217953.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2034-12-25
AI Technical Summary
External reset pins are susceptible to mechanical switch jitter or external interference, resulting in unstable reset signals. Furthermore, the asynchronous nature of the reset signal may not match the internal clock domain of the chip, potentially causing multiple unnecessary reset operations and reset instability.
The glitch detection circuit and state machine design employ a four-level synchronization method, gradually switching from power-on reset to system reset to ensure that the reset signal is synchronized with the clock. Individual control and asynchronous reset synchronization of each processor are achieved through the reset source selection module and the generation module.
It effectively avoids false resets caused by external pin jitter or power instability, ensuring system stability and rapid recovery, and improving the response speed and processing power of the SoC chip.
Smart Images
Figure CN223598201U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the technical field of semiconductor device, especially relate to a system reset controller. BACKGROUND
[0002] With the development of integrated circuit technology, SoC (System on Chip) chip integrates more and more functional modules, and its complexity and integration degree are increasingly improved; system reset controller becomes the key component to ensure the stable operation of SoC chip. The main function of system reset controller is to manage SoC reset network, support individual reset control for each processor, and also support reset synchronization between different clock domains. This function is crucial to ensure that the system can reliably recover to the initial state when power-on, exception handling and software failure.
[0003] The prior art has the following technical problems:
[0004] 1. The external reset pin may be affected by mechanical switch jitter or external interference, resulting in unstable reset signal and causing unnecessary multiple reset operations;
[0005] 2. The reset signal is asynchronous and does not match the clock domain inside the chip. If not synchronized, it may cause unstable reset operation or errors. INVENTION CONTENTS
[0006] To solve the problems in the related art, the present application provides a system reset controller, which significantly improves the response speed and processing capacity of SoC chip when facing various reset requirements, and ensures the stable operation and rapid recovery of the system.
[0007] The technical scheme is as follows:
[0008] A system reset controller, comprising a reset source selection module and a reset generation module,
[0009] The reset generation module is used to control the entire process from reset generation to clock cooperation and reset cancellation, which includes a glitch detection circuit and a reset process control module;
[0010] The reset source selection module is in communication connection with the reset generation module. The reset generation module individually controls the reset of each processor and supports reset synchronization between different clocks.
[0011] Further technical scheme, the glitch detection circuit adopts four-stage synchronization mode.
[0012] Further technical scheme, the reset source selection module includes external pin reset, power-on reset and system reset.
[0013] Further technical solutions, external pin reset, power-on reset and system reset are asynchronous reset.
[0014] Further technical solutions, in the system reset controller development process, state machine mode is used, from loading power-on reset, to start external crystal oscillator and system clock, then reset synchronization, gradually switch from power-on reset to system reset.
[0015] Further technical solutions, system reset resets peripherals first, and then resets the processor.
[0016] Further technical solutions, the peripheral and processor reset signals must be synchronized by respective clocks.
[0017] Further technical solutions, the control signals of the system reset controller are connected by input and output ports.
[0018] The technical solutions at least have the following technical effects:
[0019] In the system reset controller development process, four-level synchronization is used to filter glitches of external pin reset, state machine mode is used, from power-on reset, to start external crystal oscillator and clock, to generate system reset, peripherals are reset first, and then the processor is reset, step by step from power-on reset to system reset, reset control is performed in time and step by step, until the whole system is reset, the false reset caused by external pin jitter or unstable power supply is avoided, and the stability of the system is ensured. BRIEF DESCRIPTION OF DRAWINGS
[0020] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the present application.
[0021] Figure 1 The component structure diagram of the system reset controller provided for a preferred embodiment of the present application is shown in the figure.
[0022] Figure 2 The structure diagram of the SoC chip system reset controller provided for a preferred embodiment of the present application is shown in the figure.
[0023] Figure 3 The reset start flowchart provided for a preferred embodiment of the present application is shown in the figure.
[0024] Figure 4 The reset timing diagram provided for a preferred embodiment of the present application is shown in the figure. DETAILED DESCRIPTION
[0025] The exemplary embodiments will be described in detail herein with reference to exemplary examples, which are illustrated in the drawings. Where the description of the following exemplary embodiments refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present disclosure. Instead, they are merely examples consistent with some aspects of the present disclosure as detailed in the appended claims.
[0026] The reset controller of the embodiment supports management of the SoC reset network, supports individual reset control of each processor, and supports synchronization of resets between different clock domains; it is mainly responsible for restoring each circuit module in the chip to an initial state. When a reset signal is triggered, the components such as registers and state machines in the chip are reset, ensuring that the chip starts working from a known and stable state. The reset controller of the embodiment combines three main reset sources and then issues them to each module of the chip system in the form of a network to ensure the consistency of the chip operation.
[0027] As shown in FIG. 1, a system reset controller includes a reset source selection module and a reset generation module, the reset generation module is used to control the entire process of reset generation, cooperation with the clock, and reset cancellation, which includes a glitch detection circuit and a reset process control module; the reset source selection module is in communication connection with the reset generation module, the reset generation module individually controls the reset of each processor and supports the synchronization of resets between different clocks. Figure 1 As shown in FIG. 2, a structure diagram of a SoC chip system reset controller, taking a SoC chip as an example, the reset sources of the SoC chip mainly include the following three types:
[0028] Figure 2 As shown in FIG. 3, an external pin reset: the reset pin is connected to the reset button on the circuit board, once the reset button is pressed, a level change will be given to the external reset pin of the chip, thereby triggering the chip reset. This method is simple and direct, and is convenient for debugging and manually restarting the chip.
[0029] Power-on POR reset: when the system power supply is converted from a no-power state to a normal power supply state, the POR reset circuit detects the rising process of the power supply voltage and generates a reset signal at the appropriate time to initialize each component in the system to a known initial state, ensuring that the system can start stably and reliably.
[0030] System reset: when abnormal conditions (such as software errors, hardware failures, etc.) occur during system operation or software setting, the system can be reset to return to a normal operating state.
[0031] System reset: when abnormal conditions (such as software errors, hardware failures, etc.) occur during system operation or software setting, the system can be reset to return to a normal operating state.
[0032] As shown in FIG. 4, a reset controller of a SoC chip system includes a reset source selection module and a reset generation module, the reset generation module is used to control the entire process of reset generation, cooperation with the clock, and reset cancellation, which includes a glitch detection circuit and a reset process control module; the reset source selection module is in communication connection with the reset generation module, the reset generation module individually controls the reset of each processor and supports the synchronization of resets between different clocks. Figures 1-4 The reset generation module is the most important module, which controls the whole process from reset generation to reset synchronization with clock and reset release. During the design of the reset generation module, the following two points should be noted:
[0033] First, the reset from external pin should be detected to avoid any disturbance on the pin affecting the stability of the whole system. The four-stage synchronization method is used in the glitch detection circuit. If the continuous low level on the pin exceeds 4 clock cycles, it means a real reset signal.
[0034] Second, the process control of reset. As shown in Figure 3 After power-on, the power-on reset signal is generated, and after 256 clock cycles, the power-on reset signal is released, and after 256 clock cycles, the bus and peripheral reset signal is generated, and after 256 clock cycles, the system reset is generated to reset the whole system.
[0035] The power-on of SoC system is a very critical step, as shown in Figure 4 At power-on, the "step-by-step release of power-on reset technology" is needed to load the clock and reset signal step by step, first release the power-on reset, then release the bus and peripheral reset, processor reset and DSP reset, to ensure the initialization and consistency of the system.
[0036] During the development of the system reset controller, the state machine method will be used, from loading the power-on reset, to starting the external crystal oscillator and system clock, then performing reset synchronization, and switching from power-on reset to system reset step by step, to ensure that the clock is stable when the system is reset. This design method is stable and reliable.
[0037] The reset controller itself has no key register, and the control signals are connected by input and output interfaces. The reset control of different modules is controlled by the upper system level register, and is not set in this module.
[0038] The port signals of the reset module are shown in the following table.
[0039] Table 1 Port signals of the reset module
[0040]
[0041]
[0042] Working principle:
[0043] SoC chips must have a reset function. When powered on, reset can set the registers of each module in the chip to the initial state. When the SoC chip is powered on, the state in the chip is uncertain, and the reset operation is like a "zero key" that lets the system start working from a known starting point, ensuring stable startup of the system. Moreover, during system operation, when software failures such as program runaway, hardware abnormalities such as power fluctuations, etc. occur, reset can restore the chip to a normal state, reinitialize the key parts of the chip, and let the system continue to perform tasks normally, avoiding continuous abnormality and even damage of the system due to errors.
[0044] The reset source of the chip is various, and usually contains external pin reset, power monitoring reset, and fault, timing and software reset. SoC chips usually have one or more external reset pins, and the chip reset operation can be triggered by external circuits. A reset button can be connected to this pin on the development board. The advantage of the external reset pin is that it is convenient for debugging and manual reset, and when the system fails or needs to be reinitialized, the entire chip can be reset directly through external operation. The power monitoring circuit is another important reset source, which can trigger a reset signal when the power supply has abnormal conditions (such as voltage being too low or too high). For example, when the power supply voltage drops below the lower limit of the normal operating voltage range of the chip, the voltage comparator in the power monitoring circuit will detect this change and generate a reset signal. This reset method can protect the chip from damage caused by power fluctuations and ensure that the chip can start working from a known initial state after the power supply returns to normal. Software reset is triggered by a program running inside the chip. It is usually implemented by writing a reset instruction to a specific register, calling a system-provided reset function, or through watchdog timing. For example, in the operating system, if a serious error in the software system is detected (such as program runaway or memory overflow), a software reset instruction can be executed to restart the system. The advantage of software reset is that it can flexibly reset the operation according to the running state of the software, and can save some important system state information before resetting.
[0045] To ensure the stability of the reset source, reset debouncing and reset synchronization are usually required. Reset synchronization refers to the process of synchronizing the reset signal with the internal clock signal after it enters the chip. This is because the reset signal may be asynchronous and does not match the clock domain inside the chip. If not synchronized, it may cause unstable reset operation or errors. Reset synchronization circuits generally use flip-flops to synchronize the reset signal with the clock signal, ensuring that the reset operation is stable under the control of the clock. Reset debouncing refers to the process of debouncing the reset signal input by the external reset pin, which may be dithered due to mechanical switch dithering or external interference. To avoid unnecessary multiple resets caused by dithering, the reset signal needs to be debounced. Common debouncing methods include using hardware debouncing circuits (such as capacitor and resistor filter circuits) and software debouncing methods (such as filtering dithering signals through delays and judgments). Hardware debouncing circuits use the charge-discharge characteristics of capacitors to smooth the reset signal, and software debouncing methods use delay time and judgment logic in the program to identify and filter out dithering signals.
[0046] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice in the art to which the application pertains. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the application being indicated by the following claims.
[0047] It is understood that the application is not limited to the precise construction and methods described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is limited only by the claims that follow.
Claims
1. A system reset controller, characterized in that: This includes a reset source selection module and a reset generation module. The reset generation module is used to control the entire process of reset from generation to clock synchronization and reset cancellation. It includes a glitch detection circuit and a reset process control module. The reset source selection module communicates with the reset generation module. The reset generation module performs individual reset control on each processor and supports reset synchronization between different clocks.
2. The system reset controller according to claim 1, characterized in that, The burr detection circuit adopts a four-level synchronization method.
3. The system reset controller according to claim 1, characterized in that, The reset source selection module includes external pin reset, power-on reset, and system reset.
4. The system reset controller according to claim 3, characterized in that, The external pin reset, power-on reset, and system reset are asynchronous resets.
5. The system reset controller according to claim 3, characterized in that, During the development of the system reset controller, a state machine approach is adopted, gradually switching from power-on reset to system reset by loading the power-on reset, starting the external crystal oscillator and system clock, and then performing reset synchronization.
6. The system reset controller according to claim 5, characterized in that, The system reset first resets the peripherals, then resets the processor.
7. The system reset controller according to claim 6, characterized in that, The peripheral and processor reset signals must be synchronized using their respective clocks.
8. The system reset controller according to claim 1, characterized in that, The control signals of the system reset controller are all connected to the input / output ports.