Semiconductor defect detection structure

Abstract

The utility model relates to a semiconductor defect detection structure, which is used for carrying out defect detection on a metal wire of a semiconductor device, and comprises a metal wire to be detected and a plurality of interconnected metal wires, and each interconnected metal wire is provided with a plurality of mutually spaced metal connecting pieces; wherein at least one side of the to-be-tested metal wire is provided with a plurality of interconnection metal wires in parallel, the distance between the to-be-tested metal wire and each interconnection metal wire is the same, and the metal wire, the to-be-tested metal wire and the interconnection metal wires are all arranged in a metal interconnection layer of the semiconductor device. According to the invention, the actual setting mode of the metal wire and possible defect conditions are simulated, whether the metal wire in the semiconductor device has defects can be judged according to the resistance change of the to-be-detected metal wire, the defect detection efficiency of the metal wire is improved, and the risk of corrosion caused by exposure of the metal wire in the detection process is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor device testing technology, and in particular to a semiconductor defect detection structure. Background Technology

[0002] Dual damascene is a metal wire fabrication process that first deposits a dielectric material and then dry-etches a dual damascene structure of vias and trenches. Currently, commonly used dual damascene processes are mainly divided into three types: via-first, trench-first, and via and trench all in one.

[0003] In actual manufacturing processes, due to process variations, such as via etch shift, the critical dimension (CD) between adjacent metal lines is reduced under the stress of the metal hard mask layer, such as titanium nitride (TiN). This results in poor filling effect of subsequent metals (such as copper), and in severe cases, voids are easily generated during the planarization process of the metal lines.

[0004] To detect voids or other defects in the actual manufactured metal wire, inline defect measurement is generally used. However, this method is susceptible to interference from other defects in the preceding structure, making it difficult to detect anomalies within the metal wire in a timely manner. Furthermore, the metal wire is exposed to the atmosphere for extended periods during the measurement process, posing a risk of corrosion. Additionally, this method is limited by production capacity and other factors, preventing 100% measurement accuracy of the metal wire. Utility Model Content

[0005] Therefore, it is necessary to provide a semiconductor defect detection structure for detecting defects in the metal wires of semiconductor devices, so as to quickly detect whether there are defects in the metal wires without damaging the semiconductor device structure.

[0006] This application provides a semiconductor defect detection structure for detecting defects in the metal wires of semiconductor devices, including:

[0007] The metal wire under test;

[0008] A plurality of interconnecting metal lines, each of which is provided with a plurality of spaced-apart metal connectors;

[0009] At least one side of the to-be-tested metal line is provided with a plurality of the interconnecting metal lines, different parts of the to-be-tested metal line are parallel to different interconnecting metal lines, and the distance between the to-be-tested metal line and each interconnecting metal line is the same.

[0010] In one of the embodiments, the ratio of the distance between the to-be-tested metal line and each interconnecting metal line to the minimum design width of the metal wire ranges from 0.9 to 1.

[0011] In one of the embodiments, both sides of a set position in the to-be-tested metal line are provided with the interconnecting metal lines, and part of the metal connectors on the interconnecting metal lines are symmetrically arranged with the extension direction of the to-be-tested metal line at the set position as the axis of symmetry.

[0012] In one of the embodiments, the to-be-tested metal line includes a plurality of first straight edges and a plurality of second straight edges, the first straight edges and the second straight edges are connected in sequence, and the extension direction of the first straight edge intersects with the extension direction of the second straight edge; wherein, the first straight edges and the second straight edges are parallel to each other and provided with a plurality of the interconnecting metal lines.

[0013] In one of the embodiments, the to-be-tested metal line has an arch shape, and the to-be-tested metal line includes three U-shaped corner regions.

[0014] The interconnecting metal lines include:

[0015] Three first interconnecting metal lines, the first interconnecting metal lines have a U shape, and different first interconnecting metal lines are arranged in different U-shaped corner regions of the to-be-tested metal line.

[0016] A plurality of second interconnecting metal lines, the second interconnecting metal lines have a straight line shape, and the second interconnecting metal lines are arranged on a side of the U-shaped corner region away from the first interconnecting metal lines.

[0017] In one of the embodiments, the to-be-tested metal line has a spiral shape, and the to-be-tested metal line includes a first central square region and a plurality of first straight edges and second straight edges arranged around the first central square region.

[0018] The interconnecting metal lines include:

[0019] A third interconnecting metal line, the third interconnecting metal line has a square shape, and the third interconnecting metal line is located in the first central square region.

[0020] a plurality of fourth interconnection metal lines, each of the fourth interconnection metal lines being linearly shaped and disposed on a side of the first straight edge or the second straight edge away from the first central square region.

[0021] In one embodiment, the under-test metal line is helically shaped and includes a second central square region and a plurality of first straight edges and second straight edges disposed around the second central square region.

[0022] The interconnection metal line is helically shaped and includes a plurality of sequentially connected interconnection metal straight edges disposed around the second central square region.

[0023] The interconnection metal line is disposed on a side of the under-test metal line away from the second central square region, and each of the interconnection metal straight edges is disposed on a side of the first straight edge or the second straight edge away from the second central square region.

[0024] In one embodiment, the under-test metal line has test pads disposed at two ends thereof.

[0025] In one embodiment, the under-test metal line, the interconnection metal line, the metal connector and the metal wire are made of the same material and include at least one of metal copper and metal aluminum.

[0026] In one embodiment, the semiconductor defect detection structure is located in a semiconductor device, and the semiconductor device includes at least:

[0027] a semiconductor substrate;

[0028] a dielectric barrier layer disposed on the semiconductor substrate;

[0029] an interlayer dielectric layer disposed on the dielectric barrier layer, the interlayer dielectric layer having a trench and a via hole formed therein, the via hole penetrating through the interlayer dielectric layer and the dielectric barrier layer;

[0030] the metal interconnection layer includes the metal wire, the under-test metal line and the interconnection metal line disposed in the trench, and the metal connector disposed in the via hole.

[0031] The unexpected effect of the present application is that: by arranging a plurality of interconnection metal wires with metal connectors on at least one side of the to-be-tested metal wire to simulate the actual arrangement mode of the metal wires in the semiconductor device, by arranging the metal wires, the to-be-tested metal wire and the interconnection metal wire in the metal interconnection layer of the semiconductor device at the same time, the preparation environment of the semiconductor defect detection structure and the metal wires is ensured to be the same, and the defects in the metal wires and the semiconductor defect detection structure caused by the etching offset of the via hole or the internal stress are also consistent, so that whether the metal wires in the semiconductor device have defects can be judged according to the resistance change of the to-be-tested metal wire, which is beneficial to improve the defect detection efficiency and coverage rate of the metal wires, greatly shortens the time required for defect detection in the metal wires, and reduces or even avoids the risk of corrosion caused by the exposure of the metal wires in the defect detection. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 It is a structural schematic diagram of forming a first photoresist layer in a double damascene process method in the related art.

[0034] Figure 2 It is a structural schematic diagram corresponding to the step of forming an opening in a double damascene process method in the related art.

[0035] Figure 3 It is a structural schematic diagram corresponding to the step of forming a second photoresist layer in a double damascene process method in the related art.

[0036] Figure 4 It is a structural schematic diagram corresponding to the step of etching the interlayer dielectric layer in a double damascene process method in the related art.

[0037] Figure 5 It is a structural schematic diagram corresponding to the step of forming a metal layer in a double damascene process method in the related art.

[0038] Figure 6 It is a schematic diagram of the case when the sidewall of the interlayer dielectric layer is inclined due to stress in a double damascene process method in the related art.

[0039] Figure 7 It is a structural schematic diagram of the to-be-tested metal wire in the semiconductor defect detection structure provided by an embodiment of the present application when the shape of the to-be-tested metal wire is an arch shape.

[0040] Figure 8 A structure diagram of a semiconductor defect detection structure provided by an embodiment of the present application, in which only the shape of the metal line to be detected is spiral.

[0041] Figure 9 A structure diagram of a semiconductor defect detection structure provided by an embodiment of the present application, in which the shapes of the metal line to be detected and the interconnection metal line are both spiral.

[0042] Figure 10 A cross-sectional structure diagram of a semiconductor device in a semiconductor defect detection structure provided by an embodiment of the present application.

[0043] Legend of reference numerals:

[0044] 100 - bottom copper metal layer; 110 - first interlayer dielectric layer; 111 - barrier layer; 112 - first dielectric layer; 113 - second dielectric layer; 120 - metal hard mask layer; 130 - anti-reflective layer; 131 - first anti-reflective layer; 132 - second anti-reflective layer; 140 - first photoresist layer; 141 - opening; 142 - second photoresist layer; 150 - metal interconnection structure; 151 - interconnection layer; a - metal via; b - metal line; c - metal trench; 152 - metal barrier layer;

[0045] 200 - semiconductor substrate; 210 - dielectric barrier layer; 220 - second interlayer dielectric layer; 221 - trench; 222 - via; 230 - metal interconnection layer; 231 - metal wire;

[0046] P - semiconductor defect detection structure; X - metal line to be detected; x1 - first straight side; x2 - second straight side; Y - interconnection metal line; y1 - first interconnection metal line; y2 - second interconnection metal line; y3 - third interconnection metal line; y4 - fourth interconnection metal line; Z - metal connector; D - distance between the metal line to be detected and the interconnection metal line; A1 - first central square region; A2 - second central square region; B - set position. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The drawings show embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and, similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0050] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatial description language used herein can be interpreted accordingly.

[0051] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0052] In a general dual damascene process, the critical dimension (CD) between adjacent metal lines can be reduced due to the etching bias or the stress in the partial film layer, which can cause defects in the formed metal lines.

[0053] For example, in a process of preparing an interconnection layer of a semiconductor device by using a dual damascene process, referring to Figure 1 The semiconductor device includes at least a bottom copper metal layer 100, a first interlayer dielectric layer 110, a metal hard mask layer 120, an anti-reflective layer 130 and a patterned first photoresist layer 140 from bottom to top. Optionally, the first interlayer dielectric layer 110 includes at least a barrier layer 111, a first dielectric layer 112 and a second dielectric layer 113 arranged from bottom to top, wherein the barrier layer 111 is a nitride doped silicon carbide (NDC) layer, the first dielectric layer 112 is a BD layer and the second dielectric layer 113 is a TEOS layer. Optionally, the metal hard mask layer 120 is a titanium nitride (TiN) layer. Optionally, the anti-reflective layer 130 includes a first anti-reflective coating (ARC) layer 131 and a bottom anti-reflective coating (BARC) layer 132. Optionally, the first photoresist layer 140 is formed with an opening 141 to define the profile of a metal trench in the semiconductor device.

[0054] Then, referring to Figure 2 The opening 141 is etched through the anti-reflective layer 130, the metal hard mask layer 120 and at most a part of the second dielectric layer 113 by using the first photoresist layer 140 as a mask. Optionally, a dry etching process is used to etch the anti-reflective layer 130, the metal hard mask layer 120 and the second dielectric layer 113. Optionally, the first photoresist layer is removed after the etching process.

[0055] Subsequently, referring to Figure 3A second anti-reflective material is spin-coated to cover the sidewalls and bottom of the opening 141 with a second anti-reflective layer 132, and a patterned second photoresist layer 142 is formed on the second anti-reflective layer 132 to define the topography of the metal via of the semiconductor device.

[0056] Referring to Figure 3 and Figure 4 the anti-reflective layer 130, the first ILD layer 110 and the barrier layer 111 are etched with the second photoresist layer 142 as a mask to form a metal interconnect structure 150. The metal interconnect structure 150 includes a metal trench (not shown) in the first ILD layer 110 and a metal via (not shown) extending through the first ILD layer 110 and the barrier layer 111. Optionally, the second photoresist layer 142 and the second anti-reflective layer 132 are removed after the formation of the metal interconnect structure 150.

[0057] Next, referring to Figure 4 and Figure 5 a metal material is filled in the metal interconnect structure 150 and planarized to form an interconnect layer 151. Optionally, the material of the interconnect layer 151 can be metal copper (Cu), metal aluminum (Al) or other metal material or alloy material with good conductivity. Optionally, a metal barrier layer 152 is formed between the interconnect layer 151 and the first ILD layer 110, the barrier layer 111 and the bottom Cu metal layer 100.

[0058] Optionally, the planarization process is performed on the interconnect layer 151 while the first anti-reflective layer 131, the metal hard mask layer 120 and the second ILD layer 113 are removed, so that the remaining interconnect layer 151 is flush with the surface of the first ILD layer 112. Optionally, a chemical mechanical polishing (CMP) process is used for the planarization. At this time, the interconnect layer 151 includes at least a metal line (not shown) formed in the metal trench and an electrical connector (not shown) formed in the metal via.

[0059] During the formation of the metal via, when the overlapping value (OVL) is greater than 12 nm, a void is generated in the metal line near the metal via. After many experiments, it is found that when the metal line is provided with metal vias on both sides, the metal line is more prone to void defects. Meanwhile, the greater the offset of the metal via, the smaller the critical dimension (CD) of the metal line near the metal via, and the greater the probability of void defects in the metal line.

[0060] In addition, referring to Figure 6In the etching process of forming the metal interconnection structure, the first interlayer dielectric layer 110 can be tilted due to internal stress, causing the critical dimension of part of the metal trench c to be reduced, thereby causing a void defect in the metal line b subsequently formed in the metal trench c.

[0061] In order to detect whether there is a void defect in the interconnection layer of the semiconductor device, it is usually necessary to pretreat the semiconductor device to expose the interconnection layer in the semiconductor device, and to observe the actual morphology of the interconnection layer by electron microscopy to determine whether there is a defect in the interconnection layer. However, this method has a long detection time, and the interconnection layer is exposed to the risk of corrosion after exposure, which may generate new defects and affect the accuracy of the defect detection result.

[0062] To solve the above problems, the present application provides a semiconductor defect detection structure for defect detection of metal wires of a semiconductor device to quickly detect whether there is a defect in the metal wires without damaging the structure of the semiconductor device.

[0063] Referring to Figure 7 In one embodiment of the present application, the semiconductor defect detection structure P includes a metal wire to be tested X and a plurality of interconnection metal wires Y, each of which is provided with a plurality of metal connectors Z spaced from each other; wherein at least one side of the metal wire to be tested X is provided with a plurality of interconnection metal wires Y, and the distance D between the metal wire to be tested X and each interconnection metal wire Y is the same, and the metal wire (not shown in the figure), the metal wire to be tested X and the interconnection metal wire Y are all arranged in the metal interconnection layer (not shown in the figure) of the semiconductor device (not shown in the figure).

[0064] As can be seen, the semiconductor defect detection structure P provided in one embodiment of the present application simulates the possible defect conditions of the metal wires in the semiconductor device by arranging a plurality of interconnection metal wires Y with metal connectors Z on at least one side of the metal wire to be tested X. Since the metal wire, the metal wire to be tested X and the interconnection metal wire Y are all arranged in the metal interconnection layer of the semiconductor device, they are prepared in the same process environment. If the metal wire in the semiconductor device has a defect due to etching offset or internal stress of the via, the metal wire to be tested X in the same metal interconnection layer as the metal wire will also have the same defect due to etching offset or internal stress of the metal connectors in the interconnection metal wire. Therefore, when the semiconductor defect detection structure P provided in the present application is used for defect detection of the metal wire, whether there is a defect in the metal wire of the semiconductor device can be determined according to the resistance change of the metal wire to be tested without exposing the metal wire, effectively improving the defect detection efficiency and coverage rate of the metal wire, greatly shortening the time required for defect detection in the metal wire, and reducing or even avoiding the risk of corrosion of the metal wire in the defect detection.

[0065] With reference to Figure 7 In one embodiment, the ratio of the distance D between the metal line X under test and each interconnection metal line Y to the minimum design width of the metal line in the semiconductor device is in the range of 0.9 to 1. That is, the distance D between the metal line X under test and the interconnection metal line Y is greater than or equal to 90% of the minimum design width in the semiconductor device and less than or equal to the minimum design width in the semiconductor device, so as to ensure that the metal line X under test and the interconnection metal line Y can simulate the actual situation between adjacent metal lines in the semiconductor device. It should be noted that the smaller the distance between the metal line X under test and the interconnection metal line Y, the easier it is to detect the case that the metal line X under test has a width due to the etching offset of the metal connector Z in the interconnection metal line Y, and the case that the metal line X under test has a defect due to internal stress (the causes of the specific defects are described in the foregoing part), so as to determine whether the metal lines in the same metal interconnection layer have defects.

[0066] With reference to Figure 7 In one embodiment, the metal line X under test has interconnection metal lines Y on both sides of a set position B, and the metal connectors Z on the interconnection metal lines Y on both sides of the metal line X under test are symmetrically arranged with the extension direction of the metal line X under test at the set position B as the axis of symmetry. It should be noted that the set position B of the metal line X under test between the symmetrically arranged metal connectors Z has a higher probability of having a hollow defect due to the etching offset of the metal via.

[0067] With reference to Figure 7 In one embodiment, the metal line X under test includes a plurality of first straight edges x1 and a plurality of second straight edges x2, the first straight edges x1 and the second straight edges x2 are connected in sequence, and the extension direction of the first straight edge x1 (i.e., the M direction in the figure) and the extension direction of the second straight edge x2 (i.e., the N direction in the figure) are crossed; a plurality of interconnection metal lines Y are arranged in parallel on both sides of the first straight edge x1 and both sides of the second straight edge x2. Optionally, the extension direction of the first straight edge x1 (i.e., the M direction) and the extension direction of the second straight edge x2 (i.e., the N direction) are perpendicular. In other embodiments of the present application, the shape of the metal line under test can also be a curved line or other shapes, and the shapes and arrangement of the metal line under test and the interconnection metal line can be set according to the shapes and arrangement of the metal line in the semiconductor device, which is not limited in the present application. Figure 7 Figure 7 In one embodiment, the metal line X under test includes a plurality of first straight edges x1 and a plurality of second straight edges x2, the first straight edges x1 and the second straight edges x2 are connected in sequence, and the extension direction of the first straight edge x1 (i.e., the M direction in the figure) and the extension direction of the second straight edge x2 (i.e., the N direction in the figure) are crossed; a plurality of interconnection metal lines Y are arranged in parallel on both sides of the first straight edge x1 and both sides of the second straight edge x2. Optionally, the extension direction of the first straight edge x1 (i.e., the M direction) and the extension direction of the second straight edge x2 (i.e., the N direction) are perpendicular. In other embodiments of the present application, the shape of the metal line under test can also be a curved line or other shapes, and the shapes and arrangement of the metal line under test and the interconnection metal line can be set according to the shapes and arrangement of the metal line in the semiconductor device, which is not limited in the present application.

[0068] ​It should be noted that in the metal line X to be detected of the semiconductor defect detection structure P, the number of the first straight edges x1 and the second straight edges x2 can be the same, or the first straight edges x1 can be one more (or one less) than the second straight edges x2, to ensure that all the first straight edges x1 and the second straight edges x2 can be sequentially connected to form a complete metal line X to be detected.

[0069] Meanwhile, it should be emphasized that the interconnection metal lines Y are arranged in parallel on both sides of the first straight edges x1, which means that at least one first straight edge x1 has an interconnection metal line Y arranged in parallel on one side, and at least one first straight edge x1 has an interconnection metal line Y arranged in parallel on the other side, to simulate the case that the metal conductor extending in the same direction as the first straight edge x1 has a via arranged on one side and the other side, respectively.

[0070] In one embodiment, the interconnection metal lines Y can be arranged on both sides of the same first straight edge x1, or two different first straight edges x1 can be selected, one of which has an interconnection metal line Y arranged in parallel on one side, and the other of which has an interconnection metal line Y arranged in parallel on the other side. In other embodiments of the present application, the arrangement between the first straight edge x1 and the interconnection metal line Y can be adjusted as needed, as long as the arrangement of the first straight edge x1 and the interconnection metal line Y can simulate the case that the metal conductor extending in the same direction as the first straight edge x1 has a via arranged on both sides.

[0071] Correspondingly, the arrangement of the interconnection metal lines Y on both sides of the second straight edge x2 is the same as the arrangement of the interconnection metal lines Y on both sides of the first straight edge x1, and can also be adjusted as needed, as long as the arrangement of the second straight edge x2 and the interconnection metal line Y can simulate the case that the metal conductor extending in the same direction as the second straight edge x2 has a via arranged on both sides. Therefore, this application will not be described here.

[0072] Continuing to refer to Figure 7 In one embodiment, the shape of the metal line X to be detected is in the shape of an arch, and the metal line X to be detected includes three U-shaped corner regions (U1, U2, and U3) Figure 7 The area enclosed by the dashed line in the middle is one of the U-shaped corner regions. Meanwhile, the interconnection metal lines Y include three first interconnection metal lines y1 and a plurality of second interconnection metal lines y2, wherein the first interconnection metal lines y1 are in the shape of a U, and different first interconnection metal lines y1 are arranged in different U-shaped corner regions; the second interconnection metal lines y2 are in the shape of a straight line, and the second interconnection metal lines y2 are arranged on the side of the U-shaped corner region away from the first interconnection metal lines y1.

[0073] Referring to Figure 8In one embodiment, the metal line X to be tested has a spiral shape, and includes a first central square area A1 and a plurality of first straight edges x1 and second straight edges x2 arranged around the first central square area A1. Meanwhile, the interconnection metal line Y includes a third interconnection metal line y3 and a plurality of fourth interconnection metal lines y4, wherein the third interconnection metal line y3 has a square shape and is located within the first central square area A1; the plurality of fourth interconnection metal lines y4 have a straight shape, and each of the fourth interconnection metal lines y4 is arranged on a side of the first straight edge x1 or the second straight edge x2 away from the first central square area A1.

[0074] Referring to Figure 9 In one embodiment, the metal line X to be tested has a spiral shape, and includes a second central square area A2 and a plurality of first straight edges x1 and second straight edges x2 arranged around the second central square area A2. Meanwhile, the interconnection metal line Y has a spiral shape, and includes a plurality of interconnection metal straight edges L2 arranged around the second central square area A2 in sequence; wherein the interconnection metal line Y is arranged on a side of the metal line X to be tested away from the second central square area A2, and each of the interconnection metal straight edges L2 is arranged on a side of the first straight edge x1 or the second straight edge x2 away from the second central square area A2.

[0075] It should be noted that, Figures 7 to 9 The above are only three example cases of the semiconductor defect detection structure P in the present application. In other embodiments of the present application, the semiconductor defect detection structure P can be arranged according to the metal interconnection structure in the semiconductor device to be tested, so as to simulate the actual situation of the metal line in the semiconductor device, thereby improving the accuracy of the defect detection result.

[0076] In one embodiment, the metal line to be tested has test pads arranged at both ends thereof, so as to lead out the metal line to be tested, thereby performing electrical property test on the metal line to be tested without exposing the film layer where the metal line to be tested is located, and avoiding new defects caused by the exposure and corrosion of the metal line to be tested.

[0077] Referring to Figure 10In one embodiment, the semiconductor defect detection structure is located in a semiconductor device, which includes at least a semiconductor substrate 200, a dielectric barrier layer 210, an interlayer dielectric layer (i.e., a second interlayer dielectric layer 220), and a metal interconnection layer 230. The dielectric barrier layer 210 is located on the semiconductor substrate 200. The interlayer dielectric layer (i.e., the second interlayer dielectric layer 220) is located on the dielectric barrier layer 210, and the interlayer dielectric layer (i.e., the second interlayer dielectric layer 220) has a trench 221 and a via 222 formed therein. The via 222 penetrates the interlayer dielectric layer (i.e., the second interlayer dielectric layer 220) and the dielectric barrier layer 210. The metal interconnection layer 230 includes a metal wire 231 located in the trench 221, a metal under test (not labeled in the figure), an interconnection metal wire (not labeled in the figure), and a metal connector (not labeled in the figure) located in the via 222.

[0078] In one embodiment, the metal under test, the interconnection metal wire, the metal connector, and the metal wire 231 are formed in the same deposition process, and thus, the metal under test, the interconnection metal wire, the metal connector, and the metal wire 231 are made of the same material, which includes at least one of copper and aluminum. That is, the material of the metal interconnection layer 230 includes at least one of copper and aluminum. In other embodiments of the present application, the material of the metal interconnection layer 230 can also be other metal materials or alloy materials with good conductivity, which are not limited in the present application. Optionally, the semiconductor substrate 200 further includes a bottom metal layer (not shown in the figure) in contact with the metal connector Z. Optionally, the material of the dielectric barrier layer 210 includes carbon-doped silicon nitride. Optionally, the material of the interlayer dielectric layer (i.e., the second interlayer dielectric layer 220) includes an oxide of silicon or a material containing silicon dioxide, such as at least one of SiO2, TEOS, or BD.

[0079] Continuing to refer to Figure 10 In one embodiment, the semiconductor device further includes a passivation layer (not shown in the figure) covering the metal interconnection layer 230 (i.e., the passivation layer covers the metal under test, the interconnection metal wire, the metal wire 231, and the metal connector) to reduce or avoid corrosion damage to the metal interconnection layer 230.

[0080] The unexpected effect of the present application is that: by arranging a plurality of interconnection metal wires with metal connectors on at least one side of the to-be-tested metal wire to simulate the actual arrangement mode of the metal wires in the semiconductor device; by arranging the metal wires, the to-be-tested metal wire and the interconnection metal wire in the metal interconnection layer of the semiconductor device at the same time, the preparation environment of the semiconductor defect detection structure and the metal wires is ensured to be the same, and the defect conditions caused by the via etching offset or internal stress in the metal wires and the semiconductor defect detection structure are also consistent, so that whether the metal wires in the semiconductor device have defects can be judged according to the resistance change of the to-be-tested metal wire, which is beneficial to improve the defect detection efficiency and detection coverage of the metal wires, greatly shortens the time required for defect detection in the metal wires, and reduces or even avoids the risk of corrosion caused by the exposure of the metal wires in the defect detection.

[0081] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments" and the like means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0082] The technical features of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0083] The above-mentioned embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as a limitation on the patent application scope. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor defect detection structure for defect detection of a metal wire of a semiconductor device, characterized by, The application relates to a semiconductor device, which comprises: a metal wire to be tested; a plurality of interconnecting metal wires, each of which is provided with a plurality of metal connectors spaced from each other; wherein a plurality of the interconnecting metal wires are arranged in parallel on at least one side of the metal wire to be tested, and the distance between the metal wire to be tested and each of the interconnecting metal wires is the same, and the metal wire, the metal wire to be tested and the interconnecting metal wires are arranged in a metal interconnection layer of the semiconductor device.

2. The semiconductor defect detection structure of claim 1, wherein The ratio of the distance between the metal wire to be tested and each of the interconnecting metal wires to the minimum design width of the metal wire is in the range of 0.9-1.

3. The semiconductor defect detection structure according to claim 1 or 2, characterized by, The interconnecting metal wires are arranged on both sides of a set position of the metal wire to be tested, and part of the metal connectors on the interconnecting metal wires are symmetrically arranged with the extending direction of the metal wire to be tested at the set position as the axis of symmetry.

4. The semiconductor defect detection structure according to claim 1 or 2, characterized by, The metal wire to be tested comprises a plurality of first straight edges and a plurality of second straight edges, the first straight edges and the second straight edges are connected in sequence, and the extending direction of the first straight edge intersects with the extending direction of the second straight edge; wherein a plurality of the interconnecting metal wires are arranged in parallel on both sides of the first straight edge and both sides of the second straight edge.

5. The semiconductor defect detection structure of claim 4, wherein The metal wire to be tested has an arch shape, and comprises three U-shaped corner regions. The interconnecting metal wires comprise: three first interconnecting metal wires, which have a U shape, and different first interconnecting metal wires are arranged in different U-shaped corner regions of the metal wire to be tested; a plurality of second interconnecting metal wires, which have a straight line shape, and the second interconnecting metal wires are arranged on a side of the U-shaped corner region away from the first interconnecting metal wire.

6. The semiconductor defect detection structure of claim 4, wherein The metal wire to be tested has a spiral shape, and comprises a first central square region and a plurality of first straight edges and second straight edges arranged around the first central square region; The interconnecting metal wires comprise: a third interconnecting metal wire, which has a square shape, and the third interconnecting metal wire is located in the first central square region; a plurality of fourth interconnecting metal wires, which have a straight line shape, and each of the fourth interconnecting metal wires is arranged on a side of a first straight edge or a second straight edge away from the first central square region.

7. The semiconductor defect detection structure of claim 4, wherein The metal wire to be tested has a spiral shape, and comprises a second central square region and a plurality of first straight edges and second straight edges arranged around the second central square region; The interconnecting metal wires have a spiral shape, and the interconnecting metal wires comprise a plurality of interconnecting metal straight edges arranged around the second central square region; wherein the interconnecting metal wires are arranged on a side of the metal wire to be tested away from the second central square region, and each of the interconnecting metal straight edges is arranged on a side of a first straight edge or a second straight edge away from the second central square region.

8. The semiconductor defect detection structure of claim 1, wherein Test pads are arranged at both ends of the metal wire to be tested.

9. The semiconductor defect detection structure of claim 1, wherein The material of the to-be-tested metal line, the interconnection metal line, the metal connecting piece and the metal wire is the same, and is metal copper or metal aluminum.

10. The semiconductor defect detection structure of claim 1, wherein The semiconductor defect detection structure is located in the semiconductor device, and the semiconductor device at least comprises: a semiconductor substrate; a dielectric barrier layer located on the semiconductor substrate; an interlayer dielectric layer located on the dielectric barrier layer, the interlayer dielectric layer being provided with a groove and a via hole, the via hole penetrating through the interlayer dielectric layer and the dielectric barrier layer; the metal interconnection layer comprising the metal wire, the to-be-tested metal line and the interconnection metal line located in the groove, and the metal connecting piece located in the via hole.

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