Semiconductor device and aging test fixture

Abstract

The utility model relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and an aging test fixture, which comprises a plurality of chips, penetrating electrodes and peripheral electrodes, each chip is provided with a front electrode and a back electrode, the back electrodes of the plurality of chips are communicated with each other to form an integral electrode, and the penetrating electrodes are arranged on the periphery electrodes. The through electrodes are connected in series with the front electrodes of at least part of the chips, and the peripheral electrodes are connected with the through electrodes. By means of the arrangement, chips with defects can be screened out at the wafer end, the yield loss caused by subsequent aging test loss at the packaging end is greatly reduced, and the cost is saved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor manufacturing, especially relates to a semiconductor device and aging test fixture. BACKGROUND

[0002] In the production process of semiconductor laser products, some defects are inevitably introduced in the complex epitaxy and process, and these defects may not be initially apparent, which requires Burn-in aging to screen out these defective chips in advance. Burn-in aging of the chip needs to be under certain environmental and current conditions, to accelerate various physical and chemical reaction processes inside the chip, to make various potential defects hidden in the chip exposed as soon as possible, so as to achieve the purpose of removing early failure products. Since the normal semiconductor laser chip is small in size, it is difficult to perform Burn-in aging at the chip end, and it is necessary to package the chip into a module or a device before Burn-in aging, which increases the production cost of the overall device. Early screening of defective chips can greatly improve the time cost and production cost of the device.

[0003] The existing Burn-in aging test methods mainly include TO (Transistor Outline) packaging aging and needle card type wafer level aging box method.

[0004] TO packaging aging is to cut the wafer into dies, test the dies, then select a certain number of dies uniformly and randomly in the wafer, package the dies on TO (Transistor Outline), then perform Burn-in aging on the dies, and finally use this statistical approximation to represent that the wafer is reliable. However, this method has the disadvantage that even if the chips in the wafer are shipped to the customer end, the customer still needs to perform Burn-in on the chips that have not been Burn-in, and the failure cost generated after Burn-in at the customer end will be several times that of the chip end.

[0005] The needle card type wafer level aging box is mainly used for wafer level aging of VCSEL laser, and uses a needle card matched with the wafer design to simultaneously age each chip in the wafer in the aging box. The advantage is that it can perform Burn-in screening on the chip in advance, and the disadvantage is that the style of the needle card needs to be changed in real time according to the size of the chip and the design of the wafer, the compatibility is poor, the stability of the needle card power supply is high, the uniformity of the wafer thickness is required, the process process capability is required, the cost of the needle card is high, and the stability is poor.

[0006] Therefore, how to provide a structure for completing the aging test at the wafer end at low cost has become one of the technical problems to be solved by those skilled in the art.

[0007] It should be noted that the information disclosed in this part of the background is only intended to increase the understanding of the overall background of the utility model, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. Content of the utility model

[0008] The utility model provides a kind of semiconductor device, it includes several chips, through electrode and peripheral electrode, each chip has front electrode and back electrode, the back electrode of several chips is interconnected to form a whole electrode.Through electrode is connected to the front electrode of at least part chip in series.

[0009] The utility model also provides a kind of aging test fixture, it is used to carry out aging test to semiconductor device, semiconductor device uses the semiconductor device as described above, aging test fixture includes carrier plate and cover plate, carrier plate and cover plate have a containing cavity between, semiconductor device is arranged in containing cavity, first test electrode is arranged on the side of carrier plate close to cover plate, first test electrode connects back electrode, second test electrode is arranged on the side of cover plate close to carrier plate, and second test electrode connects peripheral electrode.

[0010] The semiconductor device and aging test fixture provided by the utility model, through electrode is connected to the front electrode of chip in series, and is connected to peripheral electrode outside, so that the chip with defect itself can be screened out at wafer end, the yield loss caused by subsequent aging test loss at packaging end is greatly saved, and cost is saved.

[0011] Other features and advantages of the utility model will be described in the subsequent specification, and part of the technical features and advantages can be obtained from the specification, or be understood by implementing the utility model. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or prior art, the drawings needed to be used in the embodiment or prior art description will be briefly introduced as follows, obviously, part of the drawings in the following description is some embodiments of the utility model, and those skilled in the art can obtain other drawings according to these drawings without creating creative labor.

[0013] Figure 1 It is the top view structural schematic diagram of semiconductor device provided by the first embodiment of the utility model;

[0014] Figure 2 is a top view structural schematic diagram of a semiconductor device provided by the second embodiment of the utility model;

[0015] Figure 3 is a structural schematic diagram of an aging test fixture provided by an embodiment of the utility model;

[0016] Figure 4 is a top view structural schematic diagram of an aging test fixture provided by an embodiment of the utility model

[0017] Reference signs:

[0018] 10-chip; 101-front electrode; 102-back electrode; 12-penetrating electrode; 14-peripheral electrode; 141-first peripheral electrode; 142-second peripheral electrode; 16-dicing lane; 21-first test area; 22-second test area; 30-carrier plate; 32-cover plate; 34-housing cavity; 36-first test electrode; 38-second test electrode; 381-electrode block. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be described clearly and completely below in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. The technical features designed in different embodiments of the utility model described below can be combined with each other as long as they do not conflict with each other. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the utility model.

[0020] In the description of the utility model, it is understood that the orientation or position relationship indicated by the terms "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is the orientation or position relationship shown in the drawings, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the devices or components indicated must have a particular orientation, or be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the utility model. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the utility model, unless otherwise specified, the meaning of "multiple" is two or more. In addition, the term "includes" and any variation thereof means "at least includes".

[0021] Please refer to Figure 1 , Figure 1 is a top view structural schematic diagram of a semiconductor device provided by the first embodiment of the present application. To achieve at least one of the above advantages or other advantages, the first embodiment of the present application provides a semiconductor device. As shown in the figure, the semiconductor device comprises a plurality of chips 10, through electrodes 12 and peripheral electrodes 14.

[0022] Each chip 10 has a front electrode and a back electrode. The chip 10 can be a laser chip. The chip 10 can be an EEL chip or a VCSEL chip. In some embodiments, each chip 10 comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer. The light-emitting layer is located between the first semiconductor layer and the second semiconductor layer, the front electrode is connected to the first semiconductor layer, and the back electrode is connected to the second semiconductor layer. The front electrode and the back electrode can be made of a metal material.

[0023] The first semiconductor layer can be a P-type semiconductor layer, which can provide holes to the light-emitting layer under the action of a power source. The P-type semiconductor layer comprises a P-type doped nitride layer. The P-type doped nitride layer can comprise one or more P-type impurities. The P-type impurities can include one or a combination of Mg, Zn and Be. The P-type semiconductor layer comprises a P-type cover layer and a P-type ohmic layer, and the P-type cover layer is located between the P-type ohmic layer and the light-emitting layer. The P-type cover layer can be a Mg-doped AlGaN layer. The P-type ohmic layer can be a P-GaN layer.

[0024] The light-emitting layer comprises a first waveguide layer, a quantum well layer and a second waveguide layer which are stacked in sequence. The first waveguide layer and the second waveguide layer are used to confine light between the two waveguide layers and form laser emission by oscillation. Both the first waveguide layer and the second waveguide layer can be InGaN layers. The first waveguide layer and the second waveguide layer have a higher band gap and a lower refractive index than the quantum well layer; the first waveguide layer has a lower band gap and a higher refractive index than the N-type cover layer; and the second waveguide layer has a lower band gap and a higher refractive index than the P-type cover layer.

[0025] The quantum well layer can be a multiple quantum well structure (MQW), which comprises a plurality of well layers (Well) and a plurality of barrier layers (Barrier) arranged alternately in a repeated manner, such as a GaN / AlGaN, InAlGaN / InAlGaN or InGaN / AlGaN multiple quantum well structure. In addition, in order to improve the light-emitting efficiency of the light-emitting layer, the depth of the quantum well, the number of layers and the thickness of the paired quantum well and quantum barrier can be changed to achieve the light-emitting efficiency.

[0026] The second semiconductor layer can be an N-type semiconductor layer that can provide electrons to the light emitting layer under the action of a power source. The second semiconductor layer includes an N-type doped nitride layer. The N-type doped impurities can include one or a combination of Si, Ge, and Sn. The second semiconductor layer includes an N-type cover layer, which can be an AlGaN layer with a low doped Si concentration.

[0027] The front electrode and the back electrode are distributed on different sides of the light emitting layer, for example, the front electrode is located on the upper side of the light emitting layer, and the back electrode is located on the lower side of the light emitting layer.

[0028] The back electrodes of the plurality of chips 10 are connected to each other to form a whole electrode. That is, the back electrodes of the plurality of chips 10 are a whole electrode that is shared.

[0029] The through electrode 12 is connected to the front electrodes of at least some of the chips 10. The peripheral electrode 14 is connected to the through electrode 12. The through electrode 12 and the peripheral electrode 14 can be made of a metal material. In some embodiments, the back electrode includes, but is not limited to, an open back light shield or a whole surface gold plating process.

[0030] Through the design of the through electrode 12 penetrating the front electrodes of the chips 10 and being connected to the peripheral electrode 14 on the outside, the design ensures that the P-side electrodes of the chips 10 are all connected together. The purpose of the peripheral electrode 14 is to ensure that the front electrodes of the chips 10 are all connected to each other. In this way, when the peripheral electrode 14 is powered, it is equivalent to powering all the P-side electrodes at the same time, so that the chips 10 with defects can be screened out at the wafer end, avoiding the yield loss caused by subsequent aging tests at the packaging end.

[0031] In some embodiments, there is a cutting path 16 between two adjacent chips 10, which is used for subsequent purposes such as laser cutting to separate single chips 10. When viewed from above, the through electrode 12 penetrates the cutting path 16, thereby ensuring that the front electrodes of the chips 10 are all connected to each other.

[0032] In some embodiments, when viewed from above, a plurality of chips 10 are located inside the peripheral electrode 14 to ensure that the front electrodes of the chips 10 are all connected to each other.

[0033] Figure 1 For the purpose of simplification and illustration, only an embodiment of four chips 10 is shown. However, the present application is not limited thereto, and in some embodiments, the number of the plurality of chips 10 is at least 100.

[0034] In some embodiments, the through electrode 12 connects the front electrodes of all the chips 10 to ensure that the front electrodes of all the chips 10 are all connected to each other.

[0035] Please refer toFigure 2 , compared with Figure 1 The difference between the embodiment and the semiconductor device shown in Figure 1 is that, viewed from above, the semiconductor device has at least a first test region 21 and a second test region 22. There are partial chips 10 in the first test region 21 and the second test region 22. The design in each test region can refer to the structure design shown in Figure 1 . The peripheral electrode 14 includes a first peripheral electrode 141 and a second peripheral electrode 142, the first peripheral electrode 141 surrounds the chip 10 located in the first test region 21, the second peripheral electrode 142 surrounds the chip 10 located in the second test region 22, and the first peripheral electrode 141 and the second peripheral electrode 142 have a pitch, which is greater than 0. That is, the first peripheral electrode 141 and the second peripheral electrode 142 are not in direct contact. In this way, the chips 10 in different test regions can be subjected to different Burn-in aging tests, improving the research and development efficiency. In the embodiment, four test regions are divided, but the case is not limited thereto, and more test regions can be divided according to actual needs. In addition, the subsequent aging test fixture can also be designed in a four-way manner. The advantage of this design is that the four quarters of the semiconductor device can be subjected to different Burn-in tests, achieving more efficient verification.

[0036] In some embodiments, because thousands of chips 10 need to be powered at the same time, a large current output is required. The large-area semiconductor device can be disassembled into small-size block units. When the number of chips 10 is large, the block units can be powered separately, reducing the pressure on the source table. At this time, the aging test fixture only needs to adapt to the modification of the upper fixture patch design, and the lower fixture does not need to be modified, and can be compatible with multiple designs at the same time, including but not limited to various sizes of blocks, circles, and the like.

[0037] Please refer to Figure 3 and Figure 4 , Figure 3 is a structure schematic view of an aging test fixture provided by an embodiment of the utility model, Figure 4 is a top view structure schematic view of an aging test fixture provided by an embodiment of the utility model. The aging test fixture is used for aging test of a semiconductor device, and the semiconductor device adopts the semiconductor device provided by any of the preceding embodiments. As shown in Figure 3 , the aging test fixture includes a carrier plate 30 and a cover plate 32. The carrier plate 30 and the cover plate 32 have a receiving cavity 34 therebetween, and the semiconductor device is arranged in the receiving cavity 34.

[0038] The first test electrode 36 is provided on the side of the carrier plate 30 close to the cover plate 32, and is used to connect the back surface electrode of the semiconductor device. The second test electrode 38 is provided on the side of the cover plate 32 close to the carrier plate 30, and is used to connect the peripheral electrode 14 of the semiconductor device. In some embodiments, the second test electrode 38 can include a plurality of electrode blocks 381, each of which is connected to the peripheral electrode 14 to supply power.

[0039] During the aging process, the semiconductor device is supplied with power through the carrier plate 30 and the cover plate 32 of the clamp, respectively. After aging, the defects in the chip 10 are triggered in advance, and the Burn-in test is performed after aging, so that the defective chips 10 can be screened in advance. In combination with the change data before and after Burn-in, the aging screening condition is formulated to ensure the reliability of the shipped chips 10.

[0040] In summary, the semiconductor device and the aging test clamp provided by the utility model can connect the front surface electrodes of the chips 10 in series through the penetrating electrodes 12, and connect to the peripheral electrodes 14 outside, so that the chips 10 with defects can be screened at the wafer end, and the yield loss caused by subsequent aging test at the packaging end is greatly saved, and the cost is saved.

[0041] In addition, those skilled in the art should understand that although there are many problems in the prior art, each embodiment or technical solution of the utility model can only be improved in one or several aspects, and it is not necessary to solve all the technical problems listed in the prior art or background art at the same time. Those skilled in the art should understand that the content not mentioned in a claim should not be regarded as a limitation of the claim.

[0042] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the utility model, and not to limit them; although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solutions of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized by: The semiconductor device comprises a plurality of chips, through electrodes and peripheral electrodes, each of the chips has a front electrode and a back electrode, the back electrodes of the plurality of chips are in communication with each other to form an integral electrode; The through electrodes are connected in series to the front electrodes of at least part of the chips; The peripheral electrodes are connected to the through electrodes.

2. The semiconductor device of claim 1, wherein: Each of the chips comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer, the light-emitting layer is located between the first semiconductor layer and the second semiconductor layer, the front electrode is connected to the first semiconductor layer, and the back electrode is connected to the second semiconductor layer.

3. The semiconductor device of claim 1, wherein: There is a cutting channel between two adjacent chips, and the through electrode passes through the cutting channel when viewed from the top.

4. The semiconductor device of claim 1, wherein: The chip is an EEL chip or a VCSEL chip.

5. The semiconductor device of claim 1, wherein: When viewed from the top, the plurality of chips are located inside the peripheral electrodes.

6. The semiconductor device of claim 1, wherein: The number of the plurality of chips is at least 100.

7. The semiconductor device of claim 1, wherein: The through electrodes are connected in series to the front electrodes of all the chips.

8. The semiconductor device of claim 1, wherein: When viewed from the top, the semiconductor device has at least a first test area and a second test area, part of the chips are located in the first test area and the second test area, the peripheral electrodes comprise a first peripheral electrode and a second peripheral electrode, the first peripheral electrode surrounds the chips located in the first test area, the second peripheral electrode surrounds the chips located in the second test area, the first peripheral electrode and the second peripheral electrode have a spacing, and the spacing is greater than 0.

9. An aging test fixture characterized by: The aging test fixture is used for aging test of a semiconductor device, the semiconductor device adopts the semiconductor device according to any one of claims 1-8, the aging test fixture comprises a carrier plate and a cover plate, the carrier plate and the cover plate have a receiving cavity therebetween, the semiconductor device is arranged in the receiving cavity, the carrier plate is provided with a first test electrode on a side close to the cover plate, the first test electrode is connected to the back electrode, the cover plate is provided with a second test electrode on a side close to the carrier plate, and the second test electrode is connected to the peripheral electrode.

10. The burn-in test fixture of claim 9, wherein: The second test electrode comprises a plurality of electrode blocks, and the electrode blocks are connected to the peripheral electrode.

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