Integrated circuit

Abstract

According to an embodiment of the present application, an integrated circuit is provided and includes: a first active region of a first conductivity type coupled to an input / output pad; a second active region of a second conductivity type different from the first conductivity type coupled to the first supply voltage terminal; a plurality of first gate structures extending along a first direction to pass through the first active region and the second active region; and a first well of a second conductivity type extending in the first direction. The first and second active regions extend in the first well in a second direction different from the first direction, and the first active region is aligned with the second active region in the first direction.

Description

TECHNICAL FIELD

[0001] The present application relates to an integrated circuit, and more particularly, to an integrated circuit including an electrostatic discharge path. BACKGROUND

[0002] An electrostatic discharge (ESD) event can generate a very high voltage and cause a large current pulse for a short time, which can damage an integrated circuit device. Therefore, it is necessary for an integrated circuit to be equipped with appropriate ESD protection devices between input / output pads and internal core circuits to prevent the internal core circuits from being affected by unwanted ESD current. SUMMARY

[0003] In an integrated circuit device, adjacent active regions release electrostatic discharge (ESD) current along their extension direction. However, due to the narrow regions of the active regions and the resistance of the well in which the active regions are located, the ESD current encounters significant resistance when flowing through these regions. In addition, due to the uneven distance between active regions of different conductivity types (e.g., P-type and N-type), the ESD current flowing through different active regions is not released at the same time, which reduces the ESD protection capability of the integrated circuit device.

[0004] To address at least the above problems, an integrated circuit is provided and includes a first active region of a first conductivity type coupled to an input / output pad, a second active region of a second conductivity type different from the first conductivity type coupled to a first power supply voltage terminal, a plurality of first gate structures extending in a first direction to pass through the first active region and the second active region, and a first well of the second conductivity type extending in the first direction. The first active region and the second active region extend in a second direction different from the first direction in the first well, and the first active region is aligned with the second active region in the first direction.

[0005] Another integrated circuit is provided and includes a first well of a first conductivity type forming a polygon, and a plurality of first active regions arranged in the first well, wherein each of the first active regions is disposed in a corresponding region of a plurality of cell rows arranged in a first direction. At least one first region of the first active regions is coupled to an input / output pad and disposed in at least one flange portion of the first well. At least one second region of the first active regions is coupled to a first power supply voltage terminal and disposed in a web portion of the first well.

[0006] This application also provides an integrated circuit comprising a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type, wherein the first active region and the second active region are disposed in a first well of the second conductivity type; and a first gate structure extending along a first direction through the first active region and the second active region, wherein the first active region and the first gate structure are coupled to an input / output pad, and the second active region is coupled to a first power supply voltage terminal. The first active region, the first gate structure, and the first well are contained in a first transistor, wherein the first transistor and the second active region are used to discharge a first electrostatic discharge current flowing between the input / output pad and the first power supply voltage terminal.

[0007] The integrated circuit provided in this application allows ESD currents flowing through different sections to discharge simultaneously between two parallel active regions. Furthermore, the increased width of the active regions and the sink through which the ESD current flows reduces the resistance of the ESD discharge path. This improves the performance and reliability of the integrated circuit ESD protection device. Attached Figure Description

[0008] An embodiment of this application will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] FIG. 1A This is a block diagram of a portion of an integrated circuit according to some embodiments;

[0010] FIG. 1B It is based on some embodiments corresponding to FIG. 1A A schematic diagram of the corresponding integrated circuit;

[0011] FIG. 2A According to some embodiments, corresponding to such FIGS. 1A-1B A schematic diagram of the layout of a portion of the integrated circuit shown;

[0012] FIG. 2B According to some embodiments, corresponding to such FIG. 2A A schematic diagram of the layout of a portion of the integrated circuit shown;

[0013] FIG. 2C According to some embodiments FIG. 2B A schematic diagram of the cross-sectional view of the AA integrated circuit section along the middle line;

[0014] FIG. 2D According to some embodiments FIG. 2B A schematic diagram of the cross-sectional view of the BB integrated circuit section along the middle line;

[0015] FIG. 2E is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in FIG. 2B FIG. 2 is a schematic diagram of a cross-sectional view along line CC of the integrated circuit portion in

[0016] FIG. 2F is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in FIGS. 1A-1B FIG. 4 is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in

[0017] FIG. 3 is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in FIGS. 1A-1B FIG. 6 is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in

[0018] FIG. 4A is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in FIGS. 1A-1B FIG. 8 is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in

[0019] FIG. 4B is a schematic diagram of a cross-sectional view along line DD of the integrated circuit portion in FIG. 4A FIG. 10 is a schematic diagram of a cross-sectional view along line EE of the integrated circuit portion in

[0020] FIG. 5 is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in FIGS. 1A-1B FIG. 12 is a schematic diagram of a layout corresponding to a portion of an integrated circuit as shown in

[0021] FIG. 6 is a schematic diagram of a cross-sectional view along line DD of the integrated circuit portion in FIG. 5 FIG. 14 is a schematic diagram of a cross-sectional view along line EE of the integrated circuit portion in

[0022] FIG. 7 is a block diagram of a system for designing an integrated circuit layout design according to various embodiments;

[0023] FIG. 8 is a block diagram of an integrated circuit manufacturing system according to various embodiments, and an integrated circuit manufacturing flow associated with the integrated circuit manufacturing system.

[0024]

SYMBOL DESCRIPTION

[0025] 10, 10A-D: integrated circuit

[0026] 100: input / output device

[0027] 101: ESD protection device

[0028] 102: receiver / transmitter

[0029] 110: I / O pad

[0030] 111: power supply voltage terminal

[0031] 112: power supply voltage terminal

[0032] 120: power clamp circuit

[0033] 130: logic circuit

[0034] ESD: electrostatic discharge

[0035] ESDP: ESD path

[0036] ESDN: ESD path

[0037] IN: ESD current

[0038] DP: diode

[0039] DN: diode

[0040] VDD: power supply voltage

[0041] VSS: power supply voltage

[0042] TP: transistor

[0043] TN: transistor

[0044] 10AA: portion

[0045] PrBoundary: boundary

[0046] Metal: metal

[0047] 201-226: active region

[0048] 203a: region

[0049] 204a: region

[0050] 301-303: gate structure

[0051] 301a: gate dielectric layer

[0052] 401-405: conductive line

[0053] CELL1, CELL3, CELL4, CELL5: cell CELL3a, CELL3b: sub-cell CH21, CH31, CH41, CH51: ROW0-ROW15: cell row

[0054] RH1: row height

[0055] RH2: row height

[0056] NW21-NW23: N-well NW21a: flange portion NW21b: flange portion NW21c: web portion

[0057] NW31: N well

[0058] NW41: N well

[0059] NW51: N well

[0060] NW51a: flange portion NW51b: flange portion

[0061] NW51c: web portion

[0062] PS: substrate

[0063] W21 - W24: width

[0064] W31 - W32: width

[0065] W41 - W42: width

[0066] CW21, CW31, CW41, CW51: cell width

[0067] x, y: direction

[0068] AA, BB, CC, DD: line

[0069] 2051, 2052: fin structure

[0070] 2061, 2062: fin structure

[0071] 700: electronic design automation (EDA) system

[0072] 710: I / O interface

[0073] 720: processor

[0074] 730: network interface

[0075] 740: network

[0076] 750: bus

[0077] 760: memory

[0078] 761: instruction

[0079] 762: standard cell library

[0080] 763: user interface (UI)

[0081] 770: manufacturing tool

[0082] 800: IC manufacturing system

[0083] 810: design room

[0084] 811: IC design layout

[0085] 820: Mask room

[0086] 821: Data preparation

[0087] 822: Mask manufacturing

[0088] 823: Mask

[0089] 830: Fab

[0090] 831: Wafer manufacturing

[0091] 832: Wafer

[0092] 840: IC device DETAILED DESCRIPTION

[0093] The following disclosure provides many different embodiments, or examples, for implementing various characteristics of the provided subject matter. Specific examples of components and configurations are described below to simplify the present application. These are, of course, merely examples and are not intended to be limiting. For example, while the making of first and second features over or on top of each other in the following description can comprise embodiments in which the first and second features are formed in direct contact, it can also comprise embodiments in which additional features can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters in the various examples can be repeated in various instances, without intent to limit the examples to the particular illustrative implementations. The repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not itself dictate a relationship between various examples and / or configurations discussed.

[0094] The terminology used in this specification generally has one generally meaning in the art and in the specific context in which each term is used. Examples of terminology used in this specification, including examples of any terms discussed herein, are for illustrative purposes only and are not limiting on the scope or meaning of the disclosure or any exemplified term. Similarly, an embodiment of the application is not limited to the various embodiments given in this specification.

[0095] Although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0096] As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," "involves," and the like can be understood to be open-ended: i.e., to mean including but not limited to.

[0097] As used herein, "about," "approximately," "almost," or "substantially" shall generally mean any value that is reasonably close to a given value or range of values, where the close approximation is relative to the various technologies employed by the various embodiments, and the close approximation should be understood as encompassing all such modifications and equivalent structures as would be appreciated by those skilled in the art to which the embodiments pertain, in order to encompass all such modifications and equivalent structures. In some embodiments, "about" shall generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range of values. Quantities given herein as approximations can mean that the term "about," "approximately," "almost," or "substantially" can be inferred even if not explicitly stated, or that other approximations are meant.

[0098] Reference is now made to FIG. 1A . FIG. 1A is a block diagram of a portion of an integrated circuit 10 according to some embodiments. For illustration, the integrated circuit 10 includes an input / output device 100 coupled to an input / output (I / O) pad 110, a power clamp circuit 120, and a logic circuit 130. The input / output device 100, the power clamp circuit 120, and the logic circuit 130 are coupled in parallel between power supply voltage terminals 111 and 112. In some embodiments, the power supply voltage terminal 111 is to provide a power supply voltage VDD, and the power supply voltage terminal 112 is to provide a power supply voltage VSS that is less than the power supply voltage VDD, e.g., the power supply voltage VSS is a ground voltage.

[0099] In some embodiments, the input / output device 100 includes an electrostatic discharge (ESD) protection device 101 and a receiver / transmitter 102 coupled between the power supply voltage terminals 111 and 112. The ESD protection device 101 includes diodes DP and DN. An anode of the diode DP, a cathode of the diode DN, and one terminal of the receiver / transmitter 102 are coupled to the I / O pad 110. A cathode of the diode DP and an anode of the diode DN are coupled to the power supply voltage terminals 111 and 112, respectively.

[0100] In some embodiments, the logic circuit 130 is coupled to the I / O pad 110 through the I / O device 100. For example, the logic circuit 130 is to receive a signal input from the I / O pad 110 through the I / O device 100, or to send a signal output to the I / O pad 110 through the I / O device 100. In some embodiments, the logic circuit 130 includes logic or circuitry to process or respond to an external signal transmitted through the I / O pad 110.

[0101] During an electrostatic discharge event, a large positive potential is transiently accumulated at the I / O pad 110, which is typically caused by direct or indirect contact with an electrostatic field. When an ESD event occurs, a plurality of ESD paths are turned on in the integrated circuit 10, e.g., including the ESD protection device 101 and the receiver / transmitter 102. FIG. 1AThe illustrated ESD paths ESDP and ESDN direct discharge of the ESD current IN.

[0102] In particular, as FIG. 1A illustrated, a portion of the ESD charge current IN flows between the I / O pad 110 and the voltage terminal VSS and is directed to flow through the ESD path ESDP formed by the diode DP and the power clamp circuit 120. Another portion of the ESD charge current IN flows from the I / O pad 110 and is directly discharged to the power supply voltage terminal 111 through the ESDN path formed by the diode DN. Details of the semiconductor structures of the diode DP and the diode DN will be discussed in connection with FIGS. 1B-6 embodiments.

[0103] Reference is now made to FIG. 1B . FIG. 1B is a schematic diagram of a portion of the integrated circuit 10 corresponding to the FIG. 1A illustrated in accordance with some embodiments. In FIG. 1B embodiments, the diode DP is implemented by a P-conductivity type transistor TP and the diode DN is implemented by an N-conductivity type transistor TN. In some embodiments, the gate, source and drain of the transistor TP correspond to the anode of the diode DP and the base of the transistor TP corresponds to the cathode of the diode DP. The gate, source and drain of the transistor TN correspond to the cathode of the diode DN and the base of the transistor TN corresponds to the anode of the diode DN. In particular, the gate, source and drain of the transistor TP are coupled to one another at the I / O pad 110 and the base of the transistor TP is configured to receive the power supply voltage VDD. Similarly, the gate, source and drain of the transistor TN are coupled to one another at the I / O pad 110 and the base of the transistor TN is configured to receive the power supply voltage VSS.

[0104] FIGS. 1A-1B The configuration illustrated in FIG. 4 is for illustration only. Various implementations are within the scope of embodiments of the present application. For example, in some embodiments, the integrated circuit 10 further includes a decoupling capacitance device coupled between the I / O device 100 and the I / O pad 110. In some embodiments, the decoupling capacitance device is configured to stabilize the power supply in the integrated circuit 10.

[0105] Reference is now made to FIG. 2A . FIG. 2A is a schematic diagram of a layout corresponding to a portion of the integrated circuit 10A illustrated in FIGS. 1A-1B in accordance with some embodiments. In some embodiments, the integrated circuit 10A is configured relative to the integrated circuit 10, for example, as FIGS. 1A-1B illustrated in FIG. 4.

[0106] As FIG. 2AAs shown, integrated circuit 10A includes cell CELL1 arranged in several cell rows ROW0 to ROW7, which extend along the x-direction and are adjacent to each other along the y-direction. Cell CELL1 includes active regions (i.e., oxide diffusions, OD) 201-220, gate structures (i.e., polysilicon, PODE) 301-303, and conductive lines 401-405. For the purposes of illustration, cell rows ROW0-ROW7 include a first group of rows ROW0-ROW1, ROW4-ROW5 with row height RH1 and a second group of rows ROW2-ROW3, ​​ROW6-ROW7 with row height RH2. In some embodiments, row height RH1 is different from row height RH2. In various embodiments, row height RH1 is greater than row height RH2. In some embodiments, conductive lines 401-405 extend in the x-direction and are metal zero (MO) conductive wire-wound structures that provide power supply voltages VDD and VSS to cell CELL1.

[0107] In some embodiments, active regions 201 and 220 are N-type doped and correspond to the drain and source of a TN transistor. Active regions 201 and 220 are coupled to I / O pads 110 via vias VD. Active regions 214-215 and 218-219, of P-conductivity type, are coupled to power supply voltage terminal 112 to receive power supply voltage VSS.

[0108] The active regions 202-203 and 206-207 of the P-conductivity type in N-well NW21 and the active regions 208-209 and 212-213 of the P-conductivity type in N-well NW22 correspond to the drain and source of transistor TP. Active regions 202-203, 206-207, 208-209, and 212-213 are coupled to I / O pad 110 via via VD. Active regions 204-205 and 210-211 of the N-conductivity type are coupled to power supply voltage terminal 111 to receive power supply voltage VDD.

[0109] like FIG. 2A As shown, active regions 201 and 220 are arranged in cell rows ROW0 and ROW7, respectively. Active regions 202-207 in different cell rows ROW1-ROW6 extend along the x-direction in the N-well NW21 and are aligned and separated from each other along the y-direction. Active regions 204-205 are located between active regions 202-203 and 206-207.

[0110] exist FIG. 2AIn the layout perspective, the N-well NW21 extends along the y-direction to form a polygonal shape, such as a C-shape, and has an opening to expose the substrate PS on which the N-well NW21 is disposed. Specifically, the active regions 202-203 and 206-207 are disposed in two flange portions NW21a-NW21b of the C-shaped N-well NW21, and the active region 204-205 is disposed in a web portion NW21c of the N-well NW21. In some embodiments, the width W21 of the web portion NW21c is different from the width W22 of the flange portions NW21a-NW21b. For example, in the embodiment of FIG. 2A, the width W21 is smaller than the width W22. FIG. 2A In the embodiment of FIG. 2B, the width W21 is larger than the width W22.

[0111] The active regions 208-213 and the N-well NW22 are configured similarly to the active regions 202-207 and the N-well NW21. Therefore, the repeated description is omitted here. In addition, the web portions of the N-wells NW21-NW22 are arranged back-to-back, as shown in FIG. 2C. In other words, the openings of the N-wells NW21-NW22 are opposite along the x-direction. FIG. 2A

[0112] In some embodiments, the openings of the N-wells NW21-NW22 are for implementing the logic circuit 130 to abut the cell CELL1 (ESD protection cell) and other standard cells.

[0113] Referring to FIGS. 2A-2C together, FIGS. 1A-1B and FIG. 2A During an ESD negative-to-VSS (NS mode) or negative electrostatic discharge event, a large amount of negative potential is transiently accumulated at the I / O pad 110. The transistor TN is turned on to discharge the negative ESD current from the I / O pad 110 to the power voltage terminal 112 through the first semiconductor structure including the active region 201, the substrate PS, the active regions 214-215, and the second semiconductor structure including the active region 220, the substrate PS, and the active regions 218-219. As shown in FIG. 2D, the ESD current is discharged along the y-direction. FIG. 2A

[0114] According to some embodiments, during an ESD positive-to-VSS (PS mode) or positive electrostatic discharge event, the transistor TP and the power clamp circuit 120 are turned on to discharge the positive ESD current from the active regions 202-203 to the active regions 204 and from the active regions 206-207 to the active region 205 in the N-well NW21 along the Y-direction. The ESD current is also discharged from the active regions 208-209 to the active region 210 along the y-direction, and from the active regions 212-213 to the active region 211 in the N-well NW22.

[0115] ​​The gate structure 301-303 extends along the y direction to pass through several active regions in the cell CELL1. For example, the gate structure 301 passes through the active regions 304-305. In some examples, the gate structure 301 further extends to overlap the active regions 202, 203, 206, 207, or a combination thereof. The gate structures 302-303 are configured relative to, for example, the gate structure 301. Thus, the repeated description is omitted here. For the purpose of brevity and illustration, FIG. 2A Even FIG. 2F , FIG. 3 , FIG. 4A and FIG. 5 depict the positions of the gate structures. Various implementations are within the contemplation of an embodiment of the present application.

[0116] Referring to FIGS. 2B-2E , FIG. 2B is a schematic diagram of a layout corresponding to a portion 10AA of an integrated circuit 10A as shown in FIG. 2A , and FIGS. 2C-2D are schematic diagrams of cross-sectional views of portions of the integrated circuit along lines AA, BB, and CC, respectively, in accordance with some embodiments. FIG. 2B For the purpose of illustration,

[0117] the gate structure 301 in FIG. 2B extends along the y direction to pass through the active regions 203-204 and couple to the I / O pad 110. In some embodiments, the gate structure 301 corresponds to a gate of a transistor TP and is disposed above a gate dielectric layer 301a, as shown in a planar structure in FIG. 2C . In some embodiments of FIG. 2B , a width W23 of the active region 204 is less than a width of the active region 203 but greater than half of a width W21 of the web portion NW21c. As shown in FIG. 2B , an ESD current discharges through a region 203a in the active region 203 to a corresponding region 204a in the active region 204 and in a direction extending along the gate structure 301 within a spacing between the active regions 203-204. In particular, in FIG. 2C , the ESD current discharges through a parasitic diode between the region 203a and the N-well NW21 and flows in the y direction to the region 204a, as shown in FIG. 2D . A portion of the substrate PS is adjacent to the N-well NW21 along the y direction, as shown in FIG. 2B and FIG. 2E .

[0118] In some approaches, two adjacent P-doped and N-doped active regions discharge ESD current along the direction in which the P-doped and N-doped active regions extend, resulting in a significant resistance caused by the narrow region of the active regions and the N-well in which the active regions are located. In addition, due to the uneven distance between different portions of the N-doped active region to the P-doped active region, the partial ESD currents flowing through different portions of the P-doped active region do not discharge at the same time, thereby reducing the ESD protection capability.

[0119] In the configuration of the present application, during an ESD event, the partial ESD currents flowing through different portions discharge at the same time between the two parallel active regions. In addition, the width of the cross-section active region and the N-well through which the ESD current flows is increased, for example, in the present embodiment, the width is increased by about 3 times, thereby reducing the resistance of the ESD path. In this way, the performance and reliability of the ESD protection device are improved.

[0120] In addition, compared with some approaches, in the present application, the active regions of the same conductivity type are arranged in the same unit row, as FIG. 2A shown, which further avoids the area loss of the blank region between the two doped regions of different conductivity types. For example, the cell width CW21 of the cell CELL1 is reduced by about 33%, thereby saving the area of the integrated circuit and further reducing the manufacturing cost.

[0121] FIGS. 2A-2E The configuration of the present application is only for illustration. Various embodiments are within the intended scope of an embodiment of the present application. For example, in some embodiments of the present application, it is a schematic diagram corresponding to a layout diagram of a portion of an integrated circuit as FIG. 2F shown. In some embodiments of the present application, it is a schematic diagram corresponding to a layout diagram of a portion of an integrated circuit as FIGS. 1A-1B shown. In some embodiments of the present application, the N-well NW23 is configured relative to the N-well NW21, as FIG. 2B shown. In some embodiments of the present application, the N-well NW23 is configured relative to the N-well NW21, as FIG. 2F shown. In some embodiments of the present application, the N-well NW23 is configured relative to the N-well NW21, as FIG. 2B shown. In some embodiments of the present application, the N-well NW23 is configured relative to the N-well NW21, as FIG. 6 shown. In some embodiments of the present application, the transistors TP and TN are Fin-FETs, as shown, which will be discussed later.

[0122] Reference is now made to FIG. 3 . FIG. 3 is a schematic diagram corresponding to a layout diagram of a portion of an integrated circuit as FIGS. 1A-1B shown. In some embodiments of the present application, the N-well NW23 is configured relative to the N-well NW21, as FIGS. 1A-2F shown. In some embodiments of the present application, the N-well NW23 is configured relative to the N-well NW21, as FIG. 3For ease of understanding, identical elements in the text are assigned the same reference symbols. For the sake of brevity, the specific operations of similar elements have already been discussed in detail in the preceding paragraphs and will be omitted here.

[0123] and FIG. 2A In comparison, the cell height of cell CELL3 included in integrated circuit 10B is FIG. 2A The cell height CH21 of cell CELL1 is twice that of cell CELL3. The width of cell CELL3 is smaller than the width of cell CELL1. Integrated circuit 10B has two sub-cells CELL3a-CELL3b, which are adjacent to each other along the y-direction. In some embodiments, each sub-cell CELL3a-CELL3b is relative to, for example... FIG. 2A The cell CELL1 is configured. In some embodiments, the width W31 of the web portion of the N-well NW31 is smaller than the width W21. The configuration of each sub-cell CELL3a-CELL3b is similar to... FIG. 2A It is similar to cell CELL1. Therefore, repeated descriptions are omitted here.

[0124] Compared with some methods, the method described in this application is more efficient. FIG. 3 In one embodiment, the area of ​​integrated circuit 10B is reduced by approximately 49%. Furthermore, the width of the active region of the N-well through which the ESD current flows is increased; for example, the width of the N-well NW31 is increased, for example, in this embodiment, by approximately twice the width, thereby reducing the resistance of the ESD path.

[0125] Now for reference FIGS. 4A-4B . FIG. 4A According to some embodiments, corresponding to such FIGS. 1A-1B A schematic diagram of the layout of a portion of the integrated circuit 10C shown. FIG. 4B According to some embodiments FIG. 4A A schematic diagram of a cross-sectional view of the 10C portion of the DD integrated circuit along the middle line. Correspondingly... FIGS. 1A-3 In the embodiments, FIGS. 4A-4B For ease of understanding, identical elements in the same text are assigned the same reference symbol.

[0126] and FIG. 2A In contrast, instead of a semiconductor structure with transistors TN arranged between two N-wells NW21-NW22, integrated circuit 10C includes a cell CELL4 having transistors TP and TN arranged in parallel. Specifically, as FIG. 4AAs shown, multiple active regions are staggered along the y-direction in cell rows ROW0-ROW11. Active regions 201 and 220 correspond to transistor TN, and active regions 214 and 219 are coupled to power supply voltage terminal 112. Active regions 202-206 in the N-well NW41 are arranged in cell rows ROW7-ROW11. Active regions 202-203 and 206 correspond to transistor TP, and active regions 204-205 are coupled to power supply voltage terminal 111. FIG. 4A As shown, cell CELL4 also includes other active regions in cell rows ROW0-ROW1 and ROW6.

[0127] In some implementations, the N-well NW41 is relative to, for example... FIG. 2A Configure the N-well NW21. FIG. 4A The N-well NW41 is formed as a polygon. For example, the N-well NW41 is H-shaped, having a first flange portion NW41a including active regions 202-203, a second flange portion NW41b including active regions 206, and a web portion NW41c having active regions 204-205. The width W41 of the web portion NW41c is smaller than the width W42 of the first flange portion NW41a and the second flange portion NW41b.

[0128] Compared with some methods, the method using this application FIG. 4A The area of ​​the integrated circuit 10B configured in the embodiment is reduced by approximately 59%. Furthermore, the width of the active region of the N-well through which the ESD current flows is increased; for example, the width of the N-well NS41 is increased, for example, in this embodiment, by approximately 4.7 times, thereby reducing the resistance of the ESD path.

[0129] refer to FIG. 4B In a positive electrostatic discharge (ESD) event mode, the positive ESD current flows along the y-direction to the power supply voltage terminal 111, through active regions 202-203 and 206, and into active regions 204-205. In other embodiments, in a negative ESD event mode, the negative ESD current flows along the y-direction through active regions 221-220 and 201, and into active regions 2012 and 219 to the power supply voltage terminal 112.

[0130] Now for reference FIG. 5 . FIG. 5 According to some embodiments, corresponding to such FIGS. 1A-1B A schematic diagram of the layout of a portion of the integrated circuit 10D shown. Correspondingly... FIGS. 1A-4B In the embodiments, FIG. 5 For ease of understanding, identical elements in the same text are assigned the same reference symbol.

[0131] and FIG. 4AIn contrast, the integrated circuit 10D includes a cell CELL5, whose cell height CH51 is greater than that of a cell CELL4 with a cell height CH41. In some embodiments, cell CELL5 is configured relative to, for example, cell CELL4, and further includes an H-shaped N-well NW51, P-doped active regions 222-224 corresponding to transistor TP, and N-doped active regions 225-226. FIG. 5 As shown, N-wells NW41 and NW51 are arranged on opposite sides of active regions 201 and 214. In other words, the two parts of transistor TP are located on opposite sides of transistor TN.

[0132] For the purposes of this description, active region 222 is disposed in the first flange portion NW51a of N-well NW51, while active regions 223-224 are disposed in the second flange portion NW51b of N-well NW51. Active regions 225-226 are disposed in the web portion NW51c of N-well NW51.

[0133] Now for reference FIG. 6 . FIG. 6 According to some embodiments FIG. 5 A schematic diagram of a cross-sectional view of the EE integrated circuit section along the middle line. Correspondingly... FIGS. 1A-5 In the embodiments, FIG. 6 For ease of understanding, identical elements in the same text are assigned the same reference symbol.

[0134] exist FIG. 6 In this embodiment, transistors TP and TN are fin field-effect transistors (Fin-FETs). FIG. 6 As shown, in the first group "A", the cell rows ROW14-ROW15 with row height RH1 include active regions 205-206 on the N-well NW41. Active region 205 includes two fin structures 2051 and 2052, and active region 206 includes two fin structures 2061 and 2062. In other words, each of the active regions 205-206 includes two fin structures.

[0135] In some embodiments, fin structures 2051-2052 are N-type fin structures, and fin structures 2061-2062 are P-type fin structures.

[0136] like FIG. 6 As shown, in the second group "B", the cell rows ROW12-ROW13 with row height RH2 include two active regions 203-204 on the N-well NW41. The active region 203 of cell row ROW12 includes a first single-fin structure, while the active region 204 of cell row ROW13 includes a second single-fin structure. In other words, each of the active regions 203-204 includes a fin structure.

[0137] The fins mentioned above can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including a dual patterning or multi-level patterning process. In general, dual or multi-patterning processes combine photolithography and self-alignment processes to allow creation of patterns, e.g., with a pitch that is less than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed with the patterned sacrificial layer by a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0138] In some embodiments, such active regions can include one or more fin structures of one or more three-dimensional field effect transistors (e.g., FinFETs, gate-all-around (GAA) transistors), or oxide-defined (OD) regions of one or more planar metal-oxide-semiconductor field effect transistors (MOSFETs). The active regions can be used as source or drain features of the corresponding transistors.

[0139] In some embodiments, each active region 205-206 of cell rows ROW14-ROW15 includes two fin structures together as an active region to form an integrated circuit element (e.g., a transistor), such that the equivalent width of the active region of an integrated circuit element disposed on active region 205 or 206 will be wider than the width of another integrated circuit element disposed on active region 203 or 204 (which includes a first single fin structure). In other words, in some embodiments, integrated circuit elements disposed on cell rows ROW14 or ROW15 have better performance than integrated circuit elements disposed on cell rows ROW12 or ROW13.

[0140] Reference is now made to FIG. 7 According to some embodiments of the present application, FIG. 7 is a block diagram of an electronic design automation (EDA) system 700 for designing integrated circuit layout designs. EDA system 700 is used to manufacture integrated circuits 10, 10A-10D, and will be explained further in conjunction with FIGS. 1A-6 In some embodiments, EDA system 700 includes an APR system.

[0141] In some embodiments, the EDA system 700 is a general purpose computing device that includes a processor 720 and a (non-transitory) memory 760. The memory (computer-readable storage medium) 760 is encoded with (i.e., stores) instructions (computer program code) 761, namely a set of executable instructions. The instructions 761 are executed by the processor 720 to implement, at least in part, an EDA tool, e.g., to fabricate an integrated circuit 10, 10A-10D.

[0142] The processor 720 is electrically coupled to the memory 760 via a bus 750. The processor 720 is also electrically coupled to the I / O interface 710 and the fabrication tool 770 through the bus 750. The network interface 730 is also electrically connected to the processor 720 via the bus 750. The network interface 730 is connected to a network 740, so the processor 720 and the memory 760 can be connected to external elements via the network 740. The processor 720 is used to execute the instructions 761 encoded in the memory 760, so that the EDA system 700 can be used to perform part or all of a proposed process and / or method. In one or more embodiments, the processor 720 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0143] In one or more embodiments, the memory 760 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the memory 760 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a hard disk, and / or an optical disk. In one or more embodiments using an optical disk, the memory 760 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0144] In one or more embodiments, memory 760 stores instructions 761 for causing EDA system 700 (herein executing (at least partially) a representation of an EDA tool) to perform some or all of a proposed process and / or method. In one or more embodiments, memory 760 also stores information used in performing some or all of a proposed process and / or method. In one or more embodiments, memory 760 stores a library of standard cells 762, including standard cells as disclosed herein, e.g., cells including transistors MN1-MN5 and MP1- MP5.

[0145] EDA system 700 includes I / O interface 710. I / O interface 710 is coupled to external circuits. In one or more embodiments, I / O interface 710 includes a keyboard, keypad, mouse, trackball, touchpad, touch screen, and / or directional pad for communicating information and commands to processor 720.

[0146] EDA system 700 also includes network interface 730 coupled to processor 720. Network interface 730 allows EDA system 700 to communicate with network 740, to which one or more other computer systems are connected. Network interface 730 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or MA; or a wired network interface, such as ETHERNET, USB, or IEEE- 1364. In one or more embodiments, some or all of a proposed process and / or method is implemented in two or more systems 700.

[0147] EDA system 700 also includes manufacturing tool 770 coupled to processor 720. Manufacturing tool 770 is used to manufacture integrated circuits according to design files processed by processor 720, e.g., FIGS. 1A-6 the illustrated integrated circuits 10, 10A-10D.

[0148] EDA system 700 is used to receive information via I / O interface 710. Information received via I / O interface 710 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters processed by processor 720. Information is transferred to processor 720 via bus 750. EDA system 700 is used to receive information related to a UI via I / O interface 710. Information is stored in memory 760 as user interface (UI) 763.

[0149] In some embodiments, some or all of the proposed processes and / or methods are implemented as a stand-alone software application executed by a processor. In some embodiments, some or all of the proposed processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the proposed processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the proposed processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the proposed processes and / or methods are implemented as a software application used by EDA system 700. In some embodiments, a layout including standard cells is generated using a tool such as, ) or another suitable layout generation tool.

[0150] In some embodiments, a process is implemented as a function of a program stored in a non-transitory computer readable recording medium. Examples of non-transitory computer readable recording media include, but are not limited to, external / transportable and / or internal / built-in storage or memory units such as one or more of the following: optical discs such as DVDs; magnetic discs such as hard discs; semiconductor memory such as ROM, RAM, memory cards; and the like.

[0151] According to some embodiments, FIG. 8 is a block diagram of an IC manufacturing system 800, and an IC manufacturing flow associated with IC manufacturing system 800. In some embodiments, based on a layout, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using IC manufacturing system 800.

[0152] In FIG. 8 , IC manufacturing system 800 includes entities such as design house 810, mask house 820, and foundry (IC manufacturer / fabricator) 830 that interact with each other in a design, development, and manufacturing cycle and / or services related to manufacturing IC devices 840. The entities in IC manufacturing system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is multiple different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more of the other entities. In some embodiments, two or more of design house 810, mask house 820, and foundry 830 are owned by a single larger company. In some embodiments, two or more of design house 810, mask house 820, and foundry 830 coexist in a common facility and use common resources.

[0153] Design room (or design team) 810 produces IC design layout 811. IC design layout 811 includes geometric patterns, e.g., as discussed above with respect to IC device 840 design for, e.g., integrated circuit 10, 10A-10D. FIGS. 1A-6 FIG. 2A FIG. 2F FIG. 3 FIG. 4A FIG. 5 IC layout design depicted in, e.g., FIGS. 1-3. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of IC device 840 to be manufactured. Various layers are combined to form various IC features. For example, a portion of IC design layout 811 includes various IC features, such as active regions, gate electrodes, source and drain, conductive segments of interlayer interconnects, or vias, to be formed in a semiconductor substrate, such as a silicon wafer, and various material layers disposed on the semiconductor substrate. Design room 810 implements appropriate design procedures to form IC design layout 811. The design procedures include one or more of logic design, physical design, or placement routing. IC design layout 811 exists in one or more data files having information about the geometric patterns. For example, IC design layout 811 can be represented in GDSII file format or DFII file format.

[0154] Mask room 820 includes data preparation 821 and mask manufacturing 822. Mask room 820 uses IC design layout 811 to manufacture one or more masks 823 to be used to manufacture various layers of IC device 840 according to IC design layout 811. Mask room 820 performs mask data preparation 821 in which IC design layout 811 is translated into a representative data file (“RDF”). Mask data preparation 821 provides the RDF to mask manufacturing 822. Mask manufacturing 822 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as mask (photomask) 823 or (semiconductor) wafer 832. IC design layout 811 is manipulated by mask data preparation 821 to comply with specific characteristics of the mask writer and / or requirements of wafer fab 830. In some embodiments, data preparation 821 and mask manufacturing 822 can be referred to together as mask data preparation. FIG. 8 In some embodiments, data preparation 821 and mask manufacturing 822 can be referred to together as mask data preparation.

[0155] ​​​​​In some embodiments, data preparation 821 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for imaging errors, such as those that can be caused by diffraction, interference, other processing effects, and the like. OPC adjusts IC design layout 811. In some embodiments, data preparation 821 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, and the like, or a combination of these techniques. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0156] In some embodiments, data preparation 821 includes a mask rule checker (MRC) that checks IC design layout 811 for processes that have undergone OPC with a set of mask creation rules that contain specific geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, MRC modifies IC design layout 811 to compensate for restrictions during mask fabrication 822, which can undo portions of the modifications performed by OPC in order to satisfy the mask creation rules.

[0157] In some embodiments, data preparation 821 includes lithography process checking (LPC) that simulates the processing that will be performed by a foundry 830 to fabricate IC devices 840. LPC simulates this processing based on IC design layout 811 to create a simulated fabricated device, such as IC devices 840. The processing parameters in LPC simulation can include parameters associated with various processes of an IC fabrication cycle, parameters associated with tools used to fabricate ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or a combination of the foregoing. In some embodiments, after a simulated fabricated device has been created by LPC, if the simulated device is not sufficiently close in shape to satisfy design rules, then OPC and / or MRC should be repeated to further refine IC design layout 811.

[0158] It should be appreciated that the above description of data preparation 821 has been simplified for clarity. In some embodiments, data preparation 821 includes additional features, such as logic operations (LOPs) for modifying IC design layout 811 according to fabrication rules. Additionally, the processes applied to IC design layout 811 during data preparation 821 can be performed in a variety of different orders.

[0159] Following data preparation 821 and during mask fabrication 822, a mask 823 or a set of masks 823 is fabricated based on modified IC design layout 811. In some embodiments, mask fabrication 822 includes performing one or more photolithography exposures based on IC design layout 811. In some embodiments, an e-beam or multiple e-beams are used to form a pattern on mask (reticle or photomask) 823 based on modified IC design layout 811. Mask 823 can be formed using a variety of techniques. In some embodiments, mask 823 is formed using binary technology. In some embodiments, mask pattern includes opaque regions and transparent regions. A beam of radiation used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer, such as a beam of ultraviolet (UV) light, is blocked by opaque regions and transmitted through transparent regions. In one example, a binary mask version of mask 823 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 823 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 823, various features in the pattern formed on the phase shift mask are formed to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) produced by mask fabrication 822 will be used in a variety of processes. For example, the mask(s) will be used in ion implantation processes for forming various doped regions in wafer 832, in etching processes for forming various etched regions in wafer 832, and / or in other suitable processes.

[0160] The foundry 830 includes wafer fabrication 831. The foundry 830 is an IC manufacturing enterprise that includes one or more manufacturing facilities for fabricating a variety of different IC products. In some embodiments, the foundry 830 is a semiconductor foundry. For example, there can be a manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of a plurality of IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnection and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry enterprise.

[0161] The foundry 830 uses the mask 823 manufactured by the mask room 820 to manufacture IC devices 840. Thus, the foundry 830 uses the IC design layout 811, at least indirectly, to manufacture the IC devices 840. In some embodiments, the wafer 832 is manufactured by the foundry 830 using the mask 823 to form the IC devices 840. In some embodiments, the IC manufacturing includes performing one or more photolithography exposures based, at least indirectly, on the IC design layout 811. The wafer 832 includes a silicon substrate or other appropriate substrate having a plurality of material layers formed thereon. The wafer 832 further includes one or more of the following: various doped regions; dielectric features; multi-level interconnects; and the like (formed in subsequent manufacturing steps).

[0162] One embodiment of the present application provides an integrated circuit including an ESD protection device that includes active regions in a polygonal shaped well and a formed vertical ESD current discharge path. In the configuration of the present application, the ESD current is subjected to less resistance due to the increased width of the well and simultaneously discharged, thus providing enhanced ESD protection. Furthermore, in one embodiment of the present application, the active regions of the same conductivity type are arranged in the same cell row, which further avoids the area penalty of blank space between two doped regions of different conductivity types. In other words, the manufacturing cost of the integrated circuit is reduced.

[0163] According to one embodiment of the present application, an integrated circuit is provided and includes a first active region of a first conductivity type coupled to an input / output pad, a second active region of a second conductivity type different from the first conductivity type coupled to a first power supply voltage terminal, a plurality of first gate structures extending in a first direction to pass through the first active region and the second active region, and a first well of the second conductivity type extending in the first direction. The first active region and the second active region extend in a second direction different from the first direction in the first well, and the first active region is aligned with the second active region in the first direction.

[0164] In some embodiments, the integrated circuit further comprises: a third active region of the second conductivity type coupled to the first power supply voltage terminal; and a fourth active region of the first conductivity type coupled to the input / output pad. The third active region and the fourth active region are located in the first well, the third active region being located between the second active region and the fourth active region.

[0165] In some embodiments, the number of fins of the first active region and the second active region is different from the number of fins of the third active region and the fourth active region.

[0166] In some embodiments, the first well is C-shaped in a layout perspective.

[0167] In some embodiments, the first well is H-shaped. The first active region and the fourth active region are disposed in flange portions of the first well, and the second active region to the third active region are disposed in a web portion of the first well.

[0168] In some embodiments, the first active region and the second active region and the first well are to discharge an electrostatic discharge current flowing in the first direction.

[0169] In some embodiments, the integrated circuit further comprises: a third active region of the first conductivity type adjacent to the first active region in a first row and coupled to a second power supply voltage terminal; and a fourth active region of the second conductivity type in a second row separated from the first row in the first direction and coupled to the input / output pad.

[0170] In some embodiments, the integrated circuit further comprises: a third active region of the first conductivity type adjacent to the first active region in a first row and coupled to a second power supply voltage terminal; and a fourth active region of the second conductivity type in a second row separated from the first row in the first direction and coupled to the input / output pad. The third active region and the fourth active region are to discharge an electrostatic discharge current flowing in the first direction.

[0171] In some embodiments, the integrated circuit further comprises: a fifth active region of the first conductivity type coupled to the input / output pad; and a sixth active region of the second conductivity type coupled to the first power supply voltage terminal. The fifth active region and the sixth active region are located in a second well of the second conductivity type. The first well and the second well are C-shaped, web portions of the first well and the second well being back-to-back in a layout perspective.

[0172] In some embodiments, the integrated circuit further includes a third active region of the first conductivity type coupled to a second power supply voltage terminal; and a fourth active region of the second conductivity type coupled to the input / output pad, wherein the third active region and the fourth active region are to discharge an electrostatic discharge current flowing in the first direction. Each of the first active region to the fourth active region is disposed in a respective region of a plurality of cell rows arranged in the first direction.

[0173] According to an embodiment of the present application, an integrated circuit is provided and includes a first well of a first conductivity type forming a polygon; and a plurality of first active regions arranged in the first well, wherein each of the first active regions is disposed in a respective region of a plurality of cell rows arranged in a first direction. At least one first region of the first active regions is coupled to an input / output pad and is disposed in at least one flange portion of the first well. At least one second region of the first active regions is coupled to a first power supply voltage terminal and is disposed in a web portion of the first well.

[0174] In some embodiments, the at least one first region, the at least one second region, and the first well are to discharge an electrostatic discharge current flowing in the first direction. The at least one first region and the at least one second region have different conductivity types.

[0175] In some embodiments, the at least one first region includes a plurality of first regions, the at least one second region includes a plurality of second regions, and the at least one flange portion includes a first flange portion and a second flange portion. A first portion of the first regions is disposed in the first flange portion, a second portion of the first regions is disposed in a second flange portion. The second regions are between the first flange and the second flange portions.

[0176] In some embodiments, the at least one first region and the at least second region extend in a second direction different from the first direction. A width of the at least one first region is different from a width of the at least one second region.

[0177] In some embodiments, the integrated circuit further includes gate structures extending in the first direction, across the at least one first region and the at least second region, and coupled to the input / output pad.

[0178] According to an embodiment of the application, an integrated circuit is provided and includes a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type, wherein the first active region and the second active region are disposed in a first well of the second conductivity type; and a first gate structure extending in a first direction, passing through the first active region and the second active region, wherein the first active region and the first gate structure are coupled to an input / output pad, and the second active region is coupled to a first power supply voltage terminal. The first active region, the first gate structure, and the first well are included in a first transistor, wherein the first transistor and the second active region are to discharge a first electrostatic discharge current flowing between the input / output pad and the first power supply voltage terminal.

[0179] In some embodiments, the first active region is disposed in a first portion of the first well, and the second active region is disposed in a second portion of the first well. In a second direction different from the first direction, a width of the first portion of the first well is greater than a width of the second portion of the first well.

[0180] In some embodiments, the integrated circuit further includes a third active region of the second conductivity type coupled to the first power supply voltage terminal, and a fourth active region of the first conductivity type coupled to the input / output pad. The third active region and the fourth active region are located in the first well, and the second active region is between the first active region and the third active region.

[0181] In some embodiments, the integrated circuit further includes a third active region of the first conductivity type and a fourth active region of the second conductivity type, wherein the third active region and the fourth active region are disposed in a second well of the second conductivity type; and a fifth active region of the first conductivity type and a sixth active region of the second conductivity type are included in a second transistor. The second transistor and the fifth active region are to discharge a second electrostatic discharge current flowing between the input / output pad and a second power supply voltage terminal different from the first power supply voltage terminal. In the first direction, the first well and the second well are disposed on opposite sides of the fifth active region and the sixth active region.

[0182] In some embodiments, the first well and the second well are C-shaped.

[0183] In some embodiments, the first well and the second well are H-shaped.

[0184] The foregoing outlines features of several embodiments so that a thorough comprehension of the novel aspects of the application can be attained. Those skilled in the art should appreciate that the features of the application can be practiced in a variety of other forms other than that specifically set forth herein without departing from the spirit and scope of the present application. Those skilled in the art will further appreciate that the application can be used with any aqueous or nonaqueous system, for example, with liquid, gaseous, or solid substrates. In addition, though the application has been described in reference to particular embodiments, those skilled in the art will readily appreciate that other embodiments can be used and characteristics can be changed. For example, elements can typically be divided into multiple parts or created combined, and / or the instruction can be carried out more or less simultaneously, etc.

Claims

1. An integrated circuit, characterized by Comprising: a first active region of a first conductivity type coupled to an input / output pad; a second active region of a second conductivity type different from the first conductivity type coupled to a first power supply voltage terminal; a plurality of first gate structures extending in a first direction to pass through the first active region and the second active region; and a first well of the second conductivity type extending in the first direction, wherein the first active region and the second active region extend in a second direction different from the first direction in the first well, and the first active region is aligned with the second active region in the first direction. Further comprising:

2. The integrated circuit of claim 1, wherein, a third active region of the second conductivity type coupled to the first power supply voltage terminal; and a fourth active region of the first conductivity type coupled to the input / output pad, wherein the third active region and the fourth active region are located in the first well, the third active region being located between the second active region and the fourth active region. The first well is C-shaped in a layout perspective.

3. The integrated circuit of claim 2, wherein, The first well is H-shaped, 4. The integrated circuit of claim 2, wherein, wherein the first active region and the fourth active region are disposed in flange portions of the first well, and the second active region to the third active region are disposed in a web portion of the first well. The integrated circuit further comprises:

5. The integrated circuit of claim 1, wherein, a third active region of the first conductivity type adjacent to the first active region in a first row and coupled to a second power supply voltage terminal; and a fourth active region of the second conductivity type in a second row and coupled to the input / output pad, wherein the second row is separated from the first row in the first direction. The integrated circuit further comprises:

6. The integrated circuit of claim 5, wherein, a fifth active region of the first conductivity type coupled to the input / output pad; and a sixth active region of the second conductivity type coupled to the first power supply voltage terminal, wherein the first well and the second well are C-shaped, web portions of the first well and the second well being back-to-back arranged in a layout perspective. The integrated circuit further comprises:

7. The integrated circuit of claim 1, wherein, a third active region of the first conductivity type coupled to a second power supply voltage terminal; and a fourth active region of the second conductivity type coupled to the input / output pad, wherein the third active region and the fourth active region are to discharge an electrostatic discharge current flowing in the first direction, wherein each of the first active region to the fourth active region is disposed in a respective region in a plurality of cell rows arranged in the first direction. Comprising:

8. An integrated circuit, characterized by a first well of a first conductivity type forming a polygon; and a plurality of first active regions arranged in the first well, wherein each of the plurality of first active regions is disposed in a respective region in a plurality of cell rows arranged in a first direction, wherein at least one first region of the plurality of first active regions is coupled to an input / output pad and is disposed in at least one flange portion of the first well, wherein the first well is C-shaped in a layout perspective. wherein at least one second region of the plurality of first active regions is coupled to a first power supply voltage terminal and disposed at a web portion of the first well.

9. The integrated circuit of claim 8, wherein, The at least one first region and the at least one second region extend in a second direction different from the first direction, wherein a width of the at least one first region is different from a width of the at least one second region.

10. An integrated circuit, characterized by comprise: a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type, wherein the first active region and the second active region are disposed in a first well of the second conductivity type; and a first gate structure passing through the first active region and the second active region, wherein the first active region and the first gate structure are coupled to an input / output pad, the second active region is coupled to a first power supply voltage terminal, wherein the first active region, the first gate structure, and the first well are comprised in a first transistor, wherein the first transistor and the second active region are to discharge a first electrostatic discharge current flowing between the input / output pad and the first power supply voltage terminal.

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