Memory bank
By setting signal test points and ground test points on the memory module motherboard and connecting the memory chip pins with leads and resistors, self-testing is achieved, solving the high cost and soldering failure problems of the external interposer method, and improving testing efficiency and stability.
Patent Information
- Application Number
- CN202423191049.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2034-12-24
AI Technical Summary
Existing memory module testing methods using external interposers are costly, time-consuming, and carry the risk of soldering failures.
Signal test points and ground test points are set on the motherboard of the memory module, and electrically connected to the DQ, C/A, and CLK pins of the memory chip through leads. Resistors are used to suppress signal reflection to achieve self-testing.
It eliminates the procurement cycle and cost of test adapter cards, avoids poor soldering, and improves test stability.
Smart Images
Figure CN223612103U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of memory bank, specifically relates to a memory bank. BACKGROUND
[0002] With the continuous development of memory technology, the demand of memory capacity is continuously improved, and the number of storage particles on the memory bank is also continuously increased. The storage particles on the existing large-capacity memory bank often adopt the form of double-face opposite pasting, and the memory bank with such structure cannot directly measure the PIN pin of the storage particle or the back hole of the storage particle during SI test and PI test. The SI test is signal integrity test, and the PI test is power integrity test.
[0003] In addition, the storage particle often includes at least one DQ pin, at least one C / A, and at least one CLK pin, and the three types of pins are often tested during testing.
[0004] At present, in order to test the large-capacity memory bank, the industry mainly adopts the mode of externally connecting interposer to test the memory bank, wherein the interposer is a conversion board of the memory mainboard and the storage particle, and the signal measuring point is placed on the interposer. However, the mode of testing the memory bank by using the interposer has the following problems:
[0005] Firstly, high procurement cost is needed, and the procurement cycle is long, which is not conducive to the test of the memory bank;
[0006] Secondly, the interposer needs to be welded to the memory board, and there is a certain risk of welding failure. INVENTION CONTENTS
[0007] In view of the deficiencies in the background art, the utility model provides a memory bank, and the technical problem to be solved is that the existing memory bank adopts the mode of externally connecting interposer for testing, which has high cost, long cycle, and risk of welding failure.
[0008] To solve the above technical problems, the utility model provides the following technical scheme: a memory bank, comprising a memory bank mainboard, wherein a storage particle storage area is arranged on the memory bank mainboard, a storage particle matrix is arranged in the storage particle storage area, and at least one storage particle to be tested is included in the storage particle matrix.
[0009] The test DQ pin of the storage particle to be tested is electrically connected with a first resistor through a first lead wire, the test C / A pin of the storage particle to be tested is electrically connected with a second resistor through a second lead wire, the test CLK pin of the storage particle to be tested is electrically connected with a third resistor through a third lead wire, and the first resistor, the second resistor, and the third resistor are respectively electrically connected with a signal measuring point through a test lead wire.
[0010] The memory module mainboard is also provided with a ground measuring point.
[0011] In some embodiments, the signal measuring point is circular in shape, and the ground measuring point is rectangular in shape.
[0012] In some embodiments, when the number of DQ pins to be measured is greater than one, the length deviation of the first lead wire electrically connected to all the DQ pins to be measured is within 2 mils, and the impedance deviation of the first lead wire electrically connected to all the DQ pins to be measured is within ±10%.
[0013] When the number of C / A pins to be measured is greater than one, the length deviation of the second lead wire electrically connected to all the C / A pins to be measured is within 2 mils, and the impedance deviation of the second lead wire electrically connected to all the C / A pins to be measured is within ±10%.
[0014] When the number of CLK pins to be measured is greater than one, the length deviation of the third lead wire electrically connected to all the CLK pins to be measured is within 2 mils, and the impedance deviation of the third lead wire electrically connected to all the CLK pins to be measured is within ±10%.
[0015] In some embodiments, the total lead wire length between the signal measuring point and the pin to be measured is less than 5 mm.
[0016] In some embodiments, the distance between the first, second, and third resistors and the outermost memory particles of the adjacent side of the memory particle matrix is between 0.5 mm and 1 mm.
[0017] In some embodiments, the first, second, and third resistors are on the memory particle storage area, and the signal measuring point and the ground measuring point are on the memory module mainboard outside the periphery of the memory particle storage area.
[0018] In some embodiments, when the memory particle to be measured is in the uppermost row of the memory particle matrix, the first, second, and third resistors are above the memory particle matrix.
[0019] In some embodiments, when the memory particle to be measured is in the lowermost row of the memory particle matrix, the first, second, and third resistors are below the memory particle matrix.
[0020] In some embodiments, when the memory particle to be measured is between the uppermost row and the lowermost row of the memory particle matrix, the first, second, and third resistors are on the left side or the right side of the memory particle matrix, and the distance between the first, second, and third resistors on the side and the memory particle to be measured is less than the distance between the first, second, and third resistors on the other side and the memory particle to be measured.
[0021] In one embodiment, the first lead, the second lead, the third lead, the test lead, the first resistor, the second resistor, and the third resistor are on the surface of the memory module motherboard or inside the memory module motherboard.
[0022] The advantages of this invention compared to existing technologies are as follows: The memory module of this invention uses signal testing points set on the memory module motherboard. This allows for testing of the memory chips on the motherboard by testing these signal testing points, eliminating the need for an external test adapter and reducing the procurement cycle and cost of the adapter. Furthermore, placing the signal testing points on the memory module motherboard eliminates the need for soldering the test adapter, thus avoiding problems caused by poor soldering. Finally, the use of a first resistor, a second resistor, and a third resistor suppresses signal reflection, thereby improving test stability. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the memory module structure in the embodiment;
[0024] Figure 2 This is a schematic diagram showing the positions of the storage chip under test and the first, second, and third resistors at different locations in the embodiment. Detailed Implementation
[0025] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.
[0026] To address the shortcomings of testing existing high-capacity memory modules via an interposer, such as... Figure 1 As shown, this embodiment provides a memory module, including a memory module motherboard 1. The memory module motherboard 1 is provided with a memory chip storage area 2. The memory chip storage area 2 is provided with a memory chip matrix. The memory chip matrix includes at least one memory chip to be tested.
[0027] The DQ pin of the memory chip under test is electrically connected to the first resistor via the first lead 3, the C / A pin of the memory chip under test is electrically connected to the second resistor via the second lead 4, and the CLK pin of the memory chip under test is electrically connected to the third resistor via the third lead 5. The first resistor, the second resistor, and the third resistor are respectively electrically connected to the signal measurement point 7 via the test lead 6.
[0028] The motherboard 1 of the memory module also has a grounding test point 8.
[0029] In actual use, the memory bank of the utility model discloses a signal measuring point 7 is arranged on the memory bank mainboard 1, so that the to-be-tested storage particles of the memory bank mainboard 1 can be tested by testing the signal measuring point 7, thereby the memory bank test can be carried out without purchasing a test interposer, and the procurement cycle and procurement cost of the test interposer are omitted;
[0030] In addition, by arranging the signal measuring point 7 on the memory bank mainboard 1, the welding work of the test interposer can be saved, thereby the problem caused by poor welding can be avoided;
[0031] Finally, by arranging the first resistor, the second resistor and the third resistor, signal reflection can be suppressed, thereby the test stability is improved.
[0032] Specifically, in the embodiment, in order to distinguish the signal measuring point 7 and the grounding measuring point 8, the signal measuring point 7 is in a circular shape, and the grounding measuring point 8 is in a rectangular shape.
[0033] Since the DQ pin, the C / A pin and the CLK pin of the storage particle are not only one, in the embodiment, when the number of to-be-tested DQ pins is greater than one, the length deviation of the first lead line 3 electrically connected to all the to-be-tested DQ pins is within 2 mils, and the impedance deviation of the first lead line 3 electrically connected to all the to-be-tested DQ pins is within ±10%;
[0034] When the number of to-be-tested C / A pins is greater than one, the length deviation of the second lead line 4 electrically connected to all the to-be-tested C / A pins is within 2 mils, and the impedance deviation of the second lead line 4 electrically connected to all the to-be-tested C / A pins is within ±10%;
[0035] When the number of to-be-tested CLK pins is greater than one, the length deviation of the third lead line 5 electrically connected to all the to-be-tested CLK pins is within 2 mils, and the impedance deviation of the third lead line 5 electrically connected to all the to-be-tested CLK pins is within ±10%.
[0036] Specifically, in the embodiment, the total lead line length between the signal measuring point 7 and the to-be-tested pin needs to be as short as possible, wherein the total lead line length between the signal measuring point 7 and the to-be-tested pin can be less than 5 mm.
[0037] In addition, as shown in the figure, Figure 2 In the embodiment, the distance between the first resistor, the second resistor and the third resistor and the outermost storage particle of the adjacent side of the storage particle matrix is between 0.5 mm and 1 mm. Figure 2 Each resistor in the figure represents the first resistor, the second resistor and the third resistor for testing the to-be-tested storage particle, and in addition, Figure 2Each circle in the storage particle storage area 2 in the figure represents a storage particle, and all the circles form a storage particle matrix, and the storage particle connected with the lead is the storage particle to be tested, wherein the position of the storage particle to be tested is set according to actual requirements, and is not limited here.
[0038] Specifically, as shown in the figure, Figure 2 The first resistance, the second resistance and the third resistance are above the storage particle matrix, and the signal measuring point 7 and the ground measuring point 8 are on the periphery of the storage particle storage area 2 on the memory mainboard 1.
[0039] Specifically, as shown in the figure, Figure 2 When the storage particle to be tested is in the uppermost row of the storage particle matrix, the first resistance, the second resistance and the third resistance are above the storage particle matrix.
[0040] When the storage particle to be tested is in the lowermost row of the storage particle matrix, the first resistance, the second resistance and the third resistance are below the storage particle matrix.
[0041] When the storage particle to be tested is between the uppermost row and the lowermost row of the storage particle matrix, the first resistance, the second resistance and the third resistance are on the left side or the right side of the storage particle matrix, and the distance between the first resistance, the second resistance and the third resistance on the side and the storage particle to be tested is less than the distance between the first resistance, the second resistance and the third resistance on the other side and the storage particle to be tested.
[0042] In addition, in the embodiment, the first lead 3, the second lead 4, the third lead 5, the test lead 6, the first resistance, the second resistance and the third resistance are on the surface of the memory mainboard 1 or inside the memory mainboard 2.
[0043] According to the above description, relevant personnel can make various changes and modifications without deviating from the technical idea of the present application. The technical scope of the present application is not limited by the content of the specification, and must be determined by the scope of the claims.
Claims
1. A memory module, characterized in that, Including memory stick mainboard (1), be equipped with the storage particle storage area (2) on the memory stick mainboard (1), be equipped with storage particle matrix in the storage particle storage area (2), including at least one storage particle to be measured in the storage particle matrix; The to-be-tested DQ pin of the to-be-tested storage particle is electrically connected with the first resistor through the first lead wire (3), the to-be-tested C / A pin of the to-be-tested storage particle is electrically connected with the second resistor through the second lead wire (4), and the to-be-tested CLK pin of the to-be-tested storage particle is electrically connected with the third resistor through the third lead wire (5), and the first resistor, the second resistor and the third resistor are respectively electrically connected with the signal measuring point (7) through the test lead wire (6). The memory stick mainboard (1) is further provided with a ground measuring point (8).
2. The memory module of claim 1, wherein, The signal measuring point (7) is circular in shape, and the ground measuring point (8) is rectangular in shape.
3. The memory module of claim 1, wherein, When the number of to-be-tested DQ pins is greater than one, the length deviation of the first lead wire (3) electrically connected with all to-be-tested DQ pins is within 2 mils, and the impedance deviation of the first lead wire (3) electrically connected with all to-be-tested DQ pins is within ±10%; When the number of to-be-tested C / A pins is greater than one, the length deviation of the second lead wire (4) electrically connected with all to-be-tested C / A pins is within 2 mils, and the impedance deviation of the second lead wire (4) electrically connected with all to-be-tested C / A pins is within ±10%; When the number of to-be-tested CLK pins is greater than one, the length deviation of the third lead wire (5) electrically connected with all to-be-tested CLK pins is within 2 mils, and the impedance deviation of the third lead wire (5) electrically connected with all to-be-tested CLK pins is within ±10%.
4. The memory module of claim 1, wherein, The total lead length between the signal measuring point (7) and the to-be-tested pin is less than 5mm.
5. The memory module of claim 1, wherein, The distance between the first resistor, the second resistor and the third resistor and the outermost storage particle on the adjacent side of the storage particle matrix is between 0.5mm and 1mm.
6. The memory module of claim 5, wherein, The first resistor, the second resistor and the third resistor are on the storage particle storage area, and the signal measuring point and the ground measuring point are on the memory stick mainboard outside the periphery of the storage particle storage area.
7. A memory module as claimed in any one of claims 1 to 6, wherein, When the to-be-tested storage particle is in the uppermost row of the storage particle matrix, the first resistor, the second resistor and the third resistor are above the storage particle matrix.
8. A memory module as claimed in any one of claims 1 to 6, wherein, When the to-be-tested storage particle is in the lowermost row of the storage particle matrix, the first resistor, the second resistor and the third resistor are below the storage particle matrix.
9. A memory module as claimed in any one of claims 1 to 6, wherein, When the to-be-tested storage particle is between the uppermost row and the lowermost row of the storage particle matrix, the first resistor, the second resistor and the third resistor are on the left side or the right side of the storage particle matrix, and the distance between the first resistor, the second resistor and the third resistor and the to-be-tested storage particle on the side is less than the distance between the first resistor, the second resistor and the third resistor and the to-be-tested storage particle on the other side.
10. A memory module as claimed in any one of claims 1 to 6, wherein, The first lead wire (3), the second lead wire (4), the third lead wire (5), the test lead wire (6), the first resistor, the second resistor and the third resistor are on the surface of the memory stick mainboard (1) or inside the memory stick mainboard (1).