Semiconductor device and packaging structure

Abstract

The embodiment of the utility model provides a semiconductor device and a packaging structure. A package structure includes: a lower package including a first semiconductor die including a backside metal film on a backside of the first semiconductor die; an upper layer package attached to and electrically coupled to the lower layer package; and a thermally conductive underfill layer between the lower package and the upper package and contacting the backside metal film.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to semiconductor structures and packaging structures. BACKGROUND

[0002] Packaging structures that include stacked semiconductor packages can include complex thermal paths, leading to the potential for heat build-up. Heat dissipation in a packaging structure can present several problems. The most direct problem is the stacking effect itself. Stacking multiple semiconductor packages on top of one another can lead to heat build-up. Heat generated by active components in the first and second packages can accumulate, which can lead to higher temperature levels than in a single package configuration.

[0003] Another problem can be that the stacking of semiconductor packages can also introduce additional thermal resistance between the active components and the external environment. In order to escape, the generated heat can have to pass through multiple layers of material, such as substrates, interconnects, and solder joints, before it can dissipate. This increased thermal resistance can lead to higher operating temperatures and reduced overall thermal performance. SUMMARY

[0004] In some embodiments of the present utility model, a packaging structure includes a lower package including a first semiconductor die including a backside metal film on a backside of the first semiconductor die, an upper package attached to and electrically coupled to the lower package, and a thermally conductive underfill layer between the lower package and the upper package and contacting the backside metal film.

[0005] In some embodiments of the present utility model, a semiconductor device includes a lower package, an upper package, and a thermally conductive underfill layer. The lower package includes a frontside redistribution layer structure, a lower encapsulation layer on the frontside redistribution layer structure, a plurality of through-holes in the lower encapsulation layer, and a first semiconductor die adjacent to the plurality of through-holes in the lower encapsulation layer, wherein the first semiconductor die includes a backside metal film having an upper surface substantially coplanar with an upper surface of the lower encapsulation layer and an upper surface of the plurality of through-holes. The upper package is stacked on the lower package and includes a package substrate including a plurality of metal interconnect structures, an upper encapsulation layer on the package substrate, a dynamic random access memory die mounted on the package substrate in the upper encapsulation layer, and a plurality of bond wires in the upper encapsulation layer and electrically coupling the dynamic random access memory die to the plurality of metal interconnect structures. The thermally conductive underfill layer is between the lower package and the upper package and contacts the backside metal film. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the present application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is to be emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] FIG. 1A is a vertical cross-sectional view of a packaging structure according to various embodiments.

[0008] FIG. 1B is a plan view (top view) of an underlayer package in a packaging structure according to one or more embodiments.

[0009] FIG. 1C is a detailed cross-sectional view of a backside metal film and a thermally conductive underfill layer in a packaging structure according to one or more embodiments.

[0010] FIG. 2A shows an intermediate structure including a sintered metal layer according to one or more embodiments.

[0011] FIG. 2B shows an intermediate structure including applying a sintered metal layer to a surface of a semiconductor layer according to one or more embodiments.

[0012] FIG. 2C shows an intermediate structure of a sintered metal layer during curing in an oven according to one or more embodiments.

[0013] FIG. 2D shows a first semiconductor die including a backside metal film according to one or more embodiments.

[0014] FIG. 3A is a vertical cross-sectional view of an intermediate structure including a seed layer on an adhesive layer according to one or more embodiments.

[0015] FIG. 3B is a vertical cross-sectional view of an intermediate structure including a photoresist layer according to one or more embodiments.

[0016] FIG. 3C is a vertical cross-sectional view of an intermediate structure including a through-hole according to one or more embodiments.

[0017] FIG. 3D is a vertical cross-sectional view of an intermediate structure including a through-hole according to one or more embodiments.

[0018] FIG. 3E is a vertical cross-sectional view of an intermediate structure including a first semiconductor die according to one or more embodiments.

[0019] FIG. 3Fis a vertical cross-sectional view of an intermediate structure including an underlayer encapsulation layer according to one or more embodiments.

[0020] FIG. 3G is a vertical cross-sectional view of an intermediate structure including an underlayer encapsulation layer after performing a planarization process according to one or more embodiments.

[0021] FIG. 3H is a vertical cross-sectional view of an intermediate structure including a front-side RDL structure according to one or more embodiments.

[0022] FIG. 3I is a vertical cross-sectional view of an intermediate structure including a solder ball according to one or more embodiments.

[0023] FIG. 3J is a vertical cross-sectional view of an intermediate structure on a carrier tape according to one or more embodiments.

[0024] FIG. 3K is a vertical cross-sectional view of an intermediate structure including an upper encapsulation according to one or more embodiments.

[0025] FIG. 3L is a vertical cross-sectional view of an intermediate structure including a thermally conductive underfill layer according to one or more embodiments.

[0026] FIG. 3M is a vertical cross-sectional view of a finished package structure after dicing according to one or more embodiments.

[0027] FIG. 4 is a flowchart illustrating a method of forming a package structure according to one or more embodiments.

[0028] FIG. 5 is a vertical cross-sectional view of a package structure with a first alternative design according to one or more embodiments.

[0029] FIG. 6 is a vertical cross-sectional view of a package structure with a second alternative design according to one or more embodiments. DETAILED DESCRIPTION

[0030] The following disclosure provides many different embodiments, or examples, for implementing various aspects of the provided subject matter. The following description of specific examples is not intended to limit the application. For example, a first feature being formed over or on a second feature in the following description can include embodiments where the first feature and the second feature are formed in direct contact, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Additionally, the present application can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, to facilitate description, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for describing the relationship between one element or feature to other element(s) or feature(s) as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, and the device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly. Unless otherwise noted, each member having the same reference numeral is assumed to have the same material composition and to have a thickness in the same range of thicknesses.

[0032] In a related package structure including a lower package and an upper package, the lower package can include a semiconductor die including a die attach film. A layer of underfill can be formed between the upper package and the lower package.

[0033] The die attach film can have a low thermal conductivity (e.g., k < 5 W / m-k). As a result, the die attach film can not be effective in dissipating heat from the semiconductor die. Heat that is trapped or accumulated in the semiconductor die (e.g., a silicon die) can result in poor device performance, and even worse, electrical failure of the semiconductor die after reliability testing. In addition, the die attach film can include a protrusion that extends from the semiconductor die. This protrusion can result in high stress or a crack initiation point in the lower package.

[0034] At least one embodiment of the present application can include an innovative package structure with high thermal dissipation. Various embodiment package structures can include an upper package positioned on a lower package. Various embodiment package structures can provide a high thermal dissipation solution, especially in compact designs for mobile access point (AP), radio frequency (RF), and integrated circuit (IC) applications. This package structure can also provide a low cost method by directly attaching a high dielectric constant film on a semiconductor die instead of performing a dry etch to remove a die attach film on the semiconductor die, and then dispensing a high dielectric constant underfill material on the etched surface.

[0035] This packaging structure can replace the currently used die attach film with high thermal conductivity (e.g., k > 20 W / m-k) backside metal film. The backside metal film can provide a better heat dissipation path between the semiconductor die in the lower layer package and the upper layer package. The backside metal film can have good adhesion to semiconductor materials (e.g., silicon). In contrast to the die attach film, the backside metal film can not protrude from the sidewalls of the semiconductor die. The backside metal film can be formed on the semiconductor layer of the semiconductor die and have a width less than or equal to the width of the semiconductor layer. The backside metal film can have a thickness less than or equal to 20 pm.

[0036] The high thermal conductivity backside metal film can be achieved by using, for example, a sintered metal film. The sintered metal film can include metal particles (e.g., metal powder, metal flakes, etc.) sintered by thermal curing. The sintered metal particles (e.g., metal fillers) can include random shapes. The sintered metal particles can have a width and length (e.g., diameter) less than 100 pm. The sintered metal particles can include, for example, copper, silver, aluminum, or gold.

[0037] The packaging structure can also include a high thermal conductivity (e.g., k > 20 W / m-k) underfill (high dielectric constant UF) material layer positioned between the upper layer package and the lower layer package. Heat generated from the semiconductor die can be effectively dissipated through the path including the high dielectric constant backside metal film and the high dielectric constant underfill material layer. In the case where the upper layer package includes a dynamic random access memory (DRAM) die, the backside metal film can provide a better heat dissipation path between the semiconductor die and the DRAM die by connecting to the highly conductive underfill (high dielectric constant UF) material. Effective heat dissipation of the semiconductor die can be achieved through the high thermal conductivity backside metal film. Such heat dissipation can help provide improved performance for the packaging structure and help the packaging structure pass reliability tests.

[0038] FIG. 1A is a vertical cross-sectional view of a packaging structure 100 according to various embodiments. FIG. 1B is a plan view (top view) of a lower layer package 10 in a packaging structure 100 according to one or more embodiments. FIG. 1A is a cross-sectional view along line A-A’ in FIG. 1B . FIG. 1C is a detailed cross-sectional view of a backside metal film 129 and a thermally conductive underfill layer 50 in a packaging structure 100 according to one or more embodiments.

[0039] It should be noted that embodiments are not limited to any particular “package on package” configuration. That is, the thermal performance of other packaging structures other than the packaging structures described in the present utility model can be improved by using a backside metal film 129 and a thermally conductive underfill layer 50 as described herein.

[0040] It should also be noted that the terms "proximal" and "distal" are sometimes used to describe the means of the package structure 100. These terms are used with reference to the central portion of the package structure 100 in the z-direction (e.g., the portion including the first semiconductor die 120). Thus, for example, "proximal" of the redistribution layer may refer to the side of the redistribution layer closest to the central portion in the z-direction, and "distal" of the redistribution layer may refer to the side of the redistribution layer furthest from the central portion in the z-direction.

[0041] like FIG. 1A As shown, the package structure 100 may include a lower package 10 and an upper package 60 mounted on the lower package 10. The lower package 10 may include a first semiconductor die 120 containing a metal film 129. An underfill layer 50 may be formed between the lower package 10 and the upper package 60 and may contact the metal film 129. The back metal film 129 and the thermally conductive underfill layer 50 may form an effective heat dissipation path between the first semiconductor die 120 and the upper package 60.

[0042] In at least one embodiment, the front redistribution layer (RDL) structure 110 may include a plurality of alternately stacked polymer layers 114 and a plurality of redistribution layers 113. The present invention does not limit the number of polymer layers 114 and / or redistribution layers 113 in the front redistribution structure 110. For example, in FIG. 1A , FIG. 3H-3M , FIG. 5 and FIG. 6 In this diagram, the RDL is shown as having four polymer layers in which redistribution layers are formed. However, more or fewer polymer layers 114 and multiple redistribution layers 113 may be used.

[0043] In at least one embodiment, polymer layer 114 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In some embodiments, redistribution layer 113 may include a conductive material. The conductive material may include metals such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. Redistribution layer 113 may include metal interconnect structures (e.g., metal structures providing electrical connections between nodes in the front-side RDL structure 110).

[0044] The redistribution layer 113 can include a metal seed layer and a metal fill material on the metal seed layer. The metal seed layer can include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer can have a thickness in a range from 50 nm to 500 nm, and the copper seed layer can have a thickness in a range from 50 nm to 500 nm. The metal fill material for the redistribution layer 113 can include copper, nickel, or copper and nickel. Other suitable metal fill materials are also within the contemplated scope of the present disclosure. The thickness of the metal fill material deposited for each redistribution layer 113 can be in a range from 2 microns to 40 microns, for example, from 4 microns to 10 microns, although lesser or greater thicknesses can also be used.

[0045] In at least one embodiment, the redistribution layer 113 can include a plurality of traces (lines) and a plurality of vias connecting the plurality of traces to each other. The traces can be disposed on the polymer layer 114 and can extend in an x-direction (e.g., a first horizontal direction) and a y-direction (e.g., a second horizontal direction) on an upper surface of the polymer layer 114, respectively.

[0046] In some embodiments, the polymer layer 114 in the front-side RDL structure 110 can include a distal polymer layer 114d. The distal polymer layer 114d can include an under bump metal (UBM) layer 115. The UBM layer 115 can include a metal, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. A portion of the UBM layer 115 can be disposed on an underside of the distal polymer layer 114d and serve as a connection pad. Solder balls 116 can be disposed on the UBM layer 115 and used to mount the package structure 100 to a substrate, such as a printed circuit board (PCB). The solder balls 116 can include a standard solder material (e.g., SAC304 or SAC405). The solder material can include a lead-free solder material. The solder material can include tin and one or more other elements, such as silver, indium, antimony, bismuth, zinc, etc. Other suitable solder materials are within the contemplated scope of the present disclosure. The UBM layer 115 can optionally include micro-bumps or metal pillars (e.g., copper pillars).

[0047] The polymer layer 114 in the front-side RDL structure 110 can also include a proximal polymer layer 114p. The proximal polymer layer 114p can include one or more vias 118 that can be used as RDL bond pads for connecting the first semiconductor die 120 to the front-side RDL structure 110. The proximal polymer layer 114p can also include one or more vias 119 that can be used as front-side bond pads for connecting one or more through vias (TVs) 145 to the front-side RDL structure 110. The vias 119 can have a size (e.g., diameter, width in the x-direction, etc.) that is larger than a size of the vias 118. The vias 118 and the vias 119 can be formed simultaneously with the redistribution layer 113 and can include a metal such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals.

[0048] The first semiconductor die 120 can be attached (e.g., mounted) on the proximal polymer layer 114p of the front-side RDL structure 110. The first semiconductor die 120 can include, for example, a semiconductor chip or a small chip for high performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications. In at least one embodiment, the first semiconductor die 120 can include a logic chip (e.g., a mobile application processor, a microcontroller, etc.) or a memory chip (e.g., a dynamic random access memory (DRAM) chip, a wide I / O die, an M-RAM chip, an R-RAM chip, a NAND chip, a static random access memory (SRAM), etc.). In at least one embodiment, the first semiconductor die 120 can include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a field programmable gate array (FPGA) chip, a network chip, an application specific integrated circuit (ASIC) chip, an artificial intelligence / deep neural network (AI / DNN) accelerator chip, etc., a co-processor, an accelerator, an on-chip memory buffer, a memory cube (e.g., HBM, HMC, etc.), a high data rate transceiver chip, an I / O interface die, an IPD die (e.g., an integrated passive device), a power management chip (e.g., a power management integrated circuit (PMIC) chip), a radio frequency (RF) chip, a sensor chip, a microelectromechanical system (MEMS) chip, a signal processing chip (e.g., a digital signal processing chip (DSP) chip), a front-end chip (e.g., an analog front end (AFE) chip), a monolithic 3D heterogeneous small chip stack chip, etc.

[0049] The first semiconductor die 120 can include, for example, an active region 122 on a front side of the first semiconductor die 120 and a semiconductor layer 126 (e.g., a bulk silicon region) on the active region 122. The active region 122 can include a front end of line (FEOL) region that includes electronic circuitry including various electronic devices (e.g., transistors, resistors, etc.). In particular, the FEOL region can include one or more logic circuits that include logic devices (e.g., logic gates) and / or one or more memory circuits that include memory devices (e.g., volatile memory (VM) devices and / or non-volatile memory (NVM) devices).

[0050] The active region 122 can also include a back end of line (BEOL) region on the FEOL region. The BEOL region can include an interlayer dielectric having a plurality of dielectric layers. The dielectric layers can include, for example, Si02, a dielectric polymer, or other suitable dielectric material. The interlayer dielectric can include one or more metal interconnect structures formed therein. The metal interconnect structures can include metal traces and metal vias formed in the dielectric layers and provide electrical connections to the electronic circuitry in the FEOL region.

[0051] The first semiconductor die 120 can also include one or more semiconductor die contact pads 123 on a surface of the active region 122. The semiconductor die contact pads 123 can include, for example, one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the contemplated scope of the present disclosure.

[0052] The first semiconductor die 120 can also include a semiconductor die passivation layer 125 on a surface of the semiconductor die active region 122. In particular, the semiconductor die passivation layer 125 can at least partially cover the semiconductor die contact pads 123. The semiconductor die passivation layer 125 can include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an ultra-low-k dielectric material such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials. Surfaces of the semiconductor die contact pads 123 can be exposed through openings in the passivation layer 125.

[0053] The package structure 100 can also include a dielectric layer 121 on the semiconductor die passivation layer 125. The dielectric layer 121 can include a dielectric polymer, silicon oxide, or other suitable dielectric material. Semiconductor die bond pads 127 can be formed in the dielectric layer 121 and contact the exposed surfaces of the semiconductor die contact pads 123 through openings in the passivation layer 125. The semiconductor die bond pads 127 can have one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the contemplated scope of the present disclosure. The first semiconductor die 120 can be connected to the front-side RDL structure 110 by connecting the semiconductor die bond pads 127 to the vias 118 (e.g., RDL bond pads) in the proximal polymer layer 114p.

[0054] The first semiconductor die 120 can also include a backside metal film 129 positioned at the backside of the first semiconductor die 120. The backside metal film 129 can be formed on a surface of the semiconductor layer 126. The backside metal film 129 can have good adhesion to the semiconductor material (e.g., silicon) in the semiconductor layer 126. In contrast to a die attach film, the backside metal film 129 can not protrude from the sidewalls of the semiconductor layer 126.

[0055] The backside metal film 129 can include a high thermal conductivity (e.g., k > 20 W / m-k) metal film. This can allow the backside metal film 129 to efficiently dissipate heat generated by the first semiconductor die 120. The backside metal film 129 can be formed from one or more layers. The backside metal film 129 can have high mechanical strength and can be ductile and malleable such that it can withstand bending and stretching without a significant loss of integrity. The backside metal film 129 can also be chemically stable and substantially resistant to corrosion. The backside metal film 129 can also include a rough upper surface with a high surface area, which can enhance the ability of the backside metal film 129 to dissipate heat.

[0056] The backside metal film 129 (e.g., high thermal conductivity backside metal film) can include, for example, a sintered metal film. The sintered metal film can include sintered metal particles (e.g., metal powder, metal flakes, etc.). The sintered metal particles can include, for example, copper, silver, aluminum, or gold. Other suitable metals can be used for the sintered metal particles.

[0057] A sintered metal film can be formed by compacting metal particles into a solid metal film with pressure and / or heat without melting the metal particles to a liquidus point. The pressure and / or heat can fuse the metal particles together to form a solid metal film. The metal particles can have a controlled particle size and distribution. This can help ensure uniformity and consistency of the sintered metal film. The sintering process can enhance the strength, electrical conductivity, and thermal conductivity of the metal particles. The high temperature of the sintering process can also cause grain growth in the metal powder particles, which can change the microstructure and mechanical properties of the sintered metal film. The sintering temperature, duration, and initial particle size of the metal powder can be controlled to achieve a particular pore size and distribution within the sintered metal film.

[0058] In at least one embodiment, the backside metal film 129 can include a high dielectric constant thermally conductive die attach film with a metal filler. The die attach film (also referred to as a die attach adhesive or a chip attach material) can include, for example, one or more layers of an epoxy or a polyimide. The die attach film can be electrically insulating, thermally conductive, and have good adhesion properties. The die attach film can also be thermally and chemically stable. The metal filler can include, for example, metal particles including one or more of stainless steel, nickel, copper, bronze, titanium, tungsten, etc. Other suitable materials for the backside metal film 129 are also within the contemplated scope of the present disclosure.

[0059] As FIG. 1A As further shown, one or more through-vias (TVs) 145 can be located on the frontside RDL structure 110. The through-vias 145 can be connected to the vias 119 (e.g., RDL bond pads) in the proximal polymer layer 114p. The through-vias 145 can have a columnar or cylindrical shape (e.g., a cylindrical shape). The through-vias 145 can have a diameter (e.g., a width) in the x-direction that is greater than a width of the vias 119. The through-vias 145 can include a seed layer 212 at one end of the through-vias 145. The seed layer 212 can include, for example, copper or one or more other suitable metals. The height of the seed layer 212 in the z-direction can be substantially the same as the height of the backside metal film 129 of the first semiconductor die 120. That is, the surface of the seed layer 212 can be substantially coplanar with the surface of the backside metal film 129. The through-vias 145 can have one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials for the through-vias 145 are within the contemplated scope of the present disclosure.

[0060] The package structure 100 can further include an underfill layer 140 on the front side RDL structure 110. The underfill layer 140 can laterally (e.g., in the x and y directions) encapsulate the first semiconductor die 120 and the through-hole 145. In at least one embodiment, the dielectric layer 121 can be omitted, in which case the underfill layer 140 can also be on and around the semiconductor die bond pads 127 between the first semiconductor die 120 and the front side RDL structure 110. A surface of the underfill layer 140 can be substantially coplanar with a surface of the seed layer 212 and a surface of the back side metal film 129. In some embodiments, the underfill layer 140 can include a mold compound, a mold underfill, a resin (e.g., an epoxy resin), or a combination thereof, or other suitable encapsulant material.

[0061] As shown further, FIG. 1A As shown further, the upper package 60 can include side walls 60a that are substantially aligned with the side walls 10a of the lower package 10. The upper package 60 can include a package substrate 605. The package substrate 605 can include a core substrate or a core less substrate. The package substrate 605 can include one or more dielectric layers stacked along a thickness direction of the package substrate 605. In at least one embodiment, the package substrate 605 can include a build-up film substrate, such as an ABF build-up film substrate. In at least one embodiment, the package substrate includes one or more layers of epoxy resin, such as BT epoxy resin, and a dielectric polymer material, such as PI, BCB, or PBO. Other suitable dielectric materials for the package substrate 605 are within the contemplated scope of the present disclosure.

[0062] The package substrate 605 can include bottom contact pads 617 on a bottom surface of the package substrate 605. The package substrate can include upper contact pads 619 on an upper surface of the package substrate 605. The upper contact pads 619 can be electrically connected to the bottom contact pads 617 through one or more interconnect structures 618 (e.g., metal traces and metal vias) in the package substrate 605.

[0063] The package structure 100 can further include a plurality of solder balls 616 for attaching the upper package 60 to the lower package 10. The solder balls 616 can be on the seed layer 212 in the lower package 10. The bottom contact pads 618 in the upper package can be in contact with the solder balls 616 on the seed layer 212. The upper package 60 can be electrically coupled to the lower package 10 (e.g., to the front side RDL structure 110) through the solder balls 616.

[0064] The upper package 60 may further include a first upper semiconductor die 620 (e.g., a second semiconductor die) mounted on the package substrate 605 (e.g., via hybrid bonding, die attachment film, etc.). The center point C of the first upper semiconductor die 620 is... 620 (In the xy plane) the center point C of the first semiconductor die 120 in the lower package 10 can be located in the z direction. 120 (In the xy plane) substantially aligned. The first upper semiconductor die 620 may include an active region 622 connected to the upper contact pad 619 via one or more metal lines 621. The upper package 60 may also include a second upper semiconductor die 630 (e.g., a third semiconductor die) mounted on the first upper semiconductor die 620 (e.g., via hybrid bonding, die-attachment film, etc.).

[0065] The width of the second upper semiconductor die 630 in the x-direction may be smaller than the width of the first upper semiconductor die 620 in the x-direction. The second upper semiconductor die 630 may include an active region 632 connected to the upper contact pad 619 via one or more metal lines 623. Each of the first upper semiconductor die 620 and the second upper semiconductor die 630 may be similar in design and / or function to the first semiconductor die 120 in the lower package 10 as described above. In at least one embodiment, each of the first upper semiconductor die 620 and the second upper semiconductor die 630 may include a dynamic random access memory (DRAM) chip.

[0066] The upper package 60 may also include an upper encapsulation layer 640 similar to the lower encapsulation layer 140 in the package structure 100. The upper encapsulation layer 640 may be formed on the package substrate 605 and may substantially encapsulate the first upper semiconductor die 620, the second upper semiconductor die 630, the metal line 621, and the metal line 623.

[0067] like FIG. 1A As further shown, the package structure 100 may also include a thermally conductive underfill layer 50 located between the upper package 60 and the lower package 10. The sidewalls 50a of the thermally conductive underfill layer 50 may be substantially aligned with the sidewalls 60a of the upper package 60 and the sidewalls 10a of the lower package 10. The thermally conductive underfill layer 50 may be formed around the solder balls 616 and substantially fills the gap (e.g., space) between the bottom surface of the package substrate 605 in the upper package 60 and the upper surfaces of the lower encapsulation layer 140, the seed layer 212, and the back metal film 129 in the lower package 10. The thermally conductive underfill layer 50 can enhance heat dissipation and thermal performance by improving the thermal conductivity (e.g., enhancing heat transfer) between the first semiconductor die 120 and the package substrate 605.

[0068] The thermally conductive underfill layer 50 can help secure the upper package 60 to the lower package 10. The thermally conductive underfill layer 50 can have a low viscosity (e.g., less than about 5000 cP at 10 rpm) and can be formed of an epoxy-based polymeric material. In at least one embodiment, the thermally conductive underfill layer 50 can include a capillary underfill that includes a mixture of an epoxy resin and silica. In at least one embodiment, the thermally conductive underfill layer 50 can include a low viscosity suspension of silica in a prepolymer.

[0069] The thermally conductive underfill layer 50 can have a thermal conductivity greater than 20 W / m-K. The thermally conductive underfill layer 50 can include, for example, a filled polymeric underfill adhesive. The filled polymeric underfill can include a thermally conductive filler, such as ceramic particles, metal particles, or carbon fibers suspended within a polymeric material (e.g., a polymeric matrix). It should be noted that the underfill material can be modified to a high dielectric constant underfill material by adding a higher percentage of filler (e.g., metal filler) or changing the high dielectric constant thermally conductive filler in the underfill material.

[0070] Referring to FIG. 1B , the first semiconductor die 120 can be positioned in a central region of the lower package 10. An outer edge of the backside metal film 129 can be substantially aligned with an outer edge of the semiconductor layer 126 around an entire periphery of the first semiconductor die 120. In at least one embodiment, a width of the backside metal film 129 in the x-direction can be less than or equal to a width of the semiconductor layer 126 in the x-direction, and a length in the y-direction can be less than or equal to a length of the semiconductor layer 126 in the x-direction. The semiconductor layer 126 is in the y-direction.

[0071] The lower encapsulation layer 140 can contact the backside metal film 129 and the semiconductor layer 126 around an entire periphery of the first semiconductor die 120. The through-holes 145 can be formed in the lower encapsulation layer 140 around an entire periphery of the first semiconductor die 120. The through-holes 145 can be formed in two or more rows extending along the x-direction or two or more columns extending along the y-direction. The spacing between the through-holes 145 can be substantially uniform around the entire periphery of the first semiconductor die 120.

[0072] A minimum distance Dm between the through-holes 145 and the backside metal film 129 (e.g., the first semiconductor die 120) can be substantially uniform around an entire periphery of the first semiconductor die 120. The minimum distance Dm can be 100 pm or greater.

[0073] Referring to FIG. 1C , the backside metal film 129 can have a thickness T 129In at least one embodiment, the back-side metal film 129 may have a thickness T less than or equal to 20 μm. 129 In at least one embodiment, the thickness T of the back-side metal film 129 is... 129 The thickness of the combination of the active region 122, the semiconductor layer 126, and the back-side metal film 129 can be at least 10%. In at least one embodiment, the thickness T of the back-side metal film 129 is... 129 The thickness T of the thermally conductive bottom filler layer can be 50. 50 At least 30%.

[0074] The back-side metal film 129 may include a sintered metal film containing a plurality of sintered metal particles 129p. The sintered metal film may also include pores 128 (e.g., voids) between the sintered metal particles 129p. The sintered metal particles 129p (e.g., metal fillers) may include random shapes, such as ellipsoids, quasi-spheres, cuboids, etc. Other suitable shapes of the sintered metal particles 129p are within the scope of this invention.

[0075] The sintered metal particles 129p (e.g., metal fillers) may include different sizes and different orientations (e.g., longitudinal direction) in the back-side metal film 129. The sintered metal particles 129p may have dimensions (e.g., length, width, diameter) of less than 100 μm. In at least one embodiment, the sintered metal particles 120p may have a width W of less than 100 μm in the x-direction and a height H of less than 100 μm in the y-direction.

[0076] like FIG. 1C As shown, the sidewall 129a of the back-side metal film 129 may be substantially aligned with the sidewall 126a of the semiconductor layer 126. That is, the sidewall 129a of the back-side metal film 129 may not protrude from the sidewall 126a of the semiconductor layer 126. In at least one embodiment, the width of the back-side metal film 129 may be slightly smaller than the width of the semiconductor layer 126. In this embodiment, the sidewall 129a of the back-side metal film 129 may not be aligned with the sidewall 126a of the semiconductor layer 126, but may be exactly inside the sidewall 126a of the semiconductor layer 126 in both the x and y directions. Furthermore, the distance between the sidewall 129a of the back-side metal film 129 and the sidewall 126a of the semiconductor layer 126 may be less than 10 μm.

[0077] FIG. 2A to FIG. 2D Various method steps for forming a first semiconductor die 120 according to one or more embodiments are illustrated. Specifically, FIG. 2A A sintered metal layer 129L according to one or more embodiments is shown. The sintered metal layer 129L can be manufactured by sintering or fusing metal particles (e.g., metal powder, metal sheet, etc.) together using heat (e.g., or heat and pressure) to form a continuous and conductive metal layer.

[0078] In at least one embodiment, the method of forming sintered metal layer 129L can include cleaning the surface of the substrate on which sintered metal layer 129L will be formed. Cleaning the surface of the substrate can mitigate contamination of sintered metal layer 129L. Metal particles can then be deposited onto the surface of the substrate to create a thin layer of metal particles. The metal particles can be deposited by, for example, screen printing, injection printing, spray coating, etc. In embodiments that use a liquid carrier during deposition of the metal particles, the substrate can be heated or allowed to dry to remove the carrier and leave the metal particles on the surface.

[0079] Sintered metal layer 129L can then be sintered by heating the substrate with the deposited metal particles to a temperature below the melting point of the metal but high enough to cause the particles to fuse together. Pressure can be selectively applied during the sintering process to promote particle bonding between the metal particles. After sintering, the substrate can be gradually cooled so that the molten metal particles solidify and form sintered metal layer 129L (e.g., a viscous metal film). Sintered metal layer 129L can then be tested to ensure that it has a thermal conductivity greater than 20 W / m-K.

[0080] At this point, sintered metal layer 129L can undergo additional processes to enhance the performance of sintered metal layer 129L, such as planarization or surface coating. In particular, sintered metal layer 129 can undergo a planarization process to provide a uniform thickness less than or equal to 20 pm. Sintered metal layer 129 can also undergo a roughening process (e.g., etching, grinding, etc.) to increase its surface area and improve its heat transfer efficiency.

[0081] Sintered metal layer 129L can also be treated by one or more processes to enhance the thermal conductivity of sintered metal layer 129L. For example, sintered metal layer 129L can be annealed to reduce defects, dislocations, and grain boundaries within the film, thereby improving its crystal structure and thermal conductivity. The surface of sintered metal layer 129L can also be coated with a thin layer of a highly thermally conductive material (e.g., boron nitride) to enhance the thermal conductivity of sintered metal layer 129L.

[0082] FIG. 2B A sintered metal layer 129L is shown being applied to the surface of semiconductor layer 126 according to one or more embodiments. As shown, an intermediate structure can be placed on a heating platform 200. The heating stage can be heated to a temperature in the range of 50 °C to 100 °C. Sintered metal layer 129L can then be applied to the upper surface of semiconductor layer 126 by a film lamination process using a roller. FIG. 2B

[0083] FIG. 2C ​Solidification of the sintered metal layer 129L in the oven 250 is shown in accordance with one or more embodiments. In at least one embodiment, the sintered metal layer 129L (which can be referred to as a backside metal film 129 when attached to the semiconductor layer) can be solidified in the oven 250 at a temperature in the range of 120 °C to 180 °C for a period of time. The duration of time is between 1.5 hours and 2.5 hours.

[0084] FIG. 2D A first semiconductor die 120 including a backside metal film 129 in accordance with one or more embodiments is shown. After the sintered metal film 129L has been sufficiently solidified in the oven, the semiconductor die 120 (including the semiconductor layer 126, the active region 122, and the backside metal film 129) can be removed from the oven and allowed to cool at room temperature. At this point, the backside metal film 129 can be firmly attached (e.g., bonded, fused, etc.) to the surface of the semiconductor layer 126, and the formation of the first semiconductor die 120 can be complete.

[0085] FIG. 3A to FIG. 3M is a view of various intermediate structures in a method of forming a package structure 100 in accordance with one or more embodiments. Specifically, FIG. 3A is a vertical cross-sectional view of an intermediate structure including a seed layer 212 on a bonding agent layer 210 in accordance with one or more embodiments.

[0086] As shown in FIG. 3A , a bonding agent layer 210 can be formed on an upper surface of a carrier substrate 5. The carrier substrate 5 can include a semiconductor wafer (e.g., a circular wafer or a rectangular wafer) or a glass substrate. The lateral dimension of the carrier substrate 5 (e.g., the diameter of a circular wafer or the side length of a rectangular wafer) can be in the range from 100 mm to 500 mm, such as from 200 mm to 400 mm, although smaller and larger lateral dimensions can also be used. The carrier substrate 5 can be transparent or opaque. The thickness of the carrier substrate 5 can be sufficient to provide mechanical support for the package structure 100. For example, the thickness of the carrier substrate 5 can be in the range from 60 microns to 1 millimeter, although smaller and larger thicknesses can also be used.

[0087] The adhesive layer 210 can include a light-to-heat conversion (LTHC) layer or can include a heat-decomposable adhesive material. In at least one embodiment, the adhesive layer 210 can cover the entire carrier substrate 5. The LTHC layer can include a solvent-based coating applied using a spin-on process. The LTHC layer can be formed as a layer that converts ultraviolet light into heat such that the LTHC layer loses adhesion. Alternatively, the adhesive layer can include a heat-decomposable adhesive material. For example, the adhesive layer can include an acrylic pressure-sensitive adhesive that decomposes at elevated temperatures. The peel temperature of the heat-decomposable adhesive material can be in the range of 150 °C to 400 °C. Other suitable heat-decomposable adhesive materials that decompose at other temperatures are also within the contemplated scope of the present disclosure.

[0088] A seed layer 212 (e.g., a metal seed layer, a copper seed layer, etc.) can then be formed on the adhesive layer 210. In at least one embodiment, the seed layer 212 can cover the entire adhesive layer 210. For example, the seed layer 212 can be formed by depositing the seed layer 212 in a deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), spin-on, lamination, or other suitable deposition techniques. The seed layer 212 can include, for example, one or more layers and can include one or more metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the contemplated scope of the present disclosure.

[0089] FIG. 3B is a vertical cross-sectional view of an intermediate structure including a photoresist layer 214 according to one or more embodiments. The photoresist layer 214 can be formed to have a thickness that is greater than the thickness of the first semiconductor die 120. The photoresist layer 214 can then be patterned to form openings O 214 through the photoresist layer 214. The bottoms of the openings O 214 may be comprised of the upper surface of the seed layer 212. For example, a mask layer (not shown) can be formed on the upper surface of the photoresist layer 214, and the layer can be patterned to have a pattern corresponding to the desired pattern in the photoresist layer 214. The photoresist layer 214 can then be patterned by an etching process (e.g., wet etching, dry etching, etc.) through the openings in the mask layer to form the openings O 214 . The etching process can be performed until the upper surface of the seed layer 212 is exposed. The mask layer can then be removed to expose the upper surface of the photoresist layer 214.

[0090] FIG. 3CThis is a vertical cross-sectional view of an intermediate structure including a through hole 145 according to one or more embodiments. FIG. 3C As shown, the through-hole 145 can be formed as an opening O in the photoresist layer 214. 214 In the middle. It can be used by opening O. 214 The seed layer 212 exposed at the bottom is at the opening O 214 Electroplated metallic filler material (e.g., copper) is used to form the through-hole 145. The metallic material used for electroplating may include, for example, one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this invention.

[0091] Fill the opening O with metal filler material. 214 Subsequently, the upper surfaces of the metal filler material and the photoresist layer 214 can be planarized by, for example, chemical mechanical polishing (CMP) or other suitable planarization techniques. After planarization, the upper surface of the metal filler material (e.g., the upper surface of the through-hole 145) can be substantially coplanar with the upper surface of the photoresist layer 214.

[0092] FIG. 3D This is a vertical cross-sectional view of an intermediate structure including a through-hole 145 according to one or more embodiments. After the upper surface of the metal filler material constituting the through-hole 145 and the photoresist layer 214 is planarized, the photoresist layer 214 can then be removed by, for example, etching (e.g., wet etching, dry etching, etc.). The seed layer 212 (e.g., under-bump metallization (UBM) layer) can also be etched (e.g., wet etching, dry etching, etc.) to expose the upper surface of the adhesive layer 210 between the through-holes 145.

[0093] The seed layer 212 can be etched simultaneously with the photoresist layer 214 in the same etching step, or etched in a separate step after etching the photoresist layer 214. For example... FIG. 3D As shown, after etching the seed layer 212, portions of the seed layer 212 can remain unetched below the through hole 145.

[0094] FIG. 3Eis a vertical cross-sectional view of an intermediate structure including a first semiconductor die 120 according to one or more embodiments. The first semiconductor die 120 (including a backside metal film 129) can be flipped over so that the backside metal film 129 faces the adhesive layer 210 and then placed on the adhesive layer 210. The entire upper surface of the backside metal film 129 can be in contact with the upper surface of the adhesive layer 210. In at least one embodiment, the first semiconductor die 120 can be placed on the upper surface of the adhesive layer 210 by a pick-and-place (PnP) process (e.g., a robotic PnP process). The first semiconductor die 120 can be placed on the adhesive layer 210 so that a minimum distance Dm (e.g., 100 pm or more) is maintained between the backside metal film 129 and an adjacent through-hole 145 surrounding the periphery of the first semiconductor die 120. Pressure (indicated by the directional arrow in FIG. 3E ) can then be applied to the first semiconductor die 120 to press the backside metal film 129 onto the surface of the adhesive layer 210. The intermediate structure can then be heated (e.g., in an oven) to firmly secure the backside metal film 129 to the surface of the adhesive layer 210. As shown in FIG. 3E , the height of the through-hole 145 can be greater than the height of the first semiconductor die 120.

[0095] FIG. 3F is a vertical cross-sectional view of an intermediate structure including an underlayer encapsulation layer 140 according to one or more embodiments. The underlayer encapsulation layer 140 can be formed by a series of over-molding and planarization processes. In particular, the underlayer encapsulation layer 140 (e.g., an epoxy molding compound (EMC)) can be formed over the adhesive layer 210 to fill the gap between the first semiconductor die 120 and the through-hole 145 and encapsulate the first semiconductor die 120 and the through-hole 145. The underlayer encapsulation layer 140 can be formed to have a height that is greater than the height of the through-hole 145. The underlayer encapsulation layer 140 can be formed by a deposition process (e.g., such as CVD, PECVD, PVD, spin coating, lamination, or other suitable deposition techniques).

[0096] FIG. 3G is a vertical cross-sectional view of an intermediate structure including an underlayer encapsulation layer 140 after performing a planarization process according to one or more embodiments. As shown in FIG. 3GAs shown, a planarization process can be performed on the surface 140a of the underlying encapsulation layer 140 until the upper surface 145a of the through-hole 145 and the upper surface 127a of the semiconductor die bond pad 127 are exposed. That is, the planarization process can be performed until the surface 140a of the underlying encapsulation layer 140 is substantially coplanar with the upper surface 145a of the through-hole 145 and the upper surface 127a of the semiconductor die bond pad 127. The planarization process can include, for example, a mechanical polishing process and / or a chemical mechanical polishing (CMP) process.

[0097] FIG. 3H is a vertical cross-sectional view of an intermediate structure including a front-side RDL structure 110 according to one or more embodiments. Polymer layers 114 and redistribution layers 113 can be alternately formed in a series of process steps. In particular, a proximal polymer layer 114p can be formed on the underlying encapsulation layer 140. The proximal polymer layer 114p can be formed by, for example, a deposition process such as CVD, PECVD, PVD, spin coating, lamination, or other suitable deposition technique.

[0098] An opening can be formed in the proximal polymer layer 114p (e.g., by etching in a photolithography process). A redistribution layer 113 can then be formed (e.g., by an electroplating process) in and on the proximal polymer layer 114p in the opening. In this way, a via 118 (e.g., an RDL bond pad) can be formed to contact the semiconductor die bond pad 127, and a via 119 (e.g., a front-side bond pad) can be formed to contact the through-hole 145. The remaining polymer layers 114 and redistribution layers 113 of the front-side RDL structure 110 can then be alternately formed in a similar manner. An opening can then be formed (e.g., by a photolithography process) in a distal polymer layer 114d, and a UBM layer 115 can be formed (e.g., by an electroplating process) in and on the surface of the opening of the distal polymer layer 114d.

[0099] FIG. 3I is a vertical cross-sectional view of an intermediate structure including solder balls 116 according to one or more embodiments. As shown, the solder balls 116 can be formed on the UBM layer 115. For example, the solder balls 116 can be formed by a suitable process such as reflow, evaporation, drop ball, screen printing, or electroplating. FIG. 3I

[0100] FIG. 3J ​is a vertical cross-sectional view of an intermediate structure on a carrier tape 6 according to one or more embodiments. After the solder balls 116 are formed on the UBM layer 115, the intermediate structure can be inverted and placed on the carrier tape 6. The carrier tape 6 can include a thin, flexible strip made of plastic. The carrier tape 6 can optionally include a pattern of pockets or cavities that precisely match the arrangement of the solder balls 116 on the intermediate structure. The intermediate structure can be positioned so that each solder ball 116 sits within its corresponding pocket. A cover tape (not shown) can then be applied to the carrier tape 6, sealing the solder balls 116 within their respective pockets. The cover tape can be made of clear plastic and is firmly bonded to the carrier tape 6, forming a protective barrier.

[0101] The intermediate structure can then be peeled off from the carrier substrate 5. The intermediate structure can be debonded from the carrier substrate 5 by, for example, decomposing the adhesive layer 210 that adheres the carrier substrate 5 to the surface of the intermediate structure, for example, by using heat, ultraviolet (UV) light, etc. A LTHC cleaning step (e.g., post-laser drill clean) or other suitable cleaning process can then be performed in order to clean the surface of the intermediate structure. The cleaning process can facilitate the removal of the adhesive layer 210 from the surface of the intermediate structure. A pre-solder layer (not shown) can also be selectively formed on the exposed surface of the seed layer 212. The pre-solder layer can be formed by, for example, a suitable process such as reflow, evaporation, drop ball, screen printing, or electroplating. Such a process provides significant time and cost savings compared to related methods that use a die attach film, as such a die attach film can be removed using a dry etching process.

[0102] FIG. 3K is a vertical cross-sectional view of an intermediate structure including an upper layer package 60 according to one or more embodiments. The upper layer package 60 can be fabricated by a process of mounting a first upper layer semiconductor die 620 (e.g., a second semiconductor die) on a package substrate 605. The first upper layer semiconductor die 620 can be positioned over the package substrate 605 using a pick-and-place machine for subsequent alignment with the first semiconductor die 120. The first upper layer semiconductor die 620 can be attached to the package substrate 605 by a die attach film, by hybrid bonding, or by other suitable bonding methods.

[0103] A second upper semiconductor die 630 (e.g., a third semiconductor die) can then be mounted on the first upper semiconductor die 620. A pick-and-place machine can also be used to position the second upper semiconductor die 630 over the first upper semiconductor die 620 and align the second upper semiconductor die 630 with the first upper semiconductor die 620. The second upper semiconductor die 630 can be attached to the first upper semiconductor die 620 by a die attach film, by hybrid bonding, or by other suitable bonding methods. The ends of the metal wires 621 and 623 can then be attached (e.g., by soldering) to the active region 622 of the first upper semiconductor die 620 and the active region 632 of the second upper semiconductor die 630, respectively. The other ends of the metal wires 621 and 623 can then be attached (e.g., by soldering) to the upper contact pad 619. An upper encapsulation layer 640 can then be formed on the package substrate 605 in a manner similar to the formation of the lower encapsulation layer 140 described above. Solder balls 616 can then be formed on the bottom contact pad 617 in a manner similar to the formation of the solder balls 116.

[0104] After the upper package 60 is formed, the upper package 60 can be mounted on the lower package 10. A pick-and-place machine can be used to position the upper package 60 over the lower package 10 so that the solder balls 616 are aligned with the portions of the seed layer 212 on the through holes 145. The pick-and-place machine can then lower the upper package 60 onto the lower package 10, and heat and / or pressure can be applied to bond the upper package 60 to the lower package 10.

[0105] FIG. 3L is a vertical cross-sectional view of an intermediate structure including a thermally conductive underfill layer 50 according to one or more embodiments. The thermally conductive underfill layer 50 (e.g., an epoxy-based polymer material) can be dispensed (e.g., injected) onto the upper surface of the lower package 10, under the package substrate 605, and around the solder balls 616. As shown, the thermally conductive underfill layer 50 can be formed individually under each of the upper packages 60. Alternatively, the thermally conductive underfill layer 50 can be formed continuously under the entire upper package 60. The thermally conductive underfill layer 50 can then be cured, for example, in a box oven at a temperature in the range of 120 °C to 180 °C for a duration in the range of 60 minutes to 120 minutes to cause the thermally conductive underfill layer 50 to provide sufficient rigidity and mechanical strength. FIG. 3L

[0106] FIG. 3M is a vertical cross-sectional view of the completed package structure 100 after singulation according to one or more embodiments. As shown, FIG. 3M after the thermally conductive underfill layer 50 has been cured, FIG. 3L ​The intermediate structure of FIG. 1 1 can be separated into individual units (e.g., separated into a plurality of package structures 100). In at least one embodiment, the individual package structures 100 can be separated from the adjoining package structures 100 by using a dicing saw. The package structures 100 can be diced along the dicing lines between adjacent package structures 100 using the dicing saw.

[0107] FIG. 4 is a flowchart illustrating a method of forming a package structure 100 according to one or more embodiments. Step 410 of the method can include forming a first semiconductor die including a backside metal film on a backside of the first semiconductor die. Step 420 can include forming an underlayer package including the first semiconductor die. Embodiments of step 430 can include attaching an overlayer package to the underlayer package. Embodiments of step 440 can include forming a thermally conductive underfill layer between the underlayer package and the overlayer package such that the thermally conductive underfill layer contacts the backside metal film in the underlayer package.

[0108] FIG. 5 is a vertical cross-sectional view of a package structure 100 having a first alternative design according to one or more embodiments. The first alternative design of the package structure 100 can be substantially similar to the original design of FIG. 1 1. FIG. 1A However, in the first alternative design, the overlayer package 60 can be replaced with an overlayer semiconductor die 800. The overlayer semiconductor die 800 can be substantially identical to the first semiconductor die 120. In at least one embodiment, the overlayer semiconductor die 800 can include a memory chip such as a DRAM die.

[0109] In the first alternative design, the overlayer semiconductor die 800 can be flip-chip mounted on the underlayer package 10. The overlayer semiconductor die 800 can include an active region 822 on a front side of the overlayer semiconductor die 800. The overlayer semiconductor die 800 can also include a semiconductor layer 826 (e.g., a bulk silicon region) on the active region 822. The front side of the overlayer semiconductor die 800 can also include a passivation layer 850 and a plurality of bond pads 855 in the passivation layer 850. The overlayer semiconductor die 800 can be connected to the underlayer package by a plurality of C4 bumps 821 formed on the bond pads 855, respectively, and connected to portions of the seed layer 212 on the through holes 145, respectively. The thermally conductive underfill layer 50 can be formed on the underlayer package 10 and around the C4 bumps 821. The thermally conductive underfill layer 50 can completely fill the gap between the overlayer semiconductor die 800 and the underlayer package 10.

[0110] FIG. 6 is a vertical cross-sectional view of a package structure 100 having a second alternative design according to one or more embodiments. The second alternative design of the package structure 100 can also be substantially similar to the original design of FIG. 1 1. FIG. 1Athe original design. However, in a second alternative design, the upper-level package 60 can be replaced with an upper-level package 900. The upper-level package 900 can include an interposer 970 (e.g., a silicon interposer) that includes a plurality of through silicon vias (TSVs) 971 and a plurality of bond pads 972 connected to the TSVs 971 on a front side of the upper-level package 900.

[0111] The upper-level package 900 can also include one or more upper-level dies 920 flip-chip mounted on the interposer 970 by, for example, hybrid bonding. The upper-level dies 920 can be substantially identical to the first semiconductor die 120. The upper-level dies 920 can be identical or different. In at least one embodiment, one or more of the upper-level dies 920 can include a memory die such as a DRAM die. The upper-level dies 920 can be embedded in a mold encapsulation material 940 formed on the interposer 970.

[0112] In the second alternative design, the upper-level dies 920 can include an active region 922 on a front side of the upper-level dies 920. The upper-level dies 920 can also include a semiconductor layer 926 (e.g., a bulk silicon region) on the active region 922. The front side of the upper-level dies 920 can also include a passivation layer 950 and a plurality of bond pads 955 in the passivation layer 950. The bond pads 955 can be connected to the TSVs 971 in the interposer 970.

[0113] The upper-level package 900 can be connected to the lower-level package 10 by a plurality of C4 bumps 921 formed on the bond pads 972, respectively, and connected to portions of the seed layer 212 on the through holes 145, respectively. A thermally conductive underfill layer 50 can be formed on the lower-level package 10 and around the C4 bumps 921. The thermally conductive underfill layer 50 can completely fill a gap between the upper-level package 900 and the lower-level package 10.

[0114] Referring now to FIG. 1A to FIG. 6 , the package structure 100 can include a lower-level package 10, an upper-level package 60, 900, the lower-level package 10 including a first semiconductor die 120, the upper-level package 60, 900 connected to and electrically coupled to the lower-level package 10, the first semiconductor die 120 including a backside metal film 129 on a backside of the first semiconductor die 120. As shown in FIG. 1A and FIG. 6 , a thermally conductive underfill layer 50 is between the lower-level package 10 and the upper-level package 60, 900 and in contact with the backside metal film 129.

[0115] In an embodiment, the backside metal film 129 can have a thermal conductivity greater than 20 W / m-K. In an embodiment, the backside metal film 129 can include a sintered metal film including metal particles. In an embodiment, the backside metal film 129 can have a thickness less than or equal to 20 pm. In an embodiment, the metal particles have a width in a first direction less than 100 pm and a length in a second direction perpendicular to the first direction less than 100 pm. In an implementation, the metal particles can include at least one of copper, silver, aluminum, or gold. In an embodiment, the first semiconductor die 120 can further include a semiconductor layer 126 and the backside metal film 129 can be attached to the semiconductor layer 126. In an embodiment, the backside metal film 129 can have a width in the first direction less than or equal to a width of the semiconductor layer 126 in the first direction and a length in the second direction perpendicular to the first direction less than or equal to a length of the semiconductor layer 126 in the second direction. In an embodiment, the lower package 10 can further include a lower encapsulation layer 140 and the first semiconductor die 120 can be in the lower encapsulation layer 140 such that an upper surface of the backside metal film 129 can be substantially coplanar with an upper surface of the lower encapsulation layer 140. In an embodiment, the thermally conductive underfill layer 50 can include an epoxy and metal particles dispersed in the epoxy. In an embodiment, the thermally conductive underfill layer 50 can have a thermal conductivity greater than 20 W / m-K. In an embodiment, the upper package 60, 900 can include a package substrate 605 and a second semiconductor die 620 attached to and electrically coupled to the lower package 10 through the package substrate 605. In an embodiment, the lower package 10 can further include a front side redistribution layer (RDL) structure on the front side RDL structure 110 and a through via adjacent to the first semiconductor die 120 and the second semiconductor die 620 can include a dynamic random access memory (DRAM) chip electrically coupled to the front side RDL structure 110 through the through via. In an embodiment, the thermally conductive underfill layer 50 can have a thickness greater than a thickness of the backside metal film 129 substantially filling a space between the package substrate 605 and the backside metal film 129.

[0116] Referring again to FIG. 1A to FIG. 6 , a method of manufacturing the package structure 100 can include forming the first semiconductor die 120 including the backside metal film 129 on a backside of the first semiconductor die 120, forming the lower package 10 including the first semiconductor die 120, attaching the upper package 60, 900 to the lower package 10, and forming the thermally conductive underfill layer 50 between the lower package 10 and the upper package 60, 900 such that the thermally conductive underfill layer 50 contacts the backside metal film 129 in the lower package 10.

[0117] In an embodiment, the backside metal film 129 can include a sintered metal film, and the forming of the backside metal film 129 can include forming a metal film material layer 129L including a plurality of metal particles on the backside surface of the first semiconductor die 120, and heating the metal film material layer 129L to form the sintered metal film. In an embodiment, the first semiconductor die 120 can further include a semiconductor layer 126, and the forming of the backside metal film 129 can include forming the backside metal film 129 on the semiconductor layer 126 such that a width of the backside metal film 129 in a first direction can be less than or equal to a width of the semiconductor layer 126 in the first direction. A length of the backside metal film 129 in a second direction perpendicular to the first direction can be less than or equal to a length of the semiconductor layer 126 in the second direction. In an embodiment, the upper package 60, 900 can include a package substrate 605 attached to the package substrate 605 and a second semiconductor die 620, and the forming of the thermally conductive underfill layer 50 can include substantially filling a gap between the package substrate 605 and the backside metal film 129. In an embodiment, attaching the upper package 60, 900 to the lower package 10 can include electrically coupling the second semiconductor die 620 to the lower package 10 through the package substrate 605.

[0118] Referring now to FIG. 1A to FIG. 6 , a semiconductor device can include: a lower package 10 including: a frontside redistribution layer (RDL) structure 110; a lower encapsulation layer 140 on the frontside RDL structure 110; a plurality of through-holes 145 in the lower encapsulation layer 140; and a first semiconductor die 120 adjacent to the plurality of through-holes 145 in the lower encapsulation layer 140, wherein the first semiconductor die 120 can include a backside metal film 129 including an upper surface substantially co-planar with an upper surface of the lower encapsulation layer 140 and an upper surface of the plurality of through-holes 145; an upper package 60, 900 stacked on the lower package 10 and including: a package substrate 605 including a plurality of metal interconnect structures 617; an upper encapsulation layer 640 on the package substrate 605; a dynamic random access memory (DRAM) die 620 mounted on the package substrate 605 in the upper encapsulation layer 640; and a plurality of bond wires in the upper encapsulation layer 640 and electrically coupling the DRAM die to the plurality of metal interconnect structures 617; and a thermally conductive underfill layer 50 between the lower package 10 and the upper package 60, 900 and contacting the backside metal film 129.

[0119] The foregoing summarizes features of several embodiments to enable those skilled in the art to better understand aspects of the present application. Those skilled in the art should understand that they can easily use the present application as a basis for designing or modifying other processes and structures to achieve the same goals and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present application, and that they can make various changes, substitutions and alterations without departing from the spirit and scope of the present application.

Claims

1. A package structure, characterized by, Comprising: a lower package including a first semiconductor die including a backside metal film on a backside of the first semiconductor die; an upper package attached to and electrically coupled to the lower package; and a thermally conductive underfill layer between the lower package and the upper package and contacting the backside metal film. The backside metal film has a thickness less than or equal to 20 pm.

2. The package structure of claim 1, wherein, The first semiconductor die further includes a semiconductor layer and the backside metal film is attached to the semiconductor layer.

3. The package structure of claim 1, wherein, A width of the backside metal film in a first direction is less than or equal to a width of the semiconductor layer in the first direction, and a length of the backside metal film in a second direction perpendicular to the first direction is less than or equal to a length of the semiconductor layer in the second direction.

4. The package structure of claim 3, wherein, The lower package further includes a lower encapsulation layer, and the first semiconductor die is positioned in the lower encapsulation layer such that an upper surface of the backside metal film is substantially coplanar with an upper surface of the lower encapsulation layer.

5. The package structure of claim 1, wherein, The thermally conductive underfill layer includes metal particles.

6. The package structure of claim 1, wherein, The upper package includes a package substrate and a second semiconductor die attached to the package substrate and electrically coupled to the lower package through the package substrate.

7. The package structure of claim 1, wherein, The lower package further includes a frontside redistribution layer structure and through-holes adjacent to the first semiconductor die on the frontside redistribution layer structure, and the second semiconductor die includes a dynamic random access memory chip electrically coupled to the frontside redistribution layer structure through the through-holes.

8. The package structure of claim 7, wherein, A thickness of the thermally conductive underfill layer is greater than a thickness of the backside metal film and substantially fills a space between the package substrate and the backside metal film.

9. The package structure of claim 7, wherein, Comprising:

10. A semiconductor device, characterized by comprising: a lower package including: a frontside redistribution layer structure; a lower encapsulation layer on the frontside redistribution layer structure; a plurality of through-holes in the lower encapsulation layer; and a first semiconductor die adjacent to the plurality of through-holes in the lower encapsulation layer, wherein the first semiconductor die includes a backside metal film having an upper surface substantially coplanar with an upper surface of the lower encapsulation layer and an upper surface of the plurality of through-holes; an upper package stacked on the lower package and including: a package substrate including a plurality of metal interconnect structures; an upper encapsulation layer on the package substrate; a dynamic random access memory chip mounted on the package substrate in the upper encapsulation layer; and a plurality of bond wires in the upper encapsulation layer and electrically coupling the dynamic random access memory die to the plurality of metal interconnect structures; and a thermally conductive underfill layer between the lower package and the upper package and contacting the backside metal film. ​

Images