Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device comprises a substrate, an inner connecting line and a vertical connecting structure, the substrate has a front side and a back side. The interconnect is disposed over the front side of the substrate. The vertical connection structure is embedded in the interconnect and penetrates through the substrate. The vertical connection structure includes a first portion and a second portion. The first portion is embedded inside the interconnect and further extends into the substrate. A second portion is disposed in the substrate and extends from the backside to the first portion, the second portion being in contact with the first portion. An aspect ratio of the second portion is smaller than an aspect ratio of the first portion.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of semiconductor devices. BACKGROUND

[0002] The development in reducing the size of semiconductor devices and electronic components enables more devices and components to be integrated into a given volume and achieve high integration density of various semiconductor devices and / or electronic components. SUMMARY

[0003] Embodiments of the utility model provide a kind of semiconductor device including: substrate, with front side and back side;Interconnect, set on the front side of the substrate;And vertical connection structure, embedded into the interconnect and penetrate the substrate, and include: first part, embedded into the interconnect and further extended into the substrate;And second part, set in the substrate and extend from the back side to the first part, the second part is in contact with the first part, wherein the aspect ratio of the second part is less than the aspect ratio of the first part.

[0004] Embodiments of the utility model provide a kind of semiconductor device including: substrate;Interconnect, set on the substrate;Device layer, set between the substrate and the interconnect;At least one first annular wall, set in the device layer above the substrate and further extended into the interconnect;At least one first vertical connection structure, embedded into the interconnect and electrically coupled with it, and penetrate the substrate, the at least one first vertical connection includes: at least one first narrow part, embedded into the interconnect and further extended into the substrate;And first wide part, set in the substrate and exposed by the substrate, the first wide part contacts the at least one first narrow part, wherein the aspect ratio of the at least one first narrow part is greater than the aspect ratio of the first wide part;And metal feature, set on the at least one first vertical connection structure and electrically coupled with it, the substrate is set between the at least one first vertical connection structure and the device layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] Aspects of the embodiments of the utility model are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0006] Figures 1 to 23 Schematic plan or cross-sectional views showing various stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure are shown.

[0007] Figure 24Schematic cross-sectional views of semiconductor devices according to some alternative embodiments of the disclosure are shown.

[0008] Figures 25 to 28 Enlarged schematic cross-sectional views of portions of semiconductor devices according to some embodiments of the disclosure are shown.

[0009] Figure 29 With Figure 30 Schematic plan or cross-sectional views of semiconductor devices according to some embodiments of the disclosure are shown.

[0010] Figure 31 Schematic cross-sectional views of semiconductor devices according to some alternative embodiments of the disclosure are shown.

[0011] Figures 32 to 35 Enlarged schematic cross-sectional views of portions of semiconductor devices according to some embodiments of the disclosure are shown.

[0012] Figure 36 Schematic cross-sectional views of semiconductor devices according to some embodiments of the disclosure are shown.

[0013] Figure 37 A flowchart of a method for fabricating a semiconductor device according to some embodiments of the disclosure is shown.

[0014] Figure 38 Schematic cross-sectional views of applications of semiconductor devices according to some embodiments of the disclosure are shown.

[0015] Figure 39 Schematic plan views of portions of semiconductor devices according to some alternative embodiments of the disclosure are shown.

[0016] Figure 40 Schematic plan views of portions of semiconductor devices according to some alternative embodiments of the disclosure are shown.

[0017] Figure 41 Schematic cross-sectional views of portions of semiconductor devices according to some alternative embodiments of the disclosure are shown.

[0018] Figure 42 Schematic plan views of portions of semiconductor devices according to some alternative embodiments of the disclosure are shown.

[0019] Figure 43 Schematic plan views of portions of semiconductor devices according to some alternative embodiments of the disclosure are shown.

[0020] [LIST OF FIGURES]

[0021] 31, 107 L , 400n, 400n1, 400n2: first portion;

[0022] 32, 107 G 400w: second portion;

[0023] 33, 107 B : third portion;

[0024] 101: substrate;

[0025] 102: device layer;

[0026] 103, 1031, 1032, 103 N-2 130 N-1 103 N : dielectric layer;

[0027] 104, 1041, 1042, 104 N-2 104 N-1 104 N : via portion;

[0028] 105, 1051, 1052, 105 N-2 105 N-1 105 N : line portion;

[0029] 106, 1061, 1062, 106 N-2 106 N-1 106 N : patterned conductive layer;

[0030] 107, 107': interconnect;

[0031] 108: dielectric structure;

[0032] 108a: first dielectric layer;

[0033] 108b: second dielectric layer;

[0034] 109: conductive layer;

[0035] 109t: conductive line;

[0036] 109v: conductive via;

[0037] 110: bonding layer;

[0038] 300: annular wall;

[0039] 3000, 3001, 3002, 300 N-2 300 N-1 : sublayer;

[0040] 400A, 400B: vertical connection structure;

[0041] 410, 430: liner features;

[0042] 420, 440: conductive features;

[0043] 4100, 4300: seed barrier material;

[0044] 4200, 4400: conductive material;

[0045] 1000: method;

[0046] A, B, C, D, E: phantom box;

[0047] BS: back side;

[0048] C1: first component;

[0049] C2: second component;

[0050] CL400n, CL400w: centerline;

[0051] CT: terminal;

[0052] D1, D2, D3: distance;

[0053] D300: outer diameter;

[0054] D400n, D400w, D420: diameter;

[0055] FS: front side;

[0056] OP1: first open hole;

[0057] OP2: second open hole;

[0058] S1, S2, S3, S101, S101b, S101t, S102t, S1032, S103 N-1 , S105 N-1 , S1302, S300 N-1 , S300t, S400n, S400w, S410, S420, S430, S440: surface;

[0059] S108a: indicated bottom surface;

[0060] S108b, S109: indicated top surface;

[0061] S420b: end surface;

[0062] S1002, S1004, S1006, S1008, S1010, S1012, S1014, S1016, S1018, S1020, S1022, S1024: Steps;

[0063] SB1, SB2: Bottom;

[0064] SC: Component assembly;

[0065] SD1, SD1', SD2, SD3, SD3', SD4, SD5: Semiconductor devices;

[0066] SS1, SS2, SW420: Sidewalls;

[0067] SWi300: Inner wall;

[0068] SWi410: inner surface;

[0069] SWo300: Outer wall;

[0070] SWo410: Outer surface;

[0071] T101a, T101b: Thickness;

[0072] UF: Bottom filler adhesive;

[0073] W300: Width;

[0074] X, Y, Z: Direction;

[0075] 3203: Deep trench capacitor;

[0076] AA: Section cutting line. Detailed Implementation

[0077] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be reused in various instances of this disclosure. Such reuse is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0078] Moreover, spatial or directional terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of describing relative relationships between one component or feature to another component(s) or feature(s) as illustrated in the figures. Such spatial or directional terms are not intended to be limiting of the positions of the devices unless defined in the claims, and are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures.

[0079] Additionally, the terms "first", "second", "third", "fourth", and the like, can be used herein to describe similar or different components or features in the figures, and can be used interchangeably with the terms "one", "another", or "at least one".

[0080] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0081] Other features and processes can also be included. For example, test structures can be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. The test structures can include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of 3D packages or 3DIC devices, use of probes and / or probe cards, and the like. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with testing methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0082] It should be appreciated that the following embodiments of the disclosure provide applicable concepts that can be implemented in a variety of specific contexts. The embodiments are intended to provide further explanation, but are not used to limit the scope of the disclosure. The specific embodiments set forth herein are related to a semiconductor device (or semiconductor package or structure) with a through-substrate vertical connection structure, and the specific embodiments are not intended to limit the scope of the disclosure. In embodiments of the disclosure, the vertical connection structure includes a first portion having a first lateral dimension and a second portion having a second lateral dimension greater than the first lateral dimension, wherein the first portion is disposed inside the substrate and extends into the interconnect disposed at the front surface of the substrate, the second portion is disposed inside the substrate and extends to the back surface of the substrate and stops at the back surface, and the first portion is connected to the second portion. Due to the first portion of the vertical connection structure, the critical dimension (CD) of the vertical connection structure at the front surface of the substrate remains unchanged, thereby ensuring the integration of the semiconductor device; and due to the second portion of the vertical connection structure, the aspect ratio of the second portion of the vertical connection structure is less than the aspect ratio of the first portion of the vertical connection structure, thereby reducing the contact resistance (Rc).

[0083] In addition, due to the two-step formation of the vertical connection structure, the thickness of the substrate can still be thick enough to obtain a semiconductor device with good heat dissipation and better warpage control. In embodiments of the disclosure, the vertical connection structure is surrounded by a ring-shaped wall (or a protective ring-shaped wall) disposed laterally inside the interconnect. Due to the ring-shaped wall, the metal features of the interconnect can be well protected from moisture during the formation of the first portion of the vertical connection structure. In embodiments of the disclosure, the first portion and the second portion of the vertical connection structure are one-to-one architecture, such a vertical connection structure can be used to transmit signals, ground power or small power. The first portion and the second portion of the vertical connection structure can be many-to-one architecture, such a vertical connection structure can be used to transmit power.

[0084] In some embodiments, the manufacturing method is part of a wafer level packaging process. It should be understood that additional processes can be provided before, during, and after the illustrated processes and some other processes can be only briefly described herein. In this disclosure, it should be understood that the illustration of components in all figures are schematic and not drawn to scale. In all various views and exemplary embodiments of the disclosure, components similar or substantially identical to previously set forth components will use the same reference number, and certain details or descriptions of the same components (e.g., materials, formation processes, positioning configurations, electrical connections, etc.) will not be repeated. For the sake of clarity, the orthogonal axes (X, Y, and Z) of a Cartesian coordinate system are used to show the figures, and the views are oriented according to the Cartesian coordinate system; however, the disclosure is not specifically limited thereto.

[0085] Figures 1 to 23 schematic plan views or cross-sectional views of various stages in a manufacturing method of a semiconductor device (e.g., SD1) according to some embodiments of the disclosure are shown, wherein Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 and Figure 14 schematic plan views of Figure 1 , Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 are respectively outlined by the dashed boxes A depicted in the schematic cross-sectional views of Figure 16 , Figure 18 , Figure 20 and Figure 22 schematic plan views of Figure 15 , Figure 17 , Figure 19 and Figure 21 are respectively outlined by the dashed boxes B depicted in the schematic cross-sectional views of Figure 24 schematic cross-sectional views of a semiconductor device (e.g., SD2) according to some alternative embodiments of the disclosure are shown. Figures 25 to 28 schematic enlarged views of a portion of a semiconductor device (e.g., SD1 and / or SD2) according to some embodiments of the disclosure (e.g., outlined by the dashed boxes C depicted in Figure 19 and / or Figure 24 are respectively shown. Figure 37 flowcharts of methods (e.g., 1000) for manufacturing a semiconductor device according to some embodiments of the disclosure are shown. The embodiments are intended to provide further explanation, but not to limit the scope of the disclosure.

[0086] refer to Figure 1 In some embodiments, according to Figure 37 In step S1002 of the method 1000 described herein, a substrate 101 is provided. In some embodiments, the substrate 101 includes a bulk semiconductor substrate, a crystalline silicon substrate, a doped semiconductor substrate (e.g., a p-type semiconductor substrate or an n-type semiconductor substrate), a semiconductor-on-insulator (SOI) substrate, etc. In some embodiments, the substrate 101 includes one or more doped regions or various types of doped regions, depending on design requirements. In some embodiments, the doped regions are doped with p-type and / or n-type dopants. For example, the p-type dopant is boron or BF2, and the n-type dopant is phosphorus or arsenic. The doped regions can be configured as n-type metal-oxide-semiconductor (NMOS) transistors or p-type metal-oxide-semiconductor (PMOS) transistors. The substrate 101 can be a silicon wafer. Generally, an SOI substrate is formed by forming a semiconductor material on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. Other substrates may also be used, such as multi-layered substrates or gradient substrates. In some alternative embodiments, substrate 101 includes a semiconductor substrate made of elemental semiconductors (e.g., diamond or germanium with a crystalline, polycrystalline, or amorphous structure); compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); alloy semiconductors (e.g., silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, substrate 101 is a bulk silicon substrate. The compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure. Alloy SiGe may be formed on the silicon substrate. The SiGe substrate can be strained. The substrate 101 has a surface S101t and a surface S101 opposite to surface S101t in the Z direction, such as... Figure 1As shown in the diagram. The thickness T101a of substrate 101 (as measured in direction Z) can be from about 20 μm to 1100 μm, for example, 20 μm to 100 μm, 100 μm to 700 μm, or 700 μm to 1100 μm; but other suitable thicknesses can be used alternatively. For example, if the size of substrate 101 is in the form of a wafer with a diameter of about 12 inches, then the thickness of substrate 101 is about 775 μm.

[0087] Continued Figure 1 In some embodiments, according to Figure 37 In step S1004 of the method 1000 described herein, a device layer 102 is disposed on a substrate 101. One or more components (not shown) formed in the device layer 102 may be or include active components, passive components, other suitable electrical components, and / or combinations thereof. The components may include integrated circuit (IC) devices. The components may include transistors, capacitors, resistors, diodes, photodiodes, fuse devices, jumpers, inductors, or other similar devices. The functions of the components may include memory, processors, sensors, amplifiers, power distribution (active component), input / output circuitry systems, etc. The components may be referred to as semiconductor components of this disclosure. In some embodiments, the components are formed in the device layer 102 at a surface S101t of the substrate 101, or a combination thereof. The surface S101t of substrate 101 can be referred to as the active surface or front side of substrate 101, and the surface S101 of substrate 101 can be referred to as the non-active surface, back side, or rear side of substrate 101. In some embodiments, device layer 102 covers (e.g., physically contacts) the active surface or front side (e.g., S101t) of substrate 101. Device layer 102 is formed in a front-end-of-line (FEOL) manufacturing process.

[0088] In some embodiments, the device layer 102 also includes one or more metal features (not shown) formed in the FEOL fabrication process, where the components (may be further referred to as FEOL components or FEOL semiconductor components) and the metal features (may be referred to as FEOL metal features, FEOL metal contacts, or FEOL metallization contacts) are protected by a dielectric (may be referred to as FEOL dielectric) formed in the FEOL fabrication process. The components can include transistors, where the metal features can include source contacts, drain contacts, and gate contacts electrically coupled to the source, drain, and gate of the transistors, respectively. In the device layer 102, a dielectric (may be referred to as FEOL dielectric, FEOL dielectric layer, interlayer dielectric (ILD), ILD layer, FEOL ILD, or FEOL ILD layer) can cover the components, and at least some of the metal features can penetrate the dielectric to contact the components. In some embodiments, the metal features formed in the device layer 102 provide electrical connections between the components formed in the device layer 102 and the metal features formed in the interconnects (e.g., 107 in Figure 13 may be formed over the surface S101t of the substrate 101, the dielectric of the device layer 102 is disposed on the components of the device layer 102, the dielectric of the device layer 102 is patterned to form a plurality of through-holes to expose portions of the components of the device layer 102 in a touchable manner, and the metal features of the device layer 102 are formed in the plurality of through-holes formed in the dielectric of the device layer 102 to electrically couple with the components of the device layer 102. The outermost surface of the device layer 102 can be planarized to facilitate the formation of the subsequently formed interconnects (e.g., 107 in Figure 13 ).

[0089] The metal features of the device layer 102 can include copper (Cu), copper alloys, nickel (Ni), aluminum (Al), manganese (Mn), magnesium (Mg), silver (Ag), gold (Au), tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), titanium nitride (TiN), combinations thereof, or the like. Throughout the specification, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium. The metal features of the device layer 102 can be formed, for example, by plating such as electroplating or electroless plating, chemical vapor deposition (CVD) such as plasma enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. The disclosure is not limited in this regard.

[0090] The dielectric of the device layer 102 can include oxides, low-k (LK) materials, ultra low-k (ULK) materials, extra low-k (ELK) materials, and extreme low-k (XLK) materials. The classification of the materials is based on the capacitance or dielectric constant value (e.g., k value), LK materials generally refer to materials with k values between 3.1 and 2.7, ULK materials generally refer to materials with k values between 2.7 and 2.4, and ELK materials generally refer to materials with k values between 2.3 and 2.0. Further, XLK materials refer to porous HSQ-based dielectric materials with typical k values less than about 2.0. In non-limiting examples, the dielectric of the device layer 102 includes oxides, LK materials, combinations thereof, or the like. It should be understood that the dielectric of the device layer 102 can include one or more dielectric materials. For example, the dielectric of the device layer 102 includes a single layer structure or a multi-layer structure. In some embodiments, the dielectric of the device layer 102 is formed to a suitable thickness by CVD such as flowable chemical vapor deposition (FCVD), high-density plasma CVD (HDP-CVD), and sub-atmospheric CVD (SACVD), spin coating, sputtering, or other suitable methods.

[0091] A seed layer (not shown) may be selectively formed between the dielectric of device layer 102 and the metal features of device layer 102. That is, for example, the seed layer covers the bottom surface and sidewalls of each metal feature in device layer 102. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer on top of the titanium layer. The seed layer is formed using, for example, PVD or a similar process. In one embodiment, the seed layer may be omitted.

[0092] Additionally, an additional barrier layer or adhesive layer (not shown) may be selectively formed between the metallic features of device layer 102 and the dielectric of device layer 102. This additional barrier layer or adhesive layer prevents the seed layer and / or metallic features of device layer 102 from diffusing into the underlying and / or surrounding layers. The additional barrier layer or adhesive layer may include Ti, TiN, Ta, TaN, combinations thereof, multilayers thereof, or similar materials, and may be formed using CVD, ALD, PVD, combinations thereof, or similar processes. In an alternative embodiment including a seed layer, an additional barrier layer or adhesive layer is inserted between the dielectric of device layer 102 and the seed layer, with the seed layer inserted between the metallic features of device layer 102 and the additional barrier layer or adhesive layer. Alternatively, the additional barrier layer or adhesive layer may be omitted.

[0093] In some embodiments, such as Figure 1 and Figure 2 As shown, according to Figure 37 In step S1004 of the method 1000 described herein, a ring wall is formed in the device layer 102 above the substrate 101 (e.g., Figure 5 The first portion 31 of the annular wall 300. The first portion 31 of the annular wall 300 includes a sub-layer 3000, in some embodiments. The first portion 31 of the annular wall 300 can penetrate the device layer 102, such as Figure 1 As shown. For example, the surface S1 of the sublayer 3000 of the annular wall 300 is exposed in an accessible manner by the surface S102t of the device layer 102. In some embodiments, the surface S1 of the sublayer 3000 of the annular wall 300 is substantially flush with the surface S102t of the device layer 102. That is, the surface S1 of the sublayer 3000 of the annular wall 300 may be substantially coplanar with the surface S102t of the device layer 102, such as... Figure 1 As shown. In some embodiments, as Figure 2 floor plan and Figure 1As shown by the dashed frame A in the cross-sectional view, the first portion 31 of the annular wall 300 (e.g., sublayer 3000) is square, having an outer sidewall SWo300 and an inner sidewall SWi300 opposite the outer sidewall SWo300 in lateral directions (e.g., directions X and Y). Direction X may differ from direction Y, and directions X and Y may differ from direction Z. For example, direction X may be perpendicular to direction Y, and directions X and Y may be perpendicular to direction Z. Figure 2 In the plan view, the width W300 of the first portion 31 of the annular wall 300 (e.g., sublayer 3000) (e.g., the minimum lateral distance measured between the outer sidewall SWo300 and the inner sidewall SWi300) is approximately 1 μm to 3 μm, but other suitable thicknesses may optionally be used. Figure 2 In the plan view, the outer diameter D300 of the first part 31 of the annular wall 300 (e.g., sublayer 3000) is approximately 2.5 μm to 7.5 μm, but other suitable outer diameters may be used alternatively.

[0094] The formation and material of the first portion 31 of the annular wall 300 (e.g., sublayer 3000) can be similar to or substantially the same as those previously described. Figure 1 and Figure 2 The formation process and materials of the metallic features (with or without an optional seed layer) of the device layer 102 described herein will not be repeated here. In some embodiments, the sublayer 300 of the annular wall 300 0-- The dielectric of device layer 102 is spaced apart from the components and metallic features of device layer 102. In other words, the dielectric of device layer 102 laterally covers the sublayer 3000 of annular wall 300. In some embodiments, an optional seed layer may be selectively formed to cover the shown bottom surface, inner sidewall, and outer sidewall of sublayer 3000 of annular wall 300. For example, sublayer 3000 of annular wall 300 and metallic features of device layer 102 at the same height as surface S101t of substrate 101 are formed in the same step. However, this disclosure is not limited thereto. Alternatively, sublayer 3000 of annular wall 300 and metallic features of device layer 102 at the same height as surface S101t of substrate 101 may be formed in different steps. The number of building layers included in the first portion 31 of annular wall 300 may include one, two, three, or more than three, depending on requirements and design specifications, as long as the first portion 31 of annular wall 300 can completely penetrate device layer 102. For example, the number of building layers contained in the first portion 31 of the annular wall 300 is the same as the number of layers of metallic features contained in the device layer 102.

[0095] In some embodiments, the interconnect 107 (in) Figure 13 The interconnect 107 is formed on the device layer 102 located above the surface S101t of the substrate 101, and is electrically coupled to the device layer 102 (e.g., electrically coupled to a component formed in the device layer 102 via a metal feature formed in the device layer 102). That is, the interconnect 107 provides routing functionality to the component formed in the device layer 102 for electrical connection to external components, such as by a first portion of the interconnect 107 (e.g., ...). Figure 3 107 L ) provides local interconnection, provided by the second part of interconnect 107 (e.g., Figure 5 107 G The first part of the interconnect 107 is set on and connected to it, providing a global interconnect, and the third part of the interconnect 107 (e.g., Figure 13 107 B The interconnect is disposed on and connected to the second portion of the interconnect 107 and provides engagement terminals. In some embodiments, at least some of the components formed in the device layer 102 are electrically connected to each other via the interconnect 107, for example via the first portion of the interconnect 107 (e.g., Figure 3 107 L That is, the first part of interconnect 107 (for example, Figure 3 107 L Local interconnections can be provided between components formed in the device layer 102, which may be referred to as local interconnections in interconnect line 107. On the other hand, the second part of interconnect line 107 (e.g., 107 in the figure) G A global interconnect can be formed between one or more external electrical components and components in device layer 102, which may be referred to as a global interconnect in interconnect 107. In such a case, the third portion of interconnect 107 (e.g., Figure 13 107 B This can be used to bond with one or more external electrical components, and can be referred to as the bonding layer of the semiconductor device SD1. The third portion of the interconnect 107 acts as the bonding layer (e.g., Figure 13 107 B It can sometimes be considered part of the global inline of inline 107. This will be described in more detail later. Figure 3 and Figure 4 The first part of the internal connection 107 shown Figure 6 and Figure 7 The second part of the internal connection 107 shown and Figure 13 and Figure 14 Details of the third part of the inline 107 shown.

[0096] Interconnect 107 may be referred to as an interconnect, redistribution structure, rewiring structure, or routing structure. Interconnect 107 may overlay device layer 102 and include multiple build-up layers electrically connected therebetween. In some embodiments, each build-up layer includes a dielectric layer 103 and a patterned conductive layer 106 formed therein. Figure 13 As shown, interconnects 107 can be formed on and electrically connected to device layer 102. In some embodiments, interconnects 107 include one or more dielectric layers 103 (e.g., 1031, 1032, ..., 103). N-2 103 N-1 and 103 N ) and one or more patterned conductive layers 106 (e.g., 1061, 1062, ..., 106) N-2 106 N-1 and 106 N For example, each patterned conductive layer 106 (e.g., 1061, 1062, ..., 106) N-2 106 N-1 and 106 N This includes line portions 105 (e.g., 1051, 1052, ..., 105) extending along a horizontal direction (e.g., direction X or direction Y). N-2 105 N-1 and 105 N ), through-hole portions 104 (e.g., 1041, 1042, ..., 104) extending along a vertical direction (e.g., direction Z). N-2 104 N-1 and 104 N (and / or combinations thereof). The patterned conductive layer 106 may be referred to as the metallization layer or redistribution layer of the interconnect 107 to provide routing functionality and may be collectively referred to as the routing structure of the interconnect 107. The dielectric layer 103 may be collectively referred to as the dielectric structure of the interconnect 107 to provide protection for the routing structure (the metallization layer or redistribution layer of the interconnect 107). In some embodiments, in the interconnect 107, dielectric layers (e.g., 103) and patterned conductive layers (e.g., 106) are arranged alternately (e.g., formed). A dielectric layer together with a corresponding metallization layer may be considered as a building layer of the interconnect 107 (e.g., 1031 and 1061; 1032 and 1062; 103). N-2 and 106 N-2;103 N-1 and 106 N-1 ;103 N and 106 N (or its analogues). Figure 13 As shown, for example, the topmost layer of dielectric layer 103 (e.g., 103) N The topmost layer of the patterned conductive layer 106 is exposed in an accessible manner (e.g., 106). N This is for external connection. In this disclosure, the number or number of dielectric layers 103 and patterned conductive layers 106 are not limited to... Figure 13 As described herein, and may be selected and specified based on requirements and design layout. In some embodiments, the line dimensions (e.g., thickness and width) of the patterned conductive layer 106 gradually increase along the direction Z from the bottommost layer of the building layer (e.g., near device layer 102) to the topmost layer of the building layer.

[0097] In some embodiments, line portions 105 (e.g., 1051, 1052, ..., 105) extending along a horizontal direction (e.g., direction X and / or direction Y) N-2 105 N-1 and 105 N ) and / or line portions 105 extending along a horizontal direction (e.g., direction X and / or direction Y) (e.g., 1051, 1052, ..., 105) N-2 105 N-1 and 105 N ) and connected to the wire portion 105 (e.g., 1051, 1052, ..., 105) N-2 105 N-1 and 105 N The through-hole portions 104 (e.g., 1041, 1042, ..., 104) extend in a vertical direction (e.g., direction Z). N-2 104 N-1 and 104 N The conductive pattern / conductive segment is referred to as the patterned conductive layer 106. In one embodiment, the patterned conductive layer 106 (e.g., 1061, 1062, ..., 106) is used to construct the layer. N-2 106 N-1 and 106 N The materials of the two layers are the same. Alternatively, patterned conductive layers 106 (e.g., 1061, 1062, ..., 106) of different building blocks are used. N-2 106 N-1 and 106 N The materials for the lines 105 can be different from each other. Additionally, the line portions 105 (e.g., 1051, 1052, ..., 105) N-2, 105 N-1 and 105 N ) can be referred to as wires, conductive traces, conductive trenches, metallized wires, routing wires, or redistribution wires, and via portions 104 (e.g., 1041, 1042,..., 104 N-2 , 104 N-1 and 104 N ) can be referred to as vias, metallized vias, routing vias, or redistribution vias.

[0098] In addition, interconnects 107 can include one or more seed layers (not shown) to facilitate formation of patterned conductive layers 106, where a seed layer can be interposed between a patterned conductive layer 106 and a dielectric layer 103. In embodiments that include seed layers, one patterned conductive layer 106 and a corresponding one seed layer (not shown) can be referred to together as a metallization layer or redistribution layer of interconnects 107 to provide routing functionality. That is, in such embodiments, one patterned conductive layer 106 and a corresponding one seed layer (not shown) can be collectively referred to as a routing structure of interconnects 107. For example, each of the seed layers covers a bottom surface and sidewalls of a patterned conductive layer 106. In some embodiments, the seed layers are independently metal or metal alloy layers, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. The material of each seed layer can include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like, which can be formed using, for example, sputtering, PVD, or the like. In some embodiments, the seed layers include a copper layer. In some embodiments, the seed layers independently include a titanium layer and a copper layer on the titanium layer. Alternatively, the seed layers can be omitted.

[0099] Referring to Figure 3 , in some embodiments, according to step S1006 of method 1000 depicted in Figure 37 , first portions 107 L of interconnects 107 are formed on device layer 102 and first portions 31 of annular wall 300. For illustrative purposes, in Figure 3 , first portions 107 L of interconnects 107 can include two build-up layers (e.g., 1031 and 1061, and 1032 and 1062), however, the present disclosure is not limited thereto. Depending on requirements and design requirements, the number of build-up layers included in first portions 107 L of interconnects 107 can include one, two, three, or more than three, as long as first portions 107 L of interconnects 107 are capable of meeting the requirement of providing local interconnects between components of device layer 102. First portions 107 L of interconnects 107 can be referred to as local interconnects or local interconnect lines of interconnects 107.

[0100] In some embodiments, the first portion 107 L may be formed by, without limitation, forming a blanket layer of a first dielectric material over the device layer 102; patterning the blanket layer of the first dielectric material to form the dielectric layer 1031, the dielectric layer 103 1-- having a plurality of first openings (not labeled) that extend through the dielectric layer 1031 and that expose portions (e.g., metal features) of the device layer 102 in a touchable manner; optionally forming a blanket layer of a first seed layer material over the dielectric layer 1031, the blanket layer of the first seed layer material extending into the first openings to line the first openings and to contact the exposed portions of the device layer 102; forming a blanket layer of a first conductive material over the blanket layer of the first seed layer material; patterning the blanket layer of the first conductive material and the blanket layer of the first seed layer material by performing a planarization process to remove excess blanket layer of the first conductive material and the blanket layer of the first seed layer material that is above the topmost surface of the dielectric layer 1031 to form the patterned conductive layer 1061 and, optionally, the first seed layer, thereby forming a build layer (e.g., a first build layer (not labeled) that includes 1031 and 1061); forming a blanket layer of a second dielectric material over the patterned conductive layer 1061, the dielectric layer 1031, and the first respective seed layer (if any); patterning the blanket layer of the second dielectric material to form the dielectric layer 1032, the dielectric layer 103 2-- having a plurality of second openings (not labeled) that extend through the dielectric layer 1032 and that expose the top surface of the patterned conductive layer 1061 in a touchable manner; optionally forming a blanket layer of a second seed layer material over the dielectric layer 1032, the blanket layer of the second seed layer material extending into the second openings to line the second openings and to contact the exposed portions of the patterned conductive layer 1061; forming a blanket layer of a second conductive material over the blanket layer of the second seed layer material; patterning the blanket layer of the second conductive material and the blanket layer of the second seed layer material by performing another planarization process to remove excess blanket layer of the second conductive material and the blanket layer of the second seed layer material that is above the topmost surface of the dielectric layer 1032 to form the patterned conductive layer 1062 and, optionally, the second seed layer, thereby forming a build layer (e.g., a second build layer (not labeled) that includes 1032 and 1062). At this point, the first portion 107 L of the interconnect 107 has been fabricated. The first portion 107 L may be formed over the device layer 102 by a single damascene or a dual damascene process. The present disclosure is not limited in this regard. In some embodiments, the first portion 107 Lformed in a middle-end-of-line (MEOL) manufacturing process. The planarization process can include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, a combination thereof, or the like, individually. The etching process can include a dry etching, a wet etching, a combination thereof, or the like. The first portion 107 L The dielectric layer 103 included in the middle can be individually referred to as a MEOL dielectric, a MEOL dielectric layer, an ILD, an ILD layer, a MEOL ILD, or a MEOL ILD layer, and the first portion 107 L The patterned conductive layer 106 included in the middle can sometimes be individually referred to as a MEOL metal feature, a MEOL conductive layer, a MEOL metallization layer, or a MEOL redistribution layer.

[0101] The formation and materials of the dielectric layer 103 (e.g., 1031 and 1032) can be similar or substantially the same as the formation process and materials of the dielectric of the device layer 102, and thus are not repeated herein for brevity. In a non-limiting example, the dielectric layer 103 (e.g., 1031 and 1032) includes an oxide, an LK material, or a combination thereof, or the like. In one embodiment, the materials of the dielectric layer 103 (e.g., 1031 and 1032) included in the first portion 107 L The materials of the dielectric layer 103 (e.g., 1031 and 1032) included in the first portion 107 L The materials of the dielectric layer 103 (e.g., 1031 and 1032) included in the first portion 107

[0102] The formation and materials of the patterned conductive layer 106 (e.g., 1061 and 1062) can be similar or substantially the same as the formation process and materials of the metal feature of the device layer 102, and thus are not repeated herein for brevity. In a non-limiting example, the patterned conductive layer 106 (e.g., 1061 and 1062) includes Co, Ru, W, or the like. In one embodiment, the materials of the patterned conductive layer 106 (e.g., 1061 and 1062) included in the first portion 107 L The materials of the patterned conductive layer 106 (e.g., 1061 and 1062) included in the different build layers in the first portion 107 L The materials of the patterned conductive layer 106 (e.g., 1061 and 1062) included in the different build layers in the first portion 107

[0103] In some embodiments, as shown in Figure 3 and Figure 4 Figure 37 ​Step S1006 of the method 1000 described herein, the first portion 107 of the interconnect 107 on the substrate 101 L A second portion 32 of annular wall 300 is formed. The second portion 32 of annular wall 300 includes a sublayer 3001 and a sublayer 3002 stacked thereon, in some embodiments. In such a case, sublayer 3001 is disposed on and electrically coupled to sublayer 3000, and sublayer 3002 is disposed on and electrically coupled to sublayer 3001, wherein sublayer 3001 is interposed between and electrically coupled to sublayers 3000 and 3002. The second portion 32 of annular wall 300 can penetrate the first portion 170 of interconnect 107. L ,like Figure 3 As shown. In this case, sublayer 3001 passes through the first building layer (including 1031 and 1061), and sublayer 3002 passes through the second building layer (including 1032 and 1062). For example, the surface S2 of sublayer 3002 of annular wall 300 is exposed in an accessible manner by the surface S1302 of dielectric layer 1302. In some embodiments, the surface S2 of sublayer 3002 of annular wall 300 is substantially flush with the surface S1032 of dielectric layer 1032. That is, the surface S2 of sublayer 3002 of annular wall 300 can be substantially coplanar with the surface S1032 of dielectric layer 1032, such as... Figure 3 As shown. In some embodiments, as Figure 4 floor plan and Figure 3 As shown in the plan view of the portion outlined by dashed frame A in the cross-sectional view, the second portion 32 of the annular wall 300 (e.g., sublayers 3001 and 3002) is square, having an outer sidewall SWo300 and an inner sidewall SWi300 opposite to the outer sidewall SWo300 in the lateral direction (e.g., direction X and direction Y). That is, the second portion 32 (e.g., sublayers 3001 and 3002) and the first portion 31 (e.g., sublayer 3000) share the same outer sidewall SWo300 and inner sidewall SWi300.

[0104] The formation and material of the second portion 32 of the annular wall 300 (e.g., sublayers 3001 and 3002) can be similar to or substantially the same as those previously described. Figure 3 and Figure 4 The first part 107 of the interconnect described in the document L The formation process and materials of metallic features (e.g., patterned conductive layer 106 with or without optional seed layers), as previously described in Figure 1 and Figure 2The formation process and materials of the first portion 31 of the annular wall 300 (including sub-layers 3000 with or without optional seed layers) described in Figure 1 and Figure 2 The formation process and materials of the metal features of the device layer 102 (including with or without optional seed layers) described in

[0105] For a non-limiting example, the sub-layer 3001 of the annular wall 300 and the first portion 107 L of the patterned conductive layer 1061 are formed in the same step. However, the present disclosure is not limited thereto. Alternatively, the sub-layer 3001 of the annular wall 300 and the first portion 107 L of the patterned conductive layer 1061 can be formed in different steps. For another non-limiting example, the sub-layer 3002 of the annular wall 300 and the first portion 107 L of the patterned conductive layer 1062 are formed in the same step. However, the present disclosure is not limited thereto. Alternatively, the sub-layer 3002 of the annular wall 300 and the first portion 107 LThe patterned conductive layer 1062 can be formed in different steps. The number of building layers included in the second portion 32 of the annular wall 300 can be one, two, three, or more than three, depending on the requirements and design specifications, as long as the second portion 32 of the annular wall 300 can completely penetrate the first portion 107 of the interconnect 107. L That's it. For example, the number of building layers contained in the second part 32 of the annular wall 300 and the first part 107 of the interconnection 107... L The number of building layers contained in them is the same.

[0106] Continue to refer to Figure 5 In some embodiments, according to Figure 37 Step S1008 of method 1000 described herein, in the first part 107 of interconnect 107 L The second part 107 of the inner connecting line 107 is formed above the second part 32 of the annular wall 300. G To illustrate the purpose, in Figure 5 In the middle, the second part of the internal connection 107 107 G It can include at least two building layers (e.g., 103). N-2 With 106 N-2 and 103 N-1 With 106 N-1 However, this disclosure does not include or limit itself to this. Part 2 of Inline 107 G The number of building layers included can be one, two, three, or more than three, depending on requirements and design specifications, as long as the second portion 107G of interconnect 107 can meet the requirement of providing global interconnection between components in device layer 102. The second portion 107G of interconnect 107 G It can be referred to as a global inline or global inline.

[0107] Part 2 of interconnect 107 G It can be formed by (but is not limited to) repeating the formation steps of the first and / or second building layers to form the second building layer (e.g., in...). Figure 3 and Figure 4 The remaining parts of the building layers (e.g., the third building layer, the fourth building layer, ..., the (N-2)th building layer) are formed after 1032 and 1062. N-2 and 106 N-2 ), and the (N-1)th building layer (e.g., including 103 N-1 and 106 N-1 This concludes the second part of interconnect 107. G Manufacturing completed. Second part of interconnect 107.G may be formed on top of the first portion 107 L of interconnects 107 by a single damascene or dual damascene process. The present disclosure is not limited thereto.

[0108] In some embodiments, the second portion 107 G of interconnects 107 is formed in a back-end-of-line (BEOL) fabrication process. The planarization process can include a grinding process, a chemical mechanical grinding process, an etching process, or a combination thereof, among others, individually. The etching process can include a dry etching, a wet etching, or a combination thereof, among others. The second portion 107 G of interconnects 107 can be referred to as a BEOL dielectric, a BEOL dielectric layer, an ILD, an ILD layer, a BEOL ILD, or a BEOL ILD layer, individually, and the second portion 107 G of interconnects 107 can be referred to as a BEOL metal feature, a BEOL conductive layer, a BEOL metallization layer, or a BEOL redistribution layer, individually.

[0109] The formation and materials of the dielectric layers 103 (e.g., 103 N-2 and 103 N-1 ) can be similar or substantially the same as the formation process and materials of the dielectric of the device layer 102, and thus are not repeated herein for brevity. In non-limiting examples, the dielectric layers 103 (e.g., 103 N-2 and 103 N-1 ) include an oxide, an LK material, an ELK material, or a combination thereof, among others. In one embodiment, the materials of the dielectric layers 103 (e.g., 103 N-2 and 103 N-1 ) included in the second portion 107 G are the same as each other. Alternatively, the materials of the dielectric layers 103 (e.g., 103 N-2 and 103 N-1 ) included in the second portion 107 G may be partially or entirely different.

[0110] The formation and materials of the patterned conductive layers 106 (e.g., 106 N-2 and 106 N-1 ) can be similar or substantially the same as the formation process and materials of the metal features of the device layer 102, and thus are not repeated herein for brevity. In non-limiting examples, the patterned conductive layers 106 (e.g., 106 N-2 and 106 N-1 ) include Cu, a Cu alloy, or the like. In one embodiment, the materials of the patterned conductive layers 106 (e.g., 106 GThe patterned conductive layer 106 (e.g., 106) in the different building layers contained therein N-2 and 106 N-1 The materials are the same for each other. Alternatively, Part Two, 107 G The patterned conductive layer 106 (e.g., 106) in the different building layers contained therein N-2 and 106 N-1 The materials may be partially or completely different.

[0111] In some embodiments, such as Figure 5 and Figure 6 As shown, according to Figure 37 Step S1008 of method 1000 depicted in the figure, the second portion 107 of the interconnect 107 on the substrate 101 G The annular wall 300 is formed in a third portion 33. The third portion 33 of the annular wall 300 may include at least two sublayers, such as sublayer 300. N-2 and the sublayer 300 stacked on top of it N-1 ,like Figure 5 As shown. In this case, sublayer 300 N-2 Located above sublayer 3002 and electrically coupled to sublayer 3002, and sublayer 300 N-1 Located in sublayer 300 N-2 Above and electrically coupled to sublayer 300 N-2 Sub-layer 300 N-2 Inserted in sublayer 3002 and sublayer 300 N-1 And electrically coupled between and to sublayer 3002 and sublayer 300 N-1 The third part 33 of the annular wall 300 can penetrate the second part 170 of the internal connecting wire 107. G ,like Figure 5 As shown. In this case, sublayer 300 N-2 Penetrate the (N-2)th building layer (including 103) N-2 and 106 N-2 ), and sub-layer 300 N-1 Penetrate the (N-1)th building layer (including 103) N-1 and 106 N-1 For example, sublayer 300 of the annular wall 300. N-1 Surface S3 is coated with dielectric layer 103 N-1 Surface S103 N-1 Exposed in a accessible manner. In some embodiments, the sublayer 300 of the annular wall 300 N-1 Surface S3 and dielectric layer 103 N-1 Surface S103 N-1In essence, it is cut flush. That is, the sublayer 300 of the annular wall 300. N-1 Surface S3 can be substantially coplanar with dielectric layer 103 N-1 Surface S103 N-1 ,like Figure 5 As shown. In the following text, sublayer 300 N-1 Surface S3 can be referred to as surface S300t of the annular wall 300. In some embodiments, such as Figure 6 floor plan and Figure 5 The plan view of the portion outlined by the dashed frame A in the cross-sectional view shows the third part 33 of the annular wall 300 (e.g., sublayer 300). N-2 and 300 N-1 It is square in shape, having an outer sidewall SWo300 and an inner sidewall SWi300 opposite to the outer sidewall SWo300 in the lateral direction (e.g., direction X and direction Y). That is, the third part 33 of the annular wall 300 (e.g., sublayer 300) N-2 and 300 N-1 The second part 32 (e.g., sublayers 3001 and 3002) and the first part 31 (e.g., sublayer 3000) share the same outer sidewall SWo300 and inner sidewall SWi300. The outer sidewall SWo300 and inner sidewall SWi300 of the annular wall 300 can be substantially vertical sidewalls, such as... Figure 5 and Figure 6 As shown. Alternatively, at least one of the outer sidewall SWo300 and the inner sidewall SWi300 of the annular wall 300 may be inclined. This disclosure is not limited thereto. In another alternative embodiment, at least one of the outer sidewall SWo300 and the inner sidewall SWi300 of the annular wall 300 is in a wavy form.

[0112] The third part 33 of the annular wall 300 (e.g., sublayer 300) N-2 and 300 N-1 The formation and materials of ) can be similar to or substantially the same as those previously described. Figure 5 and Figure 6 The second part of interconnect 107 described in the document 107 G The formation process and materials of metallic features (e.g., patterned conductive layer 106 with or without optional seed layers), as previously described in Figure 3 and Figure 4 The first part 107 of the interconnect described in the document L The formation process and materials of metallic features (e.g., patterned conductive layer 106 with or without optional seed layers), as previously described in Figure 3 and Figure 4The formation processes and materials of the second portion 32 of the annular wall 300 (including sub-layers 3002, 3001 with or without optional seed layers) described in Figure 1 and Figure 2 The formation processes and materials of the first portion 31 of the annular wall 300 (including sub-layer 3000 with or without optional seed layers) described in Figure 1 and Figure 2 The formation processes and materials of the metal features of the device layer 102 (including with or without optional seed layers) described in and

[0113] The formation processes and materials of the second portion 32 of the annular wall 300 (including sub-layers 3002, 3001 with or without optional seed layers) described in N-2 through the dielectric layer 103 N-2 is spaced apart from the patterned conductive layer 106 N-2 The sub-layers 300 N-1 of the annular wall 300 are spaced apart from the patterned conductive layer 106 N-1 through the dielectric layer 103 N-1 . In other words, the dielectric layer 103 N-2 laterally covers the sub-layers 300 N-2 of the annular wall 300, the dielectric layer 103 N-1 laterally covers the sub-layers 300 N-1 of the annular wall 300. In some embodiments, an optional seed layer can be selectively formed to cover the illustrated bottom surface, inner sidewall, and outer sidewall of the sub-layers 300 N-2 of the annular wall 300, and another optional seed layer can be selectively formed to cover the illustrated bottom surface, inner sidewall, and outer sidewall of the sub-layers 300 N-1 of the annular wall 300. In embodiments with optional seed layers, the sub-layers 300 N-1 of the annular wall 300 are electrically coupled to the sub-layers 300 N-2 of the annular wall 300 through the optional seed layers therebetween, and the sub-layers 300 N-2 of the annular wall 300 are electrically coupled to the sub-layers 3002 of the annular wall 300 through the optional seed layers therebetween (and additional sub-layers of the third portion 33, if any). In embodiments where the optional seed layers are omitted, the sub-layers 300 N-1 of the annular wall 300 are electrically coupled to the sub-layers 300 N-2 of the annular wall 300 through direct contact, and the sub-layers 300 N-2 of the annular wall 300 are electrically coupled to the sub-layers 3002 of the annular wall 300 through direct contact (or / and through additional sub-layers of the third portion 33 (without seed layers), if any) therebetween. In other words, the second portion 32 of the annular wall 300 is in physical contact and electrically coupled to the third portion 33 of the annular wall 300.

[0113] For a non-limiting example, the sub-layers 300 N-2 and the second portion 107 G of the patterned conductive layer 106 N-2 are formed in the same step. However, the present disclosure is not limited thereto. Alternatively, the sub-layers 300 N-2 and the second portion 107 G of the patterned conductive layer 106 N-2 may be formed in different steps. For another non-limiting example, the sub-layers 300 N-1 and the second portion 107 G of the patterned conductive layer 106 N-1 are formed in the same step. However, the present disclosure is not limited thereto. Alternatively, the sub-layers 300 N-2 and the second portion 107 G of the patterned conductive layer 106 N-2 may be formed in different steps. The number of build-up layers included in the third portion 33 of the annular wall 300 can include one, two, three, or more than three, depending on requirements and design requirements, as long as the third portion 33 of the annular wall 300 is able to completely penetrate the second portion 107 G of the interconnect 107. For example, the number of build-up layers included in the third portion 33 of the annular wall 300 is the same as the number of build-up layers included in the second portion 107 G of the interconnect 107. At this point, the annular wall 300 has been fabricated.

[0114] The annular wall 300 can be referred to as a guard ring wall, a guard wall, a metal wall, a metallic wall, a conductive wall, a vertical wall, or an isolation wall. In some embodiments, if a plan view (e.g., on the XY plane) is considered, Figure 6 the cross-section of the annular wall 300 is in the form of a square ring. Alternatively, in the plan view, the cross-section of the annular wall 300 can be in the form of a circular ring, an elliptical ring, an oval ring, a rectangular ring, a hexagonal ring, an octagonal ring, or any other suitable polygonal shape, depending on requirements and design requirements. The present disclosure is not limited thereto. As Figure 5 and Figure 6 As shown, for example, in the annular wall 300, the inner walls of the first part 31, the second part 32 and the third part 33 are substantially aligned with each other in the direction Z, and the outer walls of the first part 31, the second part 32 and the third part 33 are substantially aligned with each other in the direction Z.

[0115] refer to Figure 7 and Figure 8 In some embodiments, according to Figure 37 Step S1010 of method 1000 described in the text is for... Figure 5 and Figure 6 The structure depicted is subjected to a first patterning process to create a first part 107 of the inline 107. L Part 2, 107 G A first opening hole OP1 is formed in the device layer 102 and the substrate 101. For example, the first opening hole OP1 is formed at the surface S101t of the substrate 101 (e.g., adjacent to the surface S101t). Figure 7 As shown, the first opening OP1 can completely penetrate the first part 107 of the internal connecting line 107. L Part 2, 107 G and device layer 102, and may further extend into substrate 101. In some embodiments, the first opening aperture OP1 extends from the second portion 107 of interconnect 107. G dielectric layer 103 N-1 Surface S103 N-1 The aperture extends into the device layer 102 and reaches a position inside the substrate 101. That is, the bottom (SB1) of the first opening aperture OP1 is located inside the substrate 101. This position can be approximately 1 / 2 to approximately 1 / 3 of the thickness of the substrate 101 (for surface S101); however, this disclosure is not limited to this. In this way, the first opening aperture OP1 has a small aspect ratio, is easier to control, and facilitates the formation of subsequently formed components (e.g., 400A, 400B, or combinations thereof). In this case, the first opening aperture OP1 does not penetrate the substrate 101.

[0116] The first opening OP1 can be set within the annular wall 300, such as Figure 7 and Figure 8As shown. That is, the first opening aperture OP1 is spaced apart from the annular wall 300, in some embodiments. For example, the distance D1 between the inner sidewall SWi300 of the annular wall 300 and the sidewall SS1 of the first opening aperture OP1 is between about 0.2 μm and about 2 μm, but other suitable distances may be used instead. In such cases, in a plan view, the first opening aperture OP1 is, for example, defined by the annular wall 300 (e.g., the inner sidewall SWi300). The vertical projection along the direction Z onto the substrate 101 (e.g., Figure 8 In the plan view, the first opening OP1 can be completely (or continuously) surrounded (e.g., enclosed) by the annular wall 300. Through the annular wall 300, moisture can be prevented from penetrating the first portion 107 of the inner connecting line 107 during the formation of the first opening OP1. L Part 2 and Part 107 G Metal features and metal features and components of device layer 102. If considering a plan view (e.g., XY plane) of the first opening aperture OP1, the shape of the first opening aperture OP1 may include a circle, such as... Figure 8 As shown. However, this disclosure is not limited thereto; in alternative embodiments, the shape of the first opening OP1 in the plan view can be rectangular, elliptical, oval, quadrilateral, octagonal, or any suitable polygonal shape. For example, as Figure 7 As shown, the sidewall SS1 of the first opening OP1 is substantially vertical. Alternatively, the sidewall SS1 of the first opening OP1 can be an inclined sidewall.

[0117] The first patterning process may include photolithography and etching processes. For example, in the dielectric layer 103 of the interconnect 107 N-1 Surface S103 N-1 and the sublayer 300 of the annular wall 300 N-1 Surface S300 N-1 A patterned mask layer (not shown) is formed on top. The patterned mask layer may include photoresist and / or one or more hard mask layers. For example, the patterned mask layer has a dielectric layer 103 that exposes interconnects 107 surrounded by annular walls 300. N-1An etching process using the patterned mask layer as an etching mask can then be performed. For example, an etching process with the patterned mask layer as an etching mask is performed to remove portions of the interconnects 107 exposed by the patterned mask layer, thereby forming first opening holes OP1. In addition, during the etching process, portions of the device layer 102 under the removed portions of the interconnects 107 are further removed, and portions of the substrate 101 are also removed. For illustrative purposes, the number of the first opening holes OP1 is not limited to the present disclosure, and can be specified and selected based on requirements and layout designs. The etching process can include dry etching, wet etching, or a combination thereof, etc.

[0118] With reference to Figure 9 and Figure 10 , in some embodiments, a seed barrier material 4100 and a conductive material 4200 are sequentially formed on the structure shown in Figure 7 and Figure 8 . For example, the seed barrier material 4100 is conformally formed on the surface S103 G of the second portions 107 N-1 of the interconnects 107, and further extends into the first opening holes OP1 to line the sidewalls SS1 and the bottom SB1 of the first opening holes OP1, and then the conductive material 4200 is formed over the seed barrier material 4100 and further fills the first opening holes OP1. As shown in Figure 9 , the seed barrier material 4100 can extend from the surface S103 G of the second portions 107 N-1 of the interconnects 107 to portions of the substrate 101 exposed by the first opening holes OP1. In some embodiments, the seed barrier material 4100 is disposed between the substrate 101 and the conductive material 4200, between the device layer 102 and the conductive material 4200, between the first portions 107 L of the interconnects 107 and the conductive material 4200, and between the second portions 107 GBetween the seed barrier material 4100 and the conductive material 4200. The material of the seed barrier material 4100 can be made of TiN, Ta, TaN, Ti or similar materials, and can be formed by deposition processes such as CVD, PVD, ALD, etc. The material of the conductive material 4200 can be made of copper, tungsten, aluminum, silver, combinations thereof or similar materials, and can be formed by deposition processes (e.g., CVD, PVD or similar materials), plating processes, combinations thereof, etc. Here, when "layer" is described as conformally or conformally formed, it means that the layer has substantially equal thickness extending along the region on which the layer is formed.

[0119] refer to Figure 11 and Figure 12 In some embodiments, according to Figure 37 In step S1012 of the method 1000 described herein, a first planarization process is performed on the seed barrier material 4100 and the conductive material 4200 to form a vertical connection structure in the first opening hole OP1 (e.g., Figure 19 and Figure 20 The first part 400n of 400A). For example, the seed barrier material 4100 and the conductive material 4200 are planarized, and the second part 107 located on the interconnect 107 is removed. G Surface S103 N-1 Excess seed barrier material 4100 and conductive material 4200 are partially incorporated to form a liner structure 410 and a conductive structure 420 within the first opening hole OP1, wherein the liner structure 410 and conductive structure 420 together constitute the first portion 400n of the vertical connection structure 400A. In some embodiments, the surface S410 of the liner structure 410 and the surface S420 of the conductive structure 420 together constitute the surface S400n of the first portion 400n. The inner surface SWi 410 of the liner structure 410 is in physical contact with the conductive structure 420, while the outer surface SWo 410 is in physical contact with the dielectric layer 103 of the interconnect 107, the dielectric of the device layer 102, and the dielectric of the substrate 101. Figure 11 As shown, the surface S400n of the first portion 400n (including the surface S410 of the lining feature 410 and the surface S420 of the conductive feature 420) can be substantially flush with the second portion 107 of the interconnect 107. G Patterned conductive layer 106 N-1 Surface (e.g., line portion 150) N-1 Surface S105 N-1 ) and dielectric layer 103N-1 the surface S103 of the dielectric layer 103 N-1 and the surface S300t of the annular wall 300. For example, the surface S400n of the first portion 400n (including the surface S410 of the liner feature 410 and the surface S420 of the conductive feature 420) is substantially coplanar with the surface of the patterned conductive layer 106 G the second portion 107 N-1 of the interconnect 107 N-1 the surface (e.g., S105 N-1 ) of the dielectric layer 103 N-1 the surface S103 of the dielectric layer 103 N-1 and the surface S300t of the annular wall 300.

[0120] For example, as shown in Figure 12 a plan view, the first portion 400n of the vertical connection structure 400A is defined by the annular wall 300 (e.g., the inner sidewall SWi300), with the conductive feature 420 being defined by the liner feature 410. In a plan view of Figure 12 the vertical projection of the vertical connection structure 400A on the substrate 101 along the direction Z (e.g., the plan view of Figure 12 the first portion 400n can be completely (or continuously) surrounded (e.g., enclosed) by the annular wall 300, with the conductive feature 420 being separated from the dielectric layer 103 N-1 and the annular wall 300 by the liner feature 410. In the plan view of Figure 12 the diameter (or lateral width) D420 of the conductive feature 420 of the first portion 400n is between about 1.0 pm and about 3.0 pm, although other suitable diameters can alternatively be used. In the plan view of Figure 12 the diameter (or lateral width) D400n of the first portion 400n is between about 1.0 pm and about 3.0 pm, although other suitable diameters can alternatively be used. In other embodiments, the liner feature 410 can be omitted. It should be understood that the shape of the first portion 400n of the vertical connection structure 400A can correspond to the shape of the first open hole OP1 and can be controlled by adjusting the shape of the first open hole OP1.

[0121] The first planarization process can include a grinding process, a chemical mechanical grinding process, an etching process, or a combination thereof, etc. During the execution of the first planarization process, the dielectric layer 130 N-1 and / or the patterned conductive layer 106 N-1 may also be planarized. After planarization, a cleaning process can be selectively performed to, for example, clean and remove residues generated from the first planarization process. However, the present disclosure is not limited thereto, and the first planarization process can be performed by any other suitable method.

[0122] Reference is made to Figure 13and Figure 14 In some embodiments, according to Figure 37 Step S1014 of method 1000 described herein, in the second part 107 of interconnect 107 G The third part 107 of the inner connection line 107 is formed above the first part 400n of the annular wall 300 and the vertical connecting structure 400A. B To illustrate the purpose, in Figure 13 In the middle, the third part of internal connection 107 107 B It may include a building layer (e.g., 103) N and 106 N The third part of interconnect 107. B The building blocks (e.g., 103) N and 106 N ) can be the outermost layer of the internal interconnect 107, such as Figure 13 As shown. For example, Part 3, 107 B The building blocks (e.g., 103) N and 106 N The third part of interconnect 107 is the outermost (or topmost) building layer. B It can be referred to as the bonding layer of semiconductor device SD1, and sometimes it can also be considered as part of the global interconnect of interconnect 107.

[0123] Part 3 of internal connection 107 B It can be formed by (but is not limited to) repeating the formation steps of the first and / or second building layers to form the (N-1)th building layer (e.g., including...). Figure 5 and Figure 6 103 N-1 and 106 N-1 This is followed by the formation of the outermost building layer (e.g., the (N)th building layer (e.g., including 103N and 106N)). At this point, the third part 107 of the interconnect 107... B Manufacturing completed. The third part of interconnect 107. B The second part 107 of the inlay line 107 can be formed by single or double inlay techniques. G Above. This disclosure is not limited thereto. At this point, the interconnect 107 has been manufactured. In some embodiments, a first portion 400n of the vertical connection structure 400A is electrically coupled to the interconnect 107. As... Figure 13 As shown, the third part of interconnect 107 B Patterned conductive layer 106 in N 104 through-hole portion NThe conductive feature 420 in the first part 400n of the vertical connection structure 400A can be physically accessed. For example, along the direction Z in the vertical projection (e.g.) Figure 14 ), the third part of internal connection 107 B Patterned conductive layer 106 in N 104 through-hole portion N The conductive feature 420 stands on (e.g., overlaps) the first part 400n of the vertical connection structure 400A.

[0124] In some embodiments, the third portion 107 of the interconnect 107 B It is formed in the BEOL manufacturing process. The planarization process can individually include polishing, chemical mechanical polishing, etching, or a combination thereof. The etching process can include dry etching, wet etching, or a combination thereof. (The third part of interconnect 107) B The dielectric layer 103 included (e.g., 103) N It can be independently referred to as BEOL dielectric, BEOL dielectric layer, ILD, ILD layer, BEOL ILD, or BEOL ILD layer, and includes the third part 107 of the inner interconnect 107. B The patterned conductive layer 106 included (e.g., 106) N It can sometimes be independently referred to as a BEOL metallic feature, a BEOL conductive layer, a BEOL metallization layer, or a BEOL redistribution layer.

[0125] Dielectric layer 103 (e.g., 103) N The formation and materials of dielectric layer 103 can be similar to or substantially the same as those of dielectric layer 102, and therefore will not be repeated here for the sake of simplicity. In a non-limiting example, dielectric layer 103 (e.g., 103) N This includes oxides, LK materials, ELK materials, or combinations thereof. The patterned conductive layer 106 (e.g., 106) N The formation and materials of the conductive layer 106 can be similar to or substantially the same as those used to form the metallic features of the device layer 102, and therefore will not be repeated here for the sake of simplicity. In a non-limiting example, the patterned conductive layer 106 (e.g., 106) N This includes Cu, Cu alloys, Al, etc.

[0126] After the structural layer of interconnection 107 is formed, Figure 13 and Figure 14 The structure shown can be flipped (i.e., upside down) and secured by a holding device (not shown). For example, the holding device (not shown) is used to hold the internal wiring 107 in place. Figure 13 and Figure 14 The structure shown is fixed in place. The clamping device can be adhesive tape, carrier film, or suction pad. For example, after being flipped over, substrate 101 faces upward and can be exposed in an accessible manner.

[0127] refer to Figure 15 and Figure 16 In some embodiments, according to Figure 37 In step S1016 of the method 1000 described herein, substrate 101 is planarized. For example, the back side of substrate 101 (e.g., surface S101) undergoes a planarization process to obtain surface S101b, which is sufficiently flat to facilitate subsequent processes. Surface S101b of substrate 101 may be referred to as the non-active surface, back side, or rear side of substrate 101. The planarization process may include a polishing process, a chemical mechanical polishing process, an etching process, or a combination thereof. During the planarization process, naturally formed oxides on surface S101 of substrate 101 may also be planarized (e.g., removed). After planarization, a cleaning process may be selectively performed to, for example, clean and remove residues generated from the planarization process. However, this disclosure is not limited thereto, and the planarization process may be performed by any other suitable method.

[0128] Continue to refer to Figure 15 and Figure 16 In some embodiments, according to Figure 37 In step S1018 of the method 1000 described herein, a second patterning process is performed on the substrate 101 to form a second opening hole OP2. For example, the second opening hole OP2 is formed at the surface S101b of the substrate 101 (e.g., adjacent to surface S101b). Figure 15As shown, the second opening aperture OP2 can extend from the surface S101b of the substrate 101 toward the device layer 102, reaching a position inside the substrate 101 where the bottom SB1 and sidewall SS1 of the first opening aperture OP1 are exposed. For example, the bottom SB1 of the first opening aperture OP1 is completely exposed by the second opening aperture OP2, while the sidewall SS1 of the first opening aperture OP1 is partially exposed by the second opening aperture OP2. In this case, a portion of the lining feature 410 of the first portion 400n of the vertical connection structure 400A (e.g., the outer surface SWo410 of the lining feature 410 located at the bottom SB1 and sidewall SS1 of the first opening aperture OP1) is exposed by the second opening aperture OP2. That is, the bottom SB2 of the second opening aperture OP2 is located inside the substrate 101. This position may be at approximately 1 / 2 to approximately 1 / 3 of the thickness of the substrate 101 (having surface S101b); however, this disclosure is not limited thereto. In this way, the aspect ratio of the second opening aperture OP2 is small, making it easier to control and facilitating the formation of subsequent components (e.g., 400A, 400B, or combinations thereof). In this case, the second opening aperture OP2 does not penetrate the substrate 101. In some embodiments, the aspect ratio of the second opening aperture OP2 is smaller than that of the first opening aperture OP1.

[0129] The second opening OP2 can be set on the annular wall 300, such as Figure 15 As shown. That is, in some embodiments, the second opening aperture OP2 is perpendicularly away from the annular wall 300. In a plan view, the second opening aperture OP2 can be defined by the annular wall 300 (e.g., the outer wall SWo 300). That is, the lateral dimension of the second opening aperture OP2 can be less than or substantially equal to the lateral dimension of the annular wall 300. For example, the vertical projection along direction Z onto the substrate 101 (e.g., Figure 16 In the plan view), the sidewall SS2 of the second opening hole OP2 is aligned with the outer sidewall SWo300 of the annular wall 300. In this case, the vertical projection along the direction Z onto the substrate 101 (e.g., Figure 16 In the plan view, the sidewall SS2 of the second opening aperture OP2 overlaps with the periphery (e.g., the outer wall SWo300) of the annular wall 300. In embodiments where the sidewall SS2 of the second opening aperture OP2 is substantially aligned with the outer wall SWo300 of the annular wall 300, the width of the second opening aperture OP2 is substantially equal to the outer diameter D300 of the annular wall 300. This disclosure is not limited thereto. Alternatively, the vertical projection along the direction Z onto the substrate 101 (e.g., Figure 15In the plan view of the substrate 101, the second open hole OP2 can be completely (or continuously) surrounded (e.g., enclosed) by the annular wall 300. In such a case, in a vertical projection on the substrate 101 along the direction Z, the sidewall SS2 of the second open hole OP2 is closer to the center (not labeled) of the annular wall 300 than the outer sidewall SWo300 of the annular wall 300. In embodiments where the sidewall SS2 of the second open hole OP2 is enclosed by the outer sidewall SWo300 of the annular wall 300, the width of the second open hole OP2 is less than the outer diameter D300 of the annular wall 300.

[0130] If the plan view (e.g., XY plane) of the second open hole OP2 is considered, the shape of the second open hole OP2 can include a circle, as shown in Figure 16 However, the present disclosure is not limited thereto; in alternative embodiments, in the plan view, the shape of the second open hole OP2 can be a rectangle, an ellipse, an oval, a quadrilateral, an octagon, or any suitable polygonal shape. For example, as shown in Figure 15 The sidewall SS2 of the second open hole OP2 can be substantially vertical. Alternatively, the sidewall SS2 of the second open hole OP2 can be an inclined sidewall. In another aspect, as shown in Figure 15 The bottom SB2 of the second open hole OP2 can be lower than the bottom SBl of the first open hole OPl.

[0131] The second patterning process can include a photolithography and etching process. For example, a patterned mask layer (not shown) is formed on the surface S101b of the substrate 101. The patterned mask layer can include a photoresist and / or one or more hard mask layers. For example, the patterned mask layer has an opening (not shown) exposing a portion of the substrate 101 corresponding to the annular wall 300. Then, an etching process using the patterned mask layer as an etching mask can be performed. For example, the etching process with the patterned mask layer as an etching mask is performed to remove the portion of the substrate 101 exposed by the patterned mask layer, thereby forming the second open hole OP2. In addition, during the etching process, the liner feature 410 of the first portion 400n exposed by the second open hole OP2 is not removed; however, the present disclosure is not limited thereto, and in other alternative embodiments, a portion of the liner feature 410 of the first portion 400n under the second open hole OP2 can be removed. Figure 25 and / or Figure 28 For illustration purposes, the number of the second open holes OP2 is not limited by the present disclosure and can be specified and selected based on requirements and layout design. The etching process can include dry etching, wet etching, or a combination thereof, etc. Figure 26 Figure 27 For illustration purposes, the number of the second open holes OP2 is not limited by the present disclosure and can be specified and selected based on requirements and layout design. The etching process can include dry etching, wet etching, or a combination thereof, etc.

[0132] Referring to​ Figure 17 and Figure 18 In some embodiments, the seed barrier material 4300 and the conductive material 4400 are sequentially formed over the structure shown in Figure 15 and Figure 16 For example, the seed barrier material 4300 is conformally formed over the surface S101b of the substrate 101 and further extends into the second open hole OP2 to line the sidewall SS2 and the bottom SB2 of the second open hole OP2, and then the conductive material 4400 is formed over the seed barrier material 4300 and further fills the second open hole OP2. As shown in Figure 17 The seed barrier material 4300 can extend from the surface S101b of the substrate 101 to a portion of the first portion 400n of the vertical connection structure 400A exposed by the second open hole OP2. That is, the portion of the first portion 400n of the vertical connection structure 400A exposed by the second open hole OP2 is covered (e.g., physically contacted) by the seed barrier material 4300. In some embodiments, the seed barrier material 4300 is disposed between the substrate 101 and the conductive material 4400 and between the first portion 400n and the conductive material 4400. The formation of the seed barrier material 4300 is similar or substantially the same as the formation process and material of the seed barrier material 4100 previously described in Figure 10 and the formation of the conductive material 4400 is similar or substantially the same as the formation process and material of the conductive material 4200 previously described in Figure 10 In non-limiting examples, the material of the seed barrier material 4300 is the same as the material of the seed barrier material 4100. Alternatively, the material of the seed barrier material 4300 is different from the material of the seed barrier material 4100. In non-limiting examples, the material of the conductive material 4400 is the same as the material of the conductive material 4200. Alternatively, the material of the conductive material 4400 is different from the material of the conductive material 4200.

[0133] Referring to Figure 19 and Figure 20 In some embodiments, the seed barrier material 4300 and the conductive material 4400 are sequentially formed over the structure shown in Figure 37At step S1020 of the depicted method 1000, a second planarization process is performed on the seed barrier material 4300 and the conductive material 4400 to form a second portion 400w of the vertical connection structure 400A in the second open hole OP2, thereby forming the vertical connection structure 400A. For example, the seed barrier material 4300 and the conductive material 4400 are planarized to remove portions of the seed barrier material 4300 and the conductive material 4400 that are located above the surface S101b of the substrate 101 to form a liner feature 430 and a conductive feature 440 inside the second open hole OP2, where the liner feature 430 and the conductive feature 440 collectively constitute the second portion 400w of the vertical connection structure 400A. In some embodiments, a surface S430 of the liner feature 430 and a surface S440 of the conductive feature 440 together constitute a surface S400w of the second portion 400w. As shown in Figure 19 the surface S400w of the second portion 400w (including the surface S430 of the liner feature 430 and the surface S440 of the conductive feature 440) can be substantially flush with the surface S101b of the substrate 101. For example, the surface S400w of the second portion 400w (including the surface S430 of the liner feature 430 and the surface S440 of the conductive feature 440) is substantially coplanar with the surface S101b of the substrate 101.

[0134] For example, as shown in Figure 20 in a plan view, the second portion 400w of the vertical connection structure 400A is defined by the annular wall 300 (e.g., the outer sidewall SWo 300), where the conductive feature 440 is defined by the liner feature 430. In a plan view (e.g., of Figure 20 the vertical projection of the substrate 101 along the direction Z), the second portion 400w of the vertical connection structure 400A and the annular wall 300 can be completely (or entirely) overlapped with each other, where in a cross-sectional view (e.g., of Figure 19 ), the conductive feature 440 can be separated from the substrate 101 and the annular wall 300 through the liner feature 430. In a plan view (e.g., of Figure 20 , the diameter (or lateral width) D400w of the second portion 400w is between about 2.5 pm and about 7.5 pm, although other suitable diameters can be optionally used. In a non-limiting example, the diameter D400w of the second portion 400w is substantially the same as the outer diameter D300 of the annular wall 300. In other embodiments, the liner feature 430 can be omitted. It should be understood that the shape of the second portion 400w of the vertical connection structure 400A can correspond to the shape of the second open hole OP2 and can be controlled by adjusting the shape of the second open hole OP2.

[0135] As an alternative (not shown), the second portion 400w of the vertical connection structure 400A can completely (or entirely) overlap the annular wall 300 along a vertical projection on the substrate 101 in the direction Z, and the perimeter of the annular wall 300 can protrude beyond the perimeter of the second portion 400w, with the conductive feature 440 in its cross-sectional view being separated from the substrate 101 and the annular wall 300 by the liner feature 430. In such an alternative embodiment, the diameter D400w of the second portion 400w is smaller than the outer diameter D300 of the annular wall 300.

[0136] The second planarization process can include a grinding process, a chemical mechanical grinding process, an etching process, or a combination thereof, etc. During the execution of the second planarization process, the substrate 101 can also be planarized. After planarization, a cleaning process can be selectively performed to, for example, clean and remove residues generated from the second planarization process. However, the present disclosure is not limited thereto, and the second planarization process can be performed by any other suitable method.

[0137] So far, the vertical connection structure 400A (including a first portion 400n and a second portion 400w) has been fabricated. In some embodiments, in the vertical connection structure 400A, the second portion 400w is disposed above and electrically coupled to the first portion 400n. In some embodiments, the first portion 400n and the second portion 400w of the vertical connection structure 400A are formed by different and independent steps (which can be referred to as a two-step process) according to a one-to-one architecture, in which the first portion 400n and the second portion 400w are formed in different steps. Figure 19In the cross-sectional view, the sidewall of the vertical connection structure 400A has a step-form profile. Due to the formation process of the vertical connection structure 400A, the aspect ratio of the first portion 400n is reduced, making the manufacturing process of the vertical connection structure 400A easy and reliable. Due to the first portion 400n (which has a larger aspect ratio than the second portion 400w), the critical dimension of the vertical connection structure 400A at the front side (e.g., S101t) of the substrate 101 remains unchanged, thereby ensuring (or guaranteeing) the integration of the semiconductor device SD1; and due to the second portion 400w (which has a smaller aspect ratio than the first portion 400n), the contact resistance (Rc) of the semiconductor device SD1 can be reduced. In addition, due to the first portion 400n and the second portion 400w of the vertical connection structure 400A being formed in two steps, the thickness T101b of the substrate 101 can still be thick enough to obtain good heat dissipation and better warpage of the semiconductor device SD1. In embodiments of the present disclosure, since the first portion 400n is laterally surrounded by the annular wall 300 inside the interconnect 107, the metal features of the interconnect 107 can be well protected from moisture during the formation of the first portion 400n. In some embodiments, the vertical connection structure 400A can be used to transmit signals, ground power, or smaller power. The first portion 400n can be referred to as a narrow portion, the second portion 400w can be referred to as a wide portion, and the vertical connection structure 400A can be referred to as a through-substrate-via or a through-silicon-via (TSV), a through via, a conductive via, or a conductive pillar.

[0138] Reference Figure 21 and Figure 22 In some embodiments, according to step S1022 of the method 1000 depicted in Figure 37 , a bonding layer 110 is formed over the substrate 101. For example, the bonding layer 110 is disposed over and electrically coupled to the vertical connection structure 400A for providing routing functionality to the vertical connection structure 400A and / or providing electrical connection of the vertical connection structure 400A to external components. In some embodiments, the bonding layer 110 is disposed on (e.g., physically contacts) and physically and electrically connected to the substrate 101 and the vertical connection structure 400A. In such cases, the bonding layer 110 can be disposed entirely on the substrate 101, as shown in Figure 21 .

[0139] The formation of the bonding layer 110 can be formed by, but not limited to, the following: forming a blanket layer (not shown) of a third dielectric material over the substrate 101 to cover the vertical connection structure 400A; forming a blanket layer (not shown) of a fourth dielectric material over the blanket layer of the third dielectric material, such that the blanket layer of the third dielectric material is sandwiched between the blanket layer of the fourth dielectric material and the substrate 101; patterning the blanket layer of the third dielectric material and the blanket layer of the fourth dielectric material to form a first dielectric layer 108a and a second dielectric layer 108b disposed over the first dielectric layer 108a, wherein a plurality of openings (not labeled) are formed through the first dielectric layer 108a and the second dielectric layer 108b; forming an optional seed layer (not shown) in the plurality of openings; forming a conductive material in the plurality of openings to form a conductive layer 109 over the optional seed layer, thereby forming the bonding layer 110. For example, as shown in FIG. 1, the metallization layer (not labeled) of the bonding layer 110 includes the conductive layer 109 and, if present, the optional seed layer (not shown) thereunder and electrically connected thereto, and the metallization layer of the bonding layer 110 is embedded in the dielectric structure 108 of the bonding layer 110, wherein the dielectric structure 108 includes the first dielectric layer 108a and the second dielectric layer 108b stacked thereover. For example, the conductive layer 109 is electrically coupled to the vertical connection structure 400A by direct contact. Figure 21 Figure 21 As shown in FIG. 1, the conductive layer 109 can be electrically coupled to a metal feature of the interconnect 107 through the vertical connection structure 400A. In such a case, the conductive layer 109 can be electrically coupled to a component of the device layer 102 through the vertical connection structure 400A and the interconnect 107.

[0140] ​In some embodiments, the first dielectric layer 108a and the second dielectric layer 108b have different materials. For example, the first dielectric layer 108a includes a silicon carbide (SiC) layer, a silicon nitride (Si3N4) layer, an aluminum oxide layer, or the like. For example, the second dielectric layer 108b includes a silicon-rich oxide (SRO) layer. In some embodiments, the second dielectric layer 108b is referred to as an inter-metal dielectric (IMD) layer, which can be made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. In some alternative embodiments, the first dielectric layer 108a and the second dielectric layer 108b have different etching selectivities. In some cases, the first dielectric layer 108a can be referred to as an etch stop layer to prevent damage to underlying components (e.g., the substrate 101 and / or the vertical connection structure 400A) caused by over-etching.

[0141] In some embodiments, the blanket of the third dielectric material and the blanket of the fourth dielectric material are patterned through a set (or multiple sets) of photolithography and etching processes. The etching processes can include dry etching, wet etching, or a combination thereof. After the etching processes, a cleaning step can be selectively performed to, for example, clean and remove residues generated from the etching processes. However, the disclosure is not limited thereto, and the etching processes can be performed through any other suitable method. Each opening can include a trench hole and a via hole that is spatially connected to the trench hole below the trench hole. For example, the trench hole is formed in the second dielectric layer 108b and extends from the illustrated top surface S108b of the second dielectric layer 108b to a location inside the second dielectric layer 108b. For example, the via hole is formed in the second dielectric layer 108b and the first dielectric layer 108a and extends from the location inside the second dielectric layer 108b to the illustrated bottom surface S108a of the first dielectric layer 108a. The location can be at about 1 / 2 to about 1 / 3 of the thickness of the second dielectric layer 108b; however, the disclosure is not limited thereto. In some embodiments, the opening includes a dual damascene structure. The formation of the opening is not limited to the disclosure. The formation of the opening (with the dual damascene structure) can be formed through any suitable formation process such as a via first method or a trench first method.

[0142] As Figure 21As shown, the lateral dimension of the trench via can be greater than the lateral dimension of the via. In some embodiments, each sidewall of the via is a substantially vertical sidewall. In alternative embodiments, each sidewall of the via is an inclined sidewall. In some embodiments, each sidewall of the trench via is a substantially vertical sidewall. In alternative embodiments, each sidewall of the trench via is an inclined sidewall. The sidewalls of a via and the sidewalls of a trench via can be collectively referred to as the sidewalls of an opening. For illustration purposes, Figure 21 The number of openings shown in FIG. 1A is not limited to the present disclosure and can be specified and selected based on requirements and layout design. As shown in FIG. 1A, the portions of the conductive layer 109 in the metallization layer formed in the trench vias can be referred to as conductive lines, conductive traces, or conductive wires 109t extending along a horizontal direction (e.g., extending in the direction X and / or the direction Y), and the portions of the conductive layer 109 in the metallization layer formed in the vias can be referred to as conductive vias 109v extending along a vertical direction (e.g., extending in the direction Z). Figure 21 As shown, the portions of the conductive layer 109 in the metallization layer formed in the trench vias can be referred to as conductive lines, conductive traces, or conductive wires 109t extending along a horizontal direction (e.g., extending in the direction X and / or the direction Y), and the portions of the conductive layer 109 in the metallization layer formed in the vias can be referred to as conductive vias 109v extending along a vertical direction (e.g., extending in the direction Z). Figure 21 As shown, the conductive vias 109v can stand on and be electrically coupled to the vertical connection structure 400A. Figure 22 As shown, the portions of the conductive layer 109 in the metallization layer formed in the trench vias can be referred to as conductive lines, conductive traces, or conductive wires 109t extending along a horizontal direction (e.g., extending in the direction X and / or the direction Y), and the portions of the conductive layer 109 in the metallization layer formed in the vias can be referred to as conductive vias 109v extending along a vertical direction (e.g., extending in the direction Z).

[0143] In some embodiments, the optional seed layer and the conductive layer 109 can be formed in the openings sequentially by, but not limited to, forming a blanket layer composed of a metal or a metal alloy material conformally over the dielectric structure 108 and extending into the openings to line the sidewalls of the openings; filling the openings with a conductive material; and removing the excess amount of the blanket layer composed of the metal or the metal alloy material and the conductive material above the illustrated top surface S108b of the second dielectric layer 108b, thereby fabricating the metallization layer including the optional seed layer and the conductive layer 109. The removing can be performed by a planarization process (e.g., mechanical grinding, chemical mechanical grinding, and / or etching process, etc.). After the planarization process, a cleaning process can be selectively performed to, for example, clean and remove the residue generated from the planarization process. However, the present disclosure is not limited thereto, and the planarization process can be performed by any other suitable method.

[0144] In some embodiments, the optional seed layer is referred to as a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the optional seed layer includes titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the optional seed layer can include a titanium layer and a copper layer on top of the titanium layer. The optional seed layer can be formed using, for example, sputtering, PVD, or the like. The optional seed layer can have a thickness (e.g., measured in the direction Z) of between about 0.5 nm and about 100 nm, although other suitable thicknesses can alternatively be used.

[0145] In some embodiments, the material for forming the conductive material of the conductive layer 109 includes a suitable conductive material, such as a metal and / or a metal alloy. For example, the conductive material can be Al, an aluminum alloy, Cu, a copper alloy, or a combination thereof (e.g., AlCu), the like, or a combination thereof. In some embodiments, the conductive material is formed by a plating process or any other suitable method, where the plating process can include electroplating or electroless plating, or the like. In alternative embodiments, the conductive material can be formed by deposition. The disclosure is not limited in this regard. In some cases, the illustrated top surface S109 of the conductive layer 109 in the metallization layer is substantially flush with the illustrated top surface (e.g., S108b) in the dielectric structure 108. That is, the illustrated top surface S109 of the conductive layer 109 in the metallization layer can be substantially coplanar with the illustrated top surface (e.g., S108b) of the dielectric structure 108.

[0146] Referring to Figure 23 In some embodiments, after the formation of the bonding layer 110, a dicing (singulation) process is performed to cut through the bonding layer 110, the substrate 101, the device layer 102, and the interconnects 107, thereby separating the semiconductor device SD1 from the other semiconductor devices in the wafer. Figure 21 and Figure 22 The structure shown in FIG. 1A is singulated to form multiple independent and separated semiconductor devices SD1. At this point, the semiconductor device SD1 is fabricated, where the semiconductor device SD1 has a front side FS including an outermost surface of the interconnects 107 and a backside BS including an outermost surface of the bonding layer 110. The interconnects 107 can be referred to as front side interconnects or front side interconnects of the semiconductor device SD1. As shown in FIG. 1A, the semiconductor device SD1 has a front side FS including an outermost surface of the interconnects 107 and a backside BS including an outermost surface of the bonding layer 110. Figure 23As shown, the sidewalls of the semiconductor device SD1 can be substantially vertical sidewalls, which may include the sidewalls of the bonding layer 110, the sidewalls of the substrate 101, and the sidewalls of the interconnect 107. In this case, the sidewalls of the bonding layer 110, the sidewalls of the substrate 101, and the sidewalls of the interconnect 107 are substantially aligned with each other in the Z direction. In some embodiments, the vertical interconnect structure 400A is embedded in the substrate 101 and the interconnect 107 and electrically coupled to the bonding layer 110, the interconnect 107, and the device layer 102. In one embodiment, the dicing (monolithography) process is a wafer dicing process including mechanical blade sawing or laser cutting, etc. This disclosure is not limited thereto.

[0147] In an embodiment of the semiconductor device SD1, the cross-section of the annular wall 300 is rectangular and annular. However, this disclosure is not limited thereto; alternatively, in a plan view, the cross-section of the annular wall 300 may be circular and annular, see reference. Figure 39 In an embodiment of the semiconductor device SD1, the outer sidewall SWo300 and the inner sidewall SWi300 of the annular wall 300 are substantially vertical. However, this disclosure is not limited thereto; alternatively, the outer sidewall SWo300 and the inner sidewall SWi300 of the annular wall 300 are wave-shaped, see reference. Figure 41 The semiconductor device SD1'. Alternatively, the outer sidewall SWo300 and inner sidewall SWi300 of the annular wall 300 are substantially inclined. In embodiments where the annular wall 300 employs inclined sidewalls, the outer diameter D300 of the annular wall 300 can be determined from surface S103. N-1 North Korean surface S101 t It gradually tapers. Alternatively, the outer diameter D300 of the annular wall 300 can taper from surface S101t toward surface S103. N-1 Gradually becoming thinner.

[0148] In an embodiment of the semiconductor device SD1, a bonding layer 110 is provided, comprising a conductive layer 109 and a dielectric structure 108. The bonding layer 110 is disposed at the surface S101b of the substrate 101 and electrically coupled to a vertical interconnect structure 400A for providing routing functionality and / or providing electrical connections to external components. However, this disclosure is not limited thereto; alternatively, the bonding layer 110 may be replaced by an interconnect, see reference... Figure 24 Throughout the various views and illustrative embodiments disclosed herein, components that are similar to or substantially the same as those previously described will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated.

[0149] In some embodiments, Figure 24 Semiconductor device SD2 and Figure 23 The semiconductor device SD1 is similar; the difference is that... Figure 24 In the semiconductor device SD2, the bonding layer 110 is replaced by an interconnect 107'. In some embodiments, the interconnect 107' is disposed at the surface S101b of the substrate 101 and electrically coupled to a second portion 400w of the vertical connection structure 400A, while the interconnect 107 is disposed at the surface S101t of the substrate 101 and electrically coupled to a first portion 400n of the vertical connection structure 400A, wherein the interconnect 107' is electrically coupled to the interconnect 107 through the vertical connection structure 400A, and the interconnect 107' is electrically coupled to the device layer 102 through the vertical connection structure 400A and the interconnect 107. In some embodiments, the vertical connection structure 400A is embedded in the substrate 101 and the interconnect 107, and is electrically coupled to the interconnect 107', the interconnect 107, and the device layer 102. Interconnect 107 can be referred to as the front interconnect or front interconnect of semiconductor device SD2, and interconnect 107' can be referred to as the back interconnect or back interconnect of semiconductor device SD2.

[0150] like Figure 24 As shown, the semiconductor device SD2 may have a front side FS including the outermost surface of the interconnect 107 and a back side BS including the outermost surface of the interconnect 107'. In some embodiments, the sidewalls of the semiconductor device SD2 are substantially vertical sidewalls, which may include the sidewalls of the interconnect 107', the sidewalls of the substrate 101, and the sidewalls of the interconnect 107. In such a case, the sidewalls of the interconnect 107', the sidewalls of the substrate 101, and the sidewalls of the interconnect 107 are substantially aligned with each other in the Z direction. The details, formation, and materials of the interconnect 107' are similar to or substantially the same as the formation process and materials of the interconnect 107, and therefore will not be described further here. In such a case, step S1022 of method 1000 may be... Figure 37 The method 1000 is replaced by step S1024.

[0151] In the above embodiment, the lining feature 410 remains on the sidewall SW420 and end surface S420b of the conductive feature 420, and completely covers the sidewall SW420 and end surface S420b of the conductive feature 420. (Refer to...) Figure 25 and Figure 28 However, this disclosure is not limited thereto. In some alternative embodiments, the portion of the lining feature 410 initially disposed on the end surface S420b of the conductive feature 420 can be completely removed, see reference [link to relevant documentation]. Figure 26For example, the end surface S420b of the conductive feature 420 is completely (or entirely) exposed by the liner feature 410, and the sidewall SW420 of the conductive feature 420 is completely (or entirely) covered by the liner feature 410. In this way, the electrical connection between the first portion 400n and the second portion 400w can be improved. In some other embodiments, the portion of the liner feature 410 initially disposed on the end surface S420b of the conductive feature 420 can be completely removed, and the portion of the liner feature 410 initially disposed on the sidewall SW420 of the conductive feature 420 can be partially removed, with reference to Figure 27 For example, the end surface S420b of the conductive feature 420 is completely (or entirely) exposed by the liner feature 410, and the sidewall SW420 of the conductive feature 420 is partially covered by the liner feature 410. In this way, the electrical connection between the first portion 400n and the second portion 400w can be further improved.

[0152] In the above embodiments, the central line CL400w of the second portion 400w of a vertical connection structure 400A is substantially aligned with the central line CL400n of the first portion 400n, with reference to Figures 25 to 27 For example, the second portion 400w and the first portion 400n of a vertical connection structure 400A share a common central line (not labeled). However, the present disclosure is not limited thereto. In some alternative embodiments, the central line CL400w of the second portion 400w of a vertical connection structure 400A is offset from the central line CL400n of the first portion 400n, with reference to Figure 28 .

[0153] In the semiconductor devices SD1 and SD2, only one vertical connection structure 400A is present. However, the number of vertical connection structures 400A can be one, two, three, or more than three, depending on the requirements and design requirements. The present disclosure is not limited thereto.

[0154] Figure 29 and Figure 30 schematic plan view or cross-sectional view of a semiconductor device (e.g., SD3) according to some embodiments of the present disclosure is shown, wherein Figure 29 the schematic plan view of Figure 30 is outlined by the dashed box D depicted in the schematic cross-sectional view of Figure 31 schematic cross-sectional view of a semiconductor device (e.g., SD4) according to some alternative embodiments of the present disclosure is shown. Figures 32 to 35 portions (e.g., by Figure 29 and / or Figure 31 The schematic enlarged view (delineated by the dashed frame E) depicted is shown. The embodiments described are intended to provide further explanation but are not intended to limit the scope of this disclosure. Throughout the various views and illustrative embodiments of this disclosure, components similar to or substantially identical to those previously described will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated.

[0155] In some embodiments, Figure 29 and Figure 30 The semiconductor device SD3 is similar to Figure 23 (and simultaneous reference) Figure 22 The semiconductor device SD1 is different; in Figure 29 and Figure 30 In the semiconductor device SD3, a vertical connection structure 400B is used instead of a vertical connection structure 400A. The vertical connection structure 400B may include a plurality of first portions 400n and a second portion 400w, the second portion 400w being vertically disposed above and electrically coupled to the plurality of first portions 400n, wherein the plurality of first portions 400n may be arranged laterally adjacent to each other and are respectively surrounded (e.g., enclosed) by a plurality of annular walls 300. For illustrative purposes, in Figure 29 and Figure 30 Only two first portions 400n are shown (e.g., 400n1 and 400n2), however, this disclosure is not limited thereto. The number of first portions 400n included in the vertical connection structure 400B can be two, three, or more, depending on the requirements and design specifications. This disclosure is not limited thereto.

[0156] For example, such as Figure 29 and Figure 30 As shown, the first portions 400n1 and 400n2 are completely surrounded (or completely enclosed) by corresponding annular walls 300, and in a vertical projection on the substrate 101, the first portions 400n1 and 400n2 are arranged adjacent to each other (e.g., offset from each other), wherein in the Z direction, the second portion 400w is simultaneously disposed above and extends further onto a portion of the sidewall of each of the first portions 400n1 and 400n2. In this case, the first portions 400n1 and 400n2 are electrically coupled to each other through the second portion 400w. The details, construction, and materials of the first portions 400n1 and 400n2 are the same as previously described in... Figures 1 to 12 The details, construction, and materials of the first part 400n described in the previous section are the same, and the details, construction, and materials of the second part 400w are the same as those previously described in the previous section. Figures 15 to 23The details, formation, and materials of the second portion 400w described in the middle are the same, and thus are not repeated here for simplicity. It is understood that all the annular walls 300 in the semiconductor device SD3 can be formed at the same time, and all the first portions 400n1 and 400n2 in the semiconductor device SD3 can be formed at the same time. In some embodiments, the second portion 400w of the vertical connection structure 400B is defined by the maximum distance between the outer sidewalls SWo300 of the annular walls 300 that laterally surround the first portion 400n of the vertical connection structure 400B.

[0157] In some embodiments, the first portion 400n (e.g., 400n1 and 400n2) and the second portion 400w of the vertical connection structure 400B are formed by different and independent steps (which can be referred to as a two-step process) according to a many-to-one architecture, where in Figure 29 In the cross-sectional view of FIG. 1G, the sidewalls of the vertical connection structure 400B have a stepped profile. Due to the formation process of the vertical connection structure 400B, the aspect ratio of the first portion 400n is reduced, making the manufacturing process of the vertical connection structure 400B easy and reliable. Due to the first portion 400n (which has a larger aspect ratio than the second portion 400w), the critical dimension of the vertical connection structure 400B at the front side (e.g., S101t) of the substrate 101 remains unchanged, thereby ensuring (or guaranteeing) the integration of the semiconductor device SD3; and due to the second portion 400w (which has a smaller aspect ratio than the first portion 400n), the contact resistance (Rc) of the semiconductor device SD3 can be reduced.

[0158] In addition, since the first portion 400n and the second portion 400w of the vertical connection structure 400B are formed in two steps, the thickness T101b of the substrate 101 can still be thick enough to achieve good heat dissipation and better warpage of the semiconductor device SD3. In embodiments of the present disclosure, since the first portion 400n is laterally surrounded by the annular wall 300 inside the interconnect 107, the metal features of the interconnect 107 can be well protected from moisture during the formation of the first portion 400n. In some embodiments, the vertical connection structure 400B can be used to transmit signals, ground power, or smaller power. Due to such an architecture (e.g., a many-to-one architecture), not only can signals, ground power, or smaller power be transmitted through the vertical connection structure 400B, but larger power can also be transmitted to the semiconductor device SD3 through the vertical connection structure 400B. The vertical connection structure 400B can be referred to as a through-substrate via or through-silicon via (TSV), a via, a through-hole, or a conductive pillar. In embodiments of the semiconductor device SD3, the cross-section of the annular wall 300 is in the form of a rectangular ring. However, the present disclosure is not limited thereto; alternatively, in a plan view, the cross-section of the annular wall 300 can be in the form of a circular ring, as shown in FIG. 1C, for example. Figure 40 Similarly, Figure 29 The bonding layer 110 in the semiconductor device SD3 of FIG. 1A can be replaced by the interconnect 107', as shown in FIG. 1B, for example. Figure 31 The semiconductor device SD4 of FIG. 1C.

[0159] In the above embodiments, the liner feature 410 of each first portion 400n (e.g., 400n1 and / or 400n2) in the vertical connection structure 400B still remains on and fully covers the sidewall SW420 and the end surface S420b of the corresponding conductive feature 420, as shown in FIG. 1A, for example. Figure 32 and Figure 35 However, the present disclosure is not limited thereto. In some alternative embodiments, the portion of the liner feature 410 of each first portion 400n (e.g., 400n1 and / or 400n2) in the vertical connection structure 400B that is initially disposed on the end surface S420b of the corresponding conductive feature 420 can be completely removed, as shown in FIG. 1B, for example. Figure 33For example, the end surface S420b of each corresponding conductive feature 420 is completely (or entirely) exposed by the liner feature 410, and the sidewall SW420 of each corresponding conductive feature 420 is completely (or entirely) covered by the liner feature 410. In this way, the electrical connection between the first portions 400n and the second portion 400w can be improved. In some other embodiments, the portion of the liner feature 410 of each first portion 400n (e.g., 400n1 and / or 400n2) in the vertical connection structure 400B that is initially disposed on the end surface S420b of the corresponding conductive feature 420 can be completely removed, and the portion of the liner feature 410 of each first portion 400n (e.g., 400n1 and / or 400n2) in the vertical connection structure 400B that is initially disposed on the sidewall SW420 of the corresponding conductive feature 420 can be partially removed, as shown in FIG. 4B. Figure 34 For example, the end surface S420b of each corresponding conductive feature 420 is completely (or entirely) exposed by the liner feature 410, and the sidewall SW420 of each corresponding conductive feature 420 is completely (or entirely) covered by the liner feature 410. In this way, the electrical connection between the first portions 400n and the second portion 400w can be improved. In some other embodiments, the portion of the liner feature 410 of each first portion 400n (e.g., 400n1 and / or 400n2) in the vertical connection structure 400B that is initially disposed on the end surface S420b of the corresponding conductive feature 420 can be completely removed, and the portion of the liner feature 410 of each first portion 400n (e.g., 400n1 and / or 400n2) in the vertical connection structure 400B that is initially disposed on the sidewall SW420 of the corresponding conductive feature 420 can be partially removed, as shown in FIG. 4B.

[0160] In the above embodiments, the centerline CL400w of the second portion 400w and the centerline CL400n of each first portion 400n (e.g., 400n1 and / or 400n2) in a vertical connection structure 400B are offset from each other, as shown in FIG. 4A. Figures 32 to 35 However, the present disclosure is not limited thereto. In some alternative embodiments, the centerline CL400w of the second portion 400w and the centerline CL400n of one of the first portions 400n in a vertical connection structure 400B are substantially aligned, not shown. That is, the second portion 400w and only one of the first portions 400n in a vertical connection structure 400B share a common centerline (not labeled).

[0161] The centerline CL400n of the first portion 400n can be the same distance D2 away from the centerline CL400w of the second portion 400w, as shown in FIG. 4A. Figures 32 to 35 On the other hand, the centerline CL400n of the first portion 400n can be different distances D2 and D3 away from the centerline CL400w of the second portion 400w, as shown in FIG. 4B. Figure 35 For example, the distance D3 is greater than the distance D2. Alternatively, the distance D3 can be less than the distance D2.

[0162] In semiconductor devices SD3 and SD4, only one vertical interconnect structure 400B appears. However, the number of vertical interconnect structures 400B can be one, two, three, or more than three, depending on requirements and design specifications. This disclosure is not limited to this.

[0163] Alternatively, in this disclosure, the semiconductor device may include one or more vertical connection structures 400A and one or more vertical connection structures 400B. In a non-limiting example, the semiconductor device (not shown) includes one vertical connection structure 400A and multiple vertical connection structures 400B. In another non-limiting example, the semiconductor device (not shown) includes multiple vertical connection structures 400A and one vertical connection structure 400B. In yet another non-limiting example, the semiconductor device includes one vertical connection structure 400A and one vertical connection structure 400B. Figure 36 A schematic cross-sectional view of a semiconductor device (e.g., SD5) according to some embodiments of this disclosure is shown. Figure 36 As shown, the semiconductor device SD5 may include a vertical connection structure 400A and a vertical connection structure 400B. The embodiments described are intended to provide further explanation but are not intended to limit the scope of this disclosure. Throughout the various views and illustrative embodiments of this disclosure, components similar to or substantially identical to those previously described will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated. In some embodiments, Figure 36 The semiconductor device SD5 is similar to Figure 23 (and simultaneous reference) Figure 22 The semiconductor device SD1 is different; in Figure 36 In the semiconductor device SD5, in addition to the vertical interconnect structure 400A, a vertical interconnect structure 400B is further employed. Details of the vertical interconnect structure 400B are already available in [the original text]. Figures 29 to 35 As described in the text, it will not be repeated here.

[0164] In some embodiments, for the semiconductor device SD5, the first portion 400n and the second portion 400w of the vertical connection structures 400A and 400B are formed in different and independent steps (which may be referred to as a two-step process), wherein in Figure 36In the cross-sectional view, the sidewalls of the vertical connection structures 400A and 400B have a ladder-like profile. Due to the formation process of the vertical connection structures 400A and 400B, the aspect ratio of the first portion 400n is reduced, making the manufacturing process of the vertical connection structures 400A and 400B easy and reliable. Due to the first portion 400n (which has a higher aspect ratio than the second portion 400w), the critical dimension of the vertical connection structures 400A and 400B at the front side (e.g., S101t) of the substrate 101 remains unchanged, thereby ensuring (or guaranteeing) the integration of the semiconductor device SD5; and due to the second portion 400w (which has a lower aspect ratio than the first portion 400n), the contact resistance (Rc) of the semiconductor device SD5 can be reduced.

[0165] In addition, due to the two-step formation of the first portion 400n and the second portion 400w of the vertical connection structures 400A and 400B, the thickness T101b of the substrate 101 can still be thick enough to obtain good heat dissipation and better warpage of the semiconductor device SD5. In the embodiments of the present disclosure, since the first portion 400n is laterally surrounded by the annular wall 300 inside the interconnect 107, the metal features of the interconnect 107 can be well protected from moisture during the formation of the first portion 400n. Due to such an architecture, signals, ground power or smaller power can be transmitted to the semiconductor device SD5 through the vertical connection structure 400A, while larger power can be transmitted to the semiconductor device SD5 through the vertical connection structure 400B. In some embodiments, the vertical connection structure 400B can also be used to transmit signals, ground power or smaller power. Similarly, Figure 36 The bonding layer 110 of the semiconductor device SD5 in

[0166] Figures 25 to 28 the modification (i.e., the variant) for the vertical connection structure 400A in Figures 32 to 35 the modification (i.e., the variant) for the vertical connection structure 400B in The present disclosure is not limited thereto.

[0167] In the above embodiments, the annular wall (e.g., 300) and the vertical connection structure (e.g., 400A and / or 400B) are arranged in a one-to-one architecture. However, the present disclosure is not limited thereto; alternatively, the annular wall (e.g., 300) and the vertical connection structure (e.g., 400A and / or 400B) can be arranged in a one-to-many architecture, referring to Figure 42 and Figure 43 the semiconductor device SD3' of Figure 42 and Figure 23As shown, an annular wall 300 encloses at least two vertical connection structures (e.g., 400A and / or 400B), for example, a first portion of the at least two vertical connection structures.

[0168] In some embodiments, the semiconductor devices SD1-SD5 and modified forms thereof can be further mounted on another external electronic component or circuit structure, such as a circuit structure, for example, a motherboard, a package substrate, a printed circuit board (PCB), a printed wiring board, and / or other carriers capable of carrying integrated circuits. Alternatively, the semiconductor devices SD1-SD5 and modified forms thereof can be an integrated Fan-Out (InFO) package, an InFO package with a Package-on-Package (PoP) structure, a chip-on-wafer-on-substrate (CoWoS) package, a flip chip package of InFO package, or similar package, or can be a part of an InFO package, an InFO package with a PoP structure, a CoWoS package, a flip chip package of InFO package, or similar package. The present disclosure is not limited thereto.

[0169] Figure 38 FIG. 1 shows a schematic cross-sectional view of an application of a semiconductor device (e.g., semiconductor devices SD1-SD5 and modified forms thereof) according to some embodiments of the present disclosure. Similar or substantially similar components as previously set forth will use the same reference numbers, and certain details or explanations (e.g., materials, formation processes, positioning configurations, electrical connections, etc.) of the same components will not be repeated.

[0170] Reference Figure 38In some embodiments, a component assembly SC is provided that includes a first component Cl and a second component C2 disposed on the first component Cl. The first component Cl can be or include a circuit structure such as a motherboard, a package substrate, another PCB, a wiring board, an interposer, and / or other carrier capable of carrying integrated circuits. In some embodiments, the second component C2 mounted on the first component Cl is similar to one of the semiconductor devices SDl to SD5 and their modifications. For example, one or more second components C2 (e.g., semiconductor devices SDl to SD5 and their modifications) can be electrically coupled to the first component Cl through a plurality of terminals CT. The terminals CT can be electrically conductive terminals. In some embodiments, an underfill UF is formed in a gap between the first component Cl and the second component C2 to cover the terminals CT at least laterally. Alternatively, the underfill UF is omitted. For example, the underfill UF can be any acceptable material such as a polymer, an epoxy, a molded underfill, or the like. In one embodiment, the underfill UF can be formed by underfill dispensing, a capillary flow process, or any other suitable method. Due to the underfill UF, the joint strength between the first component Cl and the second component C2 is enhanced.

[0171] According to some embodiments, a semiconductor device includes a substrate, interconnects, and a vertical connection structure. The substrate has a front side and a back side. The interconnects are disposed over the front side of the substrate. The vertical connection structure is embedded in the interconnects and through the substrate, and the vertical connection structure includes a first portion and a second portion. The first portion is embedded inside the interconnects and further extends into the substrate. The second portion is disposed in the substrate and extends from the back side to the first portion, the second portion being in contact with the first portion. An aspect ratio of the second portion is less than an aspect ratio of the first portion.

[0172] According to some embodiments, in the semiconductor device, the first portion is covered by the backside of the substrate, and the second portion is covered by the frontside of the substrate. According to some embodiments, in the semiconductor device, a first dimension of the first portion is smaller than a second dimension of the second portion along a direction perpendicular to a stacking direction of the first portion and the second portion. According to some embodiments, the semiconductor device further comprises: an annular wall disposed in the interconnect and laterally surrounding the first portion, wherein the second portion is vertically distanced from the annular wall. According to some embodiments, in the semiconductor device, in a vertical projection along the stacking direction of the first portion and the second portion, the first portion is defined by an innermost wall of the annular wall, and the second portion is defined by an outermost wall of the annular wall. According to some embodiments, in the semiconductor device, in the vertical projection along the stacking direction of the first portion and the second portion, the annular wall has a ring shape continuously surrounding the first portion. According to some embodiments, the semiconductor device further comprises: an additional vertical connection structure embedded to the interconnect and penetrating the substrate, the additional vertical connection structure laterally positioned beside the vertical connection structure and comprising: a plurality of third portions embedded to the interconnect and further extending into the substrate; and a fourth portion disposed in the substrate and extending from the backside to the plurality of third portions, the fourth portion in contact with the plurality of third portions, wherein a height-to-width ratio of each of the plurality of third portions is greater than a height-to-width ratio of the fourth portion. According to some embodiments, in the semiconductor device, the plurality of third portions are covered by the backside of the substrate, and the fourth portion is covered by the frontside of the substrate. According to some embodiments, in the semiconductor device, a third dimension of each of the plurality of third portions is smaller than a fourth dimension of the fourth portion along a direction perpendicular to a stacking direction of the plurality of third portions and the fourth portion. According to some embodiments, the semiconductor device further comprises: a plurality of additional annular walls disposed in the interconnect and laterally surrounding the plurality of third portions, wherein the fourth portion is vertically distanced from the plurality of additional annular walls. According to some embodiments, in the semiconductor device, in a vertical projection along the stacking direction of the plurality of third portions and the fourth portion, each of the plurality of third portions is defined by an innermost wall of a corresponding one of the plurality of additional annular walls, and the fourth portion is defined by a maximum distance between outermost walls of the plurality of additional annular walls. According to some embodiments, in the semiconductor device, in the vertical projection along the stacking direction of the plurality of third portions and the fourth portion, each of the plurality of additional annular walls has a ring shape continuously surrounding a corresponding one of the plurality of third portions.According to some embodiments, in the semiconductor device, the first portion includes a plurality of first portions arranged laterally adjacent to each other, and the plurality of first portions are electrically coupled to each other through the second portion.

[0173] According to some embodiments, a semiconductor device includes a substrate, an interconnect, a device layer, at least one first vertical connection structure, and a metal feature. The interconnect is disposed above a substrate. The device layer is disposed between the substrate and the interconnect. The at least one first vertical connection structure is embedded in the interconnect, electrically coupled to the interconnect, and penetrates the substrate, and the at least one first vertical connection structure includes at least one first narrow portion and a first wide portion. The at least one first narrow portion is embedded in the interconnect and further extends into the substrate. The first wide portion is disposed in the substrate and exposed by the substrate, and the first wide portion contacts the at least one first narrow portion. An aspect ratio of the at least one first narrow portion is greater than an aspect ratio of the first wide portion. The metal feature is disposed above the at least one first vertical connection structure and electrically coupled to the at least one first vertical connection structure, and the substrate is between the metal feature and the device layer.

[0174] According to some embodiments, in the semiconductor device, the at least one first narrow portion includes a plurality of first narrow portions arranged laterally adjacent to each other, and the at least one first ring-shaped wall includes a plurality of first ring-shaped walls respectively surrounding the plurality of first narrow portions and spaced apart therefrom, wherein the first wide portion is spaced apart from the plurality of first ring-shaped walls and electrically coupled to the plurality of first narrow portions. According to some embodiments, the semiconductor device further includes: a bonding layer disposed above and electrically coupled to the at least one first vertical connection structure, the substrate is between the bonding layer and the device layer, and the metal feature is included in the bonding layer; or an additional interconnect disposed above and electrically coupled to the at least one first vertical connection structure, the substrate is between the additional interconnect and the device layer, and the metal feature is included in the additional interconnect. According to some embodiments, the semiconductor device further includes: at least one second vertical connection structure embedded in and electrically coupled to the interconnect and penetrating the substrate, the at least one second vertical connection structure is laterally beside the at least one first vertical connection structure and includes: a plurality of second narrow portions embedded in the interconnect and further extending into the substrate; and a second wide portion disposed in the substrate and exposed by the substrate, the second wide portion contacts the plurality of second narrow portions, wherein an aspect ratio of each of the plurality of second narrow portions is greater than an aspect ratio of the second wide portion.

[0175] According to some embodiments, a method of fabricating a semiconductor device includes the steps of: providing a substrate having a front side and a back side; disposing an interconnect over the front side of the substrate; forming an annular wall inside the interconnect; forming a first portion of a vertical connection structure in the interconnect, the first portion of the vertical connection structure further extending into the substrate, the first portion of the vertical connection structure being surrounded by and spaced apart from the annular wall, the first portion of the vertical connection structure being electrically coupled to the interconnect; forming a second portion of the vertical connection structure in the substrate, the second portion extending from a portion of the first portion inside the substrate to the back side of the substrate, the second portion connecting and being electrically coupled to the first portion, wherein an aspect ratio of the second portion is less than an aspect ratio of the first portion; and disposing a metal feature over the substrate to be electrically coupled to the second portion of the vertical connection structure.

[0176] According to some embodiments, in the method, wherein forming the annular wall inside the interconnect includes forming a plurality of annular walls in the interconnect, the plurality of annular walls being laterally adjacent to each other, and wherein forming the first portion of the vertical connection structure includes forming a plurality of first portions in the interconnect that further extend into the substrate, the plurality of first portions being respectively surrounded by and spaced apart from the plurality of annular walls, the plurality of first portions being electrically coupled to the interconnect, the second portion connecting to and being electrically coupled to the plurality of first portions to form the vertical connection structure. According to some embodiments, in the method, wherein forming the annular wall inside the interconnect further includes forming a plurality of additional annular walls adjacent to the annular wall inside the interconnect, the plurality of additional annular walls being laterally adjacent to each other, wherein forming the first portion of the vertical connection structure further includes forming a plurality of third portions of an additional vertical connection structure in the interconnect that further extend into the substrate, the plurality of third portions of the additional vertical connection structure being respectively surrounded by and spaced apart from the plurality of additional annular walls, the plurality of third portions of the additional vertical connection structure being electrically coupled to the interconnect, and wherein forming the second portion of the vertical connection structure further includes forming a fourth portion of the additional vertical connection structure in the substrate, the fourth portion extending from the plurality of third portions inside the substrate to the back side of the substrate, the fourth portion connecting to and being electrically coupled to the plurality of third portions to form the additional vertical connection structure, wherein an aspect ratio of the fourth portion is less than an aspect ratio of each of the plurality of third portions.

[0177] Finally, it should be noted that: the above embodiments are used to illustrate the technical solutions of the present application, but not limited to them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate having a front side and a back side; interconnects disposed over the front side of the substrate; and a vertical connection structure embedded into the interconnects and penetrating the substrate, and comprising: a first portion embedded into the interconnects and further extending into the substrate; and a second portion disposed in the substrate and extending from the back side to the first portion, the second portion being in contact with the first portion, wherein an aspect ratio of the second portion is less than an aspect ratio of the first portion. wherein a first dimension of the first portion is less than a second dimension of the second portion along a direction perpendicular to a stacking direction of the first portion and the second portion. Further comprising:

2. The semiconductor device according to claim 1, wherein an annular wall disposed in the interconnects and laterally surrounding the first portion, 3. The semiconductor device according to claim 1, wherein wherein the second portion is vertically distanced from the annular wall. Further comprising: an additional vertical connection structure embedded into the interconnects and penetrating the substrate, the additional vertical connection structure being laterally positioned alongside the vertical connection structure and comprising:

4. The semiconductor device according to claim 1, wherein a plurality of third portions embedded into the interconnects and further extending into the substrate; and a fourth portion disposed in the substrate and extending from the back side to the plurality of third portions, the fourth portion being in contact with the plurality of third portions, wherein an aspect ratio of each of the plurality of third portions is greater than an aspect ratio of the fourth portion. Further comprising: a plurality of additional annular walls disposed in the interconnects and laterally surrounding the plurality of third portions, 5. The semiconductor device according to claim 4, wherein wherein the fourth portion is vertically distanced from the plurality of additional annular walls. wherein the first portion comprises a plurality of first portions arranged laterally adjacent to each other, wherein the plurality of first portions are electrically coupled to each other through the second portion.

6. The semiconductor device according to claim 1, wherein Comprising: a substrate; 7. A semiconductor device, characterized by comprising: interconnects disposed over the substrate; a device layer disposed between the substrate and the interconnects; at least one first annular wall disposed within the device layer over the substrate and further extending into the interconnects; at least one first vertical connection structure embedded into the interconnects and electrically coupled thereto, and penetrating the substrate, the at least one first vertical connection structure comprising: at least one first narrow portion embedded into the interconnects and further extending into the substrate; and a first wide portion disposed in the substrate and exposed by the substrate, the first wide portion being in contact with the at least one first narrow portion, wherein an aspect ratio of the at least one first narrow portion is greater than an aspect ratio of the first wide portion; and a metal feature disposed over and electrically coupled to the at least one first vertical connection structure, the substrate being disposed between the at least one first vertical connection structure and the device layer. wherein the at least one first narrow portion comprises a plurality of first narrow portions arranged laterally adjacent to each other, and the at least one first annular wall comprises a plurality of first annular walls respectively surrounding and spaced apart from the plurality of first narrow portions, wherein the first wide portion is spaced apart from the plurality of first annular walls, and the first wide portion is electrically coupled to the plurality of first narrow portions.

8. The semiconductor device according to claim 7, wherein Further comprising: ​ 9. The semiconductor device according to claim 7, wherein ​ a bonding layer disposed on and electrically coupled with the at least one first vertical connection structure, the substrate being between the bonding layer and the device layer, wherein the metal feature is included in the bonding layer; or additional interconnects disposed on and electrically coupled with the at least one first vertical connection structure, the substrate being between the additional interconnects and the device layer, wherein the metal feature is included in the additional interconnects.

10. The semiconductor device according to claim 7, wherein Further comprising: at least one second vertical connection structure embedded in and electrically coupled with the interconnects and penetrating the substrate, the at least one second vertical connection structure being laterally alongside the at least one first vertical connection structure and including: a plurality of second narrow portions embedded in the interconnects and further extending into the substrate; and a second wide portion disposed in and exposed by the substrate, the second wide portion contacting the plurality of second narrow portions, wherein a height-to-width ratio of each of the plurality of second narrow portions is greater than a height-to-width ratio of the second wide portion.

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