Voltage regulator and DCDC converter

Abstract

The utility model discloses a voltage regulator and a DCDC converter, and belongs to the technical field of DCDC. The voltage regulator comprises a first regulator, the first regulator comprises a first input voltage pin and a first high-voltage MOS tube, a source electrode of the first high-voltage MOS tube is connected with the first input voltage pin, and a drain electrode of the first high-voltage MOS tube is connected with a second input voltage pin of the chip; the second regulator comprises a bias voltage pin, a second high-voltage MOS tube and a third high-voltage MOS tube, the bias voltage pin is fixedly connected to a corresponding output voltage pin of the DCDC converter, a drain electrode of the second high-voltage MOS tube is connected with the bias voltage pin, a drain electrode of the third high-voltage MOS tube is connected with the first regulator and a second input voltage pin, and a drain electrode of the second high-voltage MOS tube is connected with a drain electrode of the third high-voltage MOS tube. And the source electrode of the third high-voltage MOS tube is connected with the source electrode of the second high-voltage MOS tube. The voltage regulator is small in voltage drop loss.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of DCDC, and particularly relates to a voltage regulator and a DCDC converter. BACKGROUND

[0002] For a DCDC converter with low power consumption demand, a double-input voltage regulator needs to be arranged on a circuit board of the DCDC converter to reduce power consumption of the DCDC converter. In the related art, in the case of supplying power to a chip based on an input voltage of one regulator, to avoid the chip from leaking electricity to another regulator, an isolation diode needs to be arranged in the another regulator, but the isolation diode will cause a voltage drop, and the voltage drop loss is large; and the connection mode of an input voltage pin based on the another regulator needs to be adjusted according to the high and low of a VOUT voltage, which is complicated to operate. CONTENT OF THE UTILITY MODEL

[0003] The application aims to at least solve one of the technical problems in the prior art. To this end, the application provides a voltage regulator and a DCDC converter, which reduces voltage drop loss and avoids frequent changes of a bias voltage pin, and is high in convenience.

[0004] In a first aspect, the application provides a voltage regulator, which is arranged on a circuit board of a DCDC converter, and the DCDC converter is arranged between a power supply and a chip; the voltage regulator comprises:

[0005] a first regulator, which comprises a first input voltage pin and a first high-voltage MOS tube, the first input voltage pin is used to receive a first voltage, a source of the first high-voltage MOS tube is connected with the first input voltage pin, and a drain of the first high-voltage MOS tube is connected with a second input voltage pin of the chip;

[0006] a second regulator, which comprises a bias voltage pin, a second high-voltage MOS tube and a third high-voltage MOS tube, the bias voltage pin is used to receive a second voltage, the bias voltage pin is fixedly connected with a corresponding output voltage pin of the DCDC converter, a drain of the second high-voltage MOS tube is connected with the bias voltage pin, a drain of the third high-voltage MOS tube is connected with the first regulator and the second input voltage pin respectively, and a source of the third high-voltage MOS tube is connected with a source of the second high-voltage MOS tube;

[0007] The second adjuster is configured to be opened and the first adjuster is configured to be closed when the deviation between the second voltage and the target voltage threshold is within the target threshold range; the first adjuster is configured to be opened and the second adjuster is configured to be closed when the deviation between the second voltage and the target voltage threshold is not within the target threshold range.

[0008] The voltage adjuster provided by the embodiment of the present application can selectively open the first adjuster or the second adjuster according to the magnitude of the second voltage, so as to supply power to the chip based on the opened adjuster, thereby meeting the low-power consumption requirement of the DCDC converter, and without separately arranging an isolation component in the second adjuster, the bidirectional isolation between the bias voltage pin and the second input voltage pin can be realized based on the structure of the second adjuster, thereby reducing the voltage drop loss; and by arranging the bias voltage pin to be fixedly connected with the output voltage pin, the bias voltage pin can receive a higher voltage, thereby avoiding frequent changes of the bias voltage pin and improving convenience.

[0009] The voltage adjuster of one embodiment of the present application, the drain and the source of the first high-voltage MOS tube are connected in parallel with a first body diode.

[0010] The voltage adjuster of one embodiment of the present application, the first adjuster comprises:

[0011] The first switch has one end connected with the source of the first high-voltage MOS tube and the other end connected with the gate of the first high-voltage MOS tube.

[0012] The voltage adjuster of one embodiment of the present application, the first adjuster comprises:

[0013] The first amplifier has a non-inverting input end for receiving a third voltage and an inverting input end for receiving a feedback voltage corresponding to the circuit where the voltage adjuster is located, and the output end of the first amplifier is connected with the other end of the first switch and the gate of the first high-voltage MOS tube, respectively.

[0014] The voltage adjuster of one embodiment of the present application, the drain and the source of the second high-voltage MOS tube are connected in parallel with a second body diode, and the drain and the source of the third high-voltage MOS tube are connected in parallel with a third body diode.

[0015] The voltage adjuster of one embodiment of the present application, the second adjuster comprises:

[0016] A second switch, one end of the second switch is connected with the gate of the second high-voltage MOS tube, and the other end of the second switch is connected with the source of the second high-voltage MOS tube.

[0017] The voltage regulator of one embodiment of the application comprises:

[0018] A second amplifier, the non-inverting input end of the second amplifier is used for receiving a fourth voltage, the inverting input end of the second amplifier is used for receiving a feedback voltage corresponding to a circuit where the voltage regulator is located, and the output end of the second amplifier is connected with the gate of the second high-voltage MOS tube.

[0019] The voltage regulator of one embodiment of the application comprises:

[0020] A second clamping circuit, the third port of the second clamping circuit is connected between the source of the second high-voltage MOS tube and the source of the third high-voltage MOS tube, the fourth port of the second clamping circuit is grounded, and the output end of the second clamping circuit is connected with the second amplifier.

[0021] The voltage regulator of one embodiment of the application comprises:

[0022] A third switch, the first end of the third switch is connected with the gate of the third high-voltage MOS tube, and the second end of the third switch is connected with the source of the second high-voltage MOS tube.

[0023] The third end of the third switch is connected with the gate of the second high-voltage MOS tube.

[0024] Or,

[0025] The third end is connected with the output end of the second clamping circuit.

[0026] In a second aspect, the application provides a DCDC converter, which is arranged between a power supply and a chip; the DCDC converter comprises:

[0027] A circuit board;

[0028] The voltage regulator as described in the first aspect is arranged on the circuit board.

[0029] The one or more technical solutions described above in the embodiments of the application have at least one of the following technical effects:

[0030] By configuring the first adjuster and the second adjuster to be opened or closed according to the size relationship between the second voltage and the target voltage threshold, the first adjuster or the second adjuster can be selectively opened according to the size of the second voltage to supply power to the chip based on the opened adjuster, the low-power consumption requirement of the DCDC converter is met, and without separately arranging an isolation component in the second adjuster, bidirectional isolation between the bias voltage pin and the second input voltage pin can be realized based on the structure of the second adjuster, the voltage drop loss is reduced; and by arranging the bias voltage pin to be fixedly connected with the output voltage pin, the bias voltage pin can receive a higher voltage, frequent change of the bias voltage pin is avoided, and convenience is higher.

[0031] Further, by arranging the first body diode to be reversed between the first input voltage pin and the second input voltage pin, in the case that the first adjuster is closed, the gate of the first high-voltage MOS tube can be connected to the first input voltage pin, so that no leakage occurs between the first input voltage pin and the second input voltage pin.

[0032] Still further, in the case that the second adjuster is opened, the first end of the third switch is connected to the third end, by arranging the third end to be connected to the gate of the second high-voltage MOS tube, the second body diode and the third body diode can be reversely connected in series as a new PMOS tube; or by arranging the third end to be connected to the output end of the second clamping circuit, the third body diode is turned on, so that in the case that the second adjuster is opened, the third body diode remains turned on, the voltage drop from the bias voltage pin to the second input voltage pin is reduced, and energy waste is reduced.

[0033] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0034] The above and / or additional aspects and advantages of the application will become apparent and be readily appreciated from the description of the embodiments, which follows, including the accompanying drawings.

[0035] Figure 1 is a structural schematic diagram of a DCDC converter provided by an embodiment of the application;

[0036] Figure 2 is one of structural schematic diagrams of a voltage adjuster provided by an embodiment of the application;

[0037] Figure 3 is another one of structural schematic diagrams of a voltage adjuster provided by an embodiment of the application;

[0038] Figure 4 is a third one of structural schematic diagrams of a voltage adjuster provided by an embodiment of the application.

[0039] Reference signs:

[0040] Voltage regulator 100; first regulator 110; second regulator 120; detection control circuit 130;

[0041] First input voltage pin VIN; first high-voltage MOS tube PM1; second input voltage pin VCC;

[0042] Bias voltage pin VBIAS; second high-voltage MOS tube PM2; third high-voltage MOS tube PM3;

[0043] Output voltage pin VOUT; first body diode D1; first switch S_VIN; first amplifier OP_VIN;

[0044] First clamping circuit VCLP1; second body diode D2; third body diode D3; second switch S_BIAS2;

[0045] Second amplifier OP_BIAS; second clamping circuit VCLP2; third switch S_BIAS3; first resistor RH;

[0046] Second resistor RL; target capacitor CO. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0048] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a category and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in a "or" relationship.

[0049] 1. In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0050] 2. In the description of the present application, "a plurality of" means two or more.

[0051] The embodiment of the present application provides a voltage regulator 100.

[0052] It should be noted that, as shown in the figure, Figure 1 The voltage regulator 100 can be arranged on the circuit board of the DCDC converter.

[0053] The DCDC converter can be arranged between the power supply and the chip, and by arranging the voltage regulator 100, the voltage required by the chip can be provided to the chip based on the voltage regulator 100.

[0054] The voltage regulator 100 provided by the embodiment of the present application can be implemented on a BCD (Bipolar-CMOS-DMOS) process or other processes.

[0055] As shown in the figure, Figure 2 In some embodiments, the voltage regulator 100 includes a first regulator 110 and a second regulator 120.

[0056] In this embodiment, the first regulator 110 includes a first input voltage pin VIN and a first high-voltage MOS tube PM1.

[0057] The first input voltage pin VIN is used to receive a first voltage, wherein the first voltage can be determined based on the power supply accessed by the DCDC converter.

[0058] The first regulator 110 is connected with a second input voltage pin VCC of the chip, for example, the first input voltage pin VIN can be connected with the second input voltage pin VCC through the first high-voltage MOS tube PM1.

[0059] The second input voltage pin VCC can be connected with the internal power supply of the chip to supply power, and the voltage required by the chip is generally 3-5V.

[0060] The source of the first high-voltage MOS tube PM1 is connected with the first input voltage pin VIN, and the drain of the first high-voltage MOS tube PM1 is connected with the second input voltage pin VCC of the chip.

[0061] The VGS withstand voltage between the gate and the source of the high-voltage MOS tube is small, that is, the maximum voltage that can be applied between the gate and the source is small, for example, the VGS withstand voltage is generally about 5V.

[0062] The VGD withstand voltage between the gate and the drain of the high-voltage MOS tube, and the VDS withstand voltage between the drain and the source are large, that is, the maximum voltage that can be applied between the gate and the drain is large, and the maximum voltage that can be applied between the drain and the source is large, for example, the VGD withstand voltage and the VDS withstand voltage are generally much higher than 5V, and can be 12V, 24V, 30V or 40V, etc.

[0063] In the case where the first regulator 110 works, the external power supply can supply power to the second input voltage pin VCC through the first input voltage pin VIN to supply power to the chip.

[0064] The second regulator 120 includes a bias voltage pin VBIAS, a second high-voltage MOS tube PM2 and a third high-voltage MOS tube PM3.

[0065] The bias voltage pin VBIAS is used to receive a second voltage, wherein the second voltage can be determined based on the power supply accessed by the DCDC converter.

[0066] The bias voltage pin VBIAS can be fixedly connected to the corresponding output voltage pin VOUT of the DCDC converter, so that the bias voltage pin VBIAS can receive a higher voltage.

[0067] The drain of the second high-voltage MOS tube PM2 is connected to the bias voltage pin VBIAS.

[0068] The drain of the third high-voltage MOS tube PM3 is connected to the first regulator 110 and the second input voltage pin VCC respectively, and the source of the third high-voltage MOS tube PM3 is connected to the source of the second high-voltage MOS tube PM2.

[0069] In the case where the second regulator 120 works, the external power supply can supply power to the second input voltage pin VCC through the bias voltage pin VBIAS to supply power to the chip.

[0070] In the case where the deviation between the second voltage and the target voltage threshold is within the target threshold range, the first regulator 110 is configured to be closed, and the second regulator 120 is configured to be opened.

[0071] The target voltage threshold can be determined based on the voltage required by the chip, for example, in the case where the voltage required by the chip is 5V, the target voltage threshold can be determined as 5V.

[0072] The target threshold range can be customized by a user, for example, the target threshold range can be (-1, 1), or can be other ranges, which are not limited in the present application.

[0073] In a case where the deviation between the second voltage and the target voltage threshold exceeds the target threshold range, the first adjuster 110 is configured to be opened, and the second adjuster 120 is configured to be closed.

[0074] For example, the target voltage threshold can be set to 5V, in a case where the second voltage is 24V, the second voltage is much greater than the target voltage threshold, the first adjuster 110 is opened, and the second adjuster 120 is closed, the voltage input to the chip is adjusted by the first adjuster 110; in a case where the second voltage is 5V, the second voltage is near the target voltage threshold, the first adjuster 110 is closed, and the second adjuster 120 is opened, the voltage input to the chip is adjusted by the second adjuster 120.

[0075] In actual implementation, different enable signals can be generated based on the size relationship between the second voltage and the target voltage threshold, to control the working states of the first adjuster 110 and the second adjuster 120 respectively.

[0076] In the present application, the voltage resistance characteristic of the MOS tube under the BCD process is utilized, so that the bias voltage pin VBIAS can be fixedly connected to the output voltage pin VOUT to receive a higher voltage, avoiding frequent changes of the bias voltage pin VBIAS connection method.

[0077] In a case where the first adjuster 110 is opened and the second adjuster 120 is closed, based on the second high-voltage MOS tube PM2 and the third high-voltage MOS tube PM3 arranged back-to-back in the second adjuster 120, the bidirectional isolation between the bias voltage pin VBIAS and the second input voltage pin VCC can be realized without separately arranging an isolation device, avoiding the case of current leakage from the second input voltage pin VCC to the bias voltage pin VBIAS, and reducing the voltage drop loss.

[0078] In a case where the first adjuster 110 is closed and the second adjuster 120 is opened, the voltage at the first input voltage pin VIN is higher than the voltage at the output voltage pin VOUT, avoiding the case of current leakage from the second input voltage pin VCC to the first input voltage pin VIN.

[0079] According to the voltage regulator 100 provided in the embodiment of the present application, by configuring the first regulator 110 and the second regulator 120 to be opened or closed according to the size relationship between the second voltage and the target voltage threshold, the first regulator 110 or the second regulator 120 can be selectively opened according to the size of the second voltage, so as to supply power to the chip based on the opened regulator, thereby meeting the low-power consumption requirement of the DCDC converter, and without separately arranging an isolation component in the second regulator 120, the bidirectional isolation between the bias voltage pin VBIAS and the second input voltage pin VCC can be realized based on the structure of the second regulator 120, thereby reducing the voltage drop loss; and by arranging the bias voltage pin VBIAS to be fixedly connected with the output voltage pin VOUT, the bias voltage pin VBIAS can receive a higher voltage, thereby avoiding frequent changes of the bias voltage pin VBIAS, and the convenience is higher.

[0080] As shown in Figure 4 In some embodiments, the voltage regulator 100 can further include a detection control circuit 130.

[0081] In this embodiment, one input end of the detection control circuit 130 is connected with the bias voltage pin VBIAS.

[0082] Another input end of the detection control circuit 130 is used to receive a target voltage threshold.

[0083] One output end of the detection control circuit 130 is connected with the first regulator 110, and is used to output a first enable signal EN_VIN.

[0084] Another output end of the detection control circuit 130 is connected with the second regulator 120, and is used to output a second enable signal EN_VBIAS.

[0085] The detection control circuit 130 can output the enable signals to the first regulator 110 and the second regulator 120 according to the size relationship between the second voltage at the bias voltage pin VBIAS and the target voltage threshold.

[0086] For example, in the case where it is determined that the deviation between the second voltage and the target voltage threshold is within the target threshold range, the detection control circuit 130 outputs: EN_VIN=LO, EN_VBIAS=HI, that is, the first enable signal EN_VIN is at a low level, and the second enable signal EN_VBIAS is at a high level, so as to make the first regulator 110 closed and the second regulator 120 opened.

[0087] In a case where the deviation between the second voltage and the target voltage threshold is not within the target threshold range, the detection control circuit 130 outputs: EN_VIN=HI, EN_VBIAS=LO, i.e., the first enable signal EN_VIN is high, and the second enable signal EN_VBIAS is low, so as to enable the first regulator 110 and disable the second regulator 120.

[0088] It can be understood that EN_VBIAS and EN_VIN cannot be high at the same time, i.e., at the current moment, one of the first regulator 110 and the second regulator 120 is in an open state, and the other is in a closed state.

[0089] As shown in FIG. 1, Figure 2 and Figure 3 In some embodiments, a first body diode D1 is connected in parallel between the drain and the source of the first high-voltage MOS tube PM1.

[0090] In this embodiment, the direction of the first body diode D1 can be from the drain of the first high-voltage MOS tube PM1 to the source, i.e., the positive electrode of the first body diode D1 is connected to the drain of the first high-voltage MOS tube PM1, and the negative electrode of the first body diode D1 is connected to the source of the first high-voltage MOS tube PM1.

[0091] In this embodiment, the first body diode D1 connected in parallel between the drain and the source of the first high-voltage MOS tube PM1 can prevent the first high-voltage MOS tube PM1 from bearing a reverse voltage in a wrong state, thereby protecting the first high-voltage MOS tube PM1 from being damaged.

[0092] As shown in FIG. 1, Figure 2 In some embodiments, the first regulator 110 can include a first switch S_VIN.

[0093] In this embodiment, one end A of the first switch S_VIN is connected to the source of the first high-voltage MOS tube PM1, and the other end B of the first switch S_VIN can also be connected to the first input voltage pin VIN. In a case where the first enable signal EN_VIN is high, the first switch S_VIN can be connected to “0”, i.e., the first switch S_VIN is disconnected; in a case where the first enable signal EN_VIN is low, the first switch S_VIN is closed.

[0094] The other end of the first switch S_VIN is connected to the gate of the first high-voltage MOS tube PM1.

[0095] In a case where the first adjuster 110 is closed, the first switch S_VIN is in a closed state, the gate of the first high-voltage MOS PM1 is connected to the first input voltage pin VIN, so that the first body diode D1 is closed, and only the first body diode D1 (and is a reverse diode) exists between the first input voltage pin VIN and the second input voltage pin VCC, the first voltage received by the first input voltage pin VIN is higher than the voltage at the second input voltage pin VCC, and no leakage occurs from the first input voltage pin VIN to the second input voltage pin VCC.

[0096] In some embodiments, the first adjuster 110 can include a first amplifier OP_VIN.

[0097] In this embodiment, as shown in Figure 2 The non-inverting input terminal of the first amplifier OP_VIN is configured to receive a third voltage VR_VIN, where the magnitude of the third voltage can be customized by a user or can be determined based on the power supply to which the DC converter is connected, for example, the third voltage can be 1V or other values, which are not limited in the present application.

[0098] The inverting input terminal of the first amplifier OP_VIN is configured to receive a feedback voltage VFB corresponding to the circuit in which the voltage adjuster 100 is located, and the feedback voltage is used to represent the magnitude of the voltage output by the voltage adjuster 100. The greater the voltage output by the voltage adjuster 100, the greater the feedback voltage. The smaller the voltage output by the voltage adjuster 100, the smaller the feedback voltage.

[0099] The output terminal of the first amplifier OP_VIN is connected to the other end of the first switch S_VIN and the gate of the first high-voltage MOS PM1, respectively.

[0100] In a case where the third voltage is greater than the feedback voltage, the first amplifier OP_VIN outputs a high-level signal; in a case where the third voltage is less than the feedback voltage, the first amplifier OP_VIN outputs a low-level signal.

[0101] One end of the first amplifier OP_VIN can be configured to receive a first enable signal EN_VIN, and the other end of the first amplifier OP_VIN can be grounded.

[0102] In a case where the first enable signal EN_VIN is low, the first amplifier OP_VIN does not work, and the first amplifier OP_VIN outputs high resistance; in a case where the first enable signal EN_VIN is high, the first amplifier OP_VIN works.

[0103] In some embodiments, the first adjuster 110 can include a first clamping circuit VCLP1.

[0104] In this embodiment, the first port of the first clamping circuit VCLP1 is connected with the first input voltage pin VIN for receiving a first voltage.

[0105] The second port of the first clamping circuit VCLP1 is grounded.

[0106] The output end of the first clamping circuit VCLP1 is connected with the first amplifier OP_VIN for providing a bias voltage to the first amplifier OP_VIN.

[0107] In actual execution, the voltage received by the first clamping circuit VCLP1 is VIN, and the voltage output by the first clamping circuit VCLP1 is VP1, wherein VP1≥VIN-5V.

[0108] According to the voltage regulator 100 provided in the embodiments of the present application, by arranging the first body diode D1 in reverse between the first input voltage pin VIN and the second input voltage pin VCC, in the case that the first regulator 110 is closed, the gate of the first high-voltage MOS PM1 can be connected to the first input voltage pin VIN, so that the leakage between the first input voltage pin VIN and the second input voltage pin VCC will not occur.

[0109] In some embodiments, the second body diode D2 is connected in parallel between the drain and the source of the second high-voltage MOS PM2.

[0110] In this embodiment, the direction of the second body diode D2 can be from the drain of the second high-voltage MOS PM2 to the source, that is, the positive electrode of the second body diode D2 is connected with the drain of the second high-voltage MOS PM2, and the negative electrode of the second body diode D2 is connected with the source of the second high-voltage MOS PM2.

[0111] In some embodiments, the third body diode D3 is connected in parallel between the drain and the source of the third high-voltage MOS PM3.

[0112] In this embodiment, the direction of the third body diode D3 can be from the drain of the third high-voltage MOS PM3 to the source, that is, the positive electrode of the third body diode D3 is connected with the drain of the third high-voltage MOS PM3, and the negative electrode of the third body diode D3 is connected with the source of the third high-voltage MOS PM3.

[0113] In some embodiments, the second regulator 120 can include a second switch S_BIAS2.

[0114] In this embodiment, one end C of the second switch S_BIAS2 is connected with the gate GT2 of the second high-voltage MOS PM2, and the other end D of the second switch S_BIAS2 is connected with the source of the second high-voltage MOS PM2.

[0115] With the second switch S_BIAS2 in the closed state, the second body diode D2 is configured to be off.

[0116] The second switch S_BIAS2 can receive the second enable signal EN_BIAS, which can control the opening and closing state of the second switch S_BIAS2.

[0117] When the second enable signal is low, the second switch S_BIAS2 is closed; when the second enable signal is high, the second switch S_BIAS2 is connected to "0", that is, the second switch S_BIAS2 is open.

[0118] like Figure 2 As shown, when the second switch S_BIAS2 is closed, the gate GT2 of the second high-voltage MOSFET PM2 can be connected to the VMID pin, causing the second body diode D2 to be short-circuited and turned off.

[0119] In some embodiments, the second adjuster 120 may include a second amplifier OP_BIAS.

[0120] In this embodiment, the non-inverting input of the second amplifier OP_BIAS is used to receive the fourth voltage VR_BIAS. The magnitude of the fourth voltage can be user-defined or determined based on the power supply connected to the DC-DC converter. For example, the fourth voltage can be 1V or 1.3V, etc. This application does not limit it.

[0121] The inverting input of the second amplifier OP_BIAS is used to receive the feedback voltage corresponding to the circuit where the voltage regulator 100 is located.

[0122] The output of the second amplifier OP_BIAS is connected to the gate GT2 of the second high-voltage MOSFET PM2.

[0123] When the fourth voltage is greater than the feedback voltage, the second amplifier OP_BIAS outputs a high-level signal; when the fourth voltage is less than the feedback voltage, the second amplifier OP_BIAS outputs a low-level signal.

[0124] In some embodiments, the second adjuster 120 may include a second clamping circuit VCLP2.

[0125] In this embodiment, the third port of the second clamping circuit VCLP2 is connected between the source of the second high-voltage MOSFET PM2 and the source of the third high-voltage MOSFET PM3.

[0126] The fourth port of the second clamping circuit VCLP2 is grounded.

[0127] The output end of the second clamping circuit VCLP2 is connected with the second amplifier OP_BIAS, for providing a bias voltage to the second amplifier OP_BIAS.

[0128] In actual execution, the voltage received by the second clamping circuit VCLP2 is VMID, and the voltage output by the second clamping circuit VCLP2 is VP2, wherein VP2≥VMID-5V.

[0129] In some embodiments, the second adjuster 120 can include a third switch S_BIAS3.

[0130] In this embodiment, the first end E of the third switch S_BIAS3 is connected with the gate GT3 of the third high-voltage MOS PM3, and the second end F of the third switch S_BIAS3 is connected with the source of the second high-voltage MOS PM2.

[0131] The third end VON of the third switch S_BIAS3 can be connected with the gate GT2 of the second high-voltage MOS PM2, or can be connected with the output end of the second clamping circuit VCLP2.

[0132] The third switch S_BIAS3 can receive a second enable signal EN_BIAS, in the case that the second enable signal is low, the third switch S_BIAS3 is closed, the third switch S_BIAS3 is connected to "0", that is, the first end and the second end of the third switch S_BIAS3 are connected, the gate GT3 of the third high-voltage MOS PM3 is connected to VMID, so that the third body diode D3 is closed.

[0133] In the case that the second enable signal is high, the second switch S_BIAS2 is opened, the third switch S_BIAS3 is closed, the third switch S_BIAS3 is connected to "1", that is, the first end and the third end of the third switch S_BIAS3 are connected, the third body diode D3 is opened;

[0134] In the case that the third end VON of the third switch S_BIAS3 is connected with the gate GT2 of the second high-voltage MOS PM2, the second body diode D2 and the third body diode D3 can be reversely connected in series as a new PMOS; in the case that the third end VON of the third switch S_BIAS3 is connected with the output end of the second clamping circuit VCLP2, the third body diode D3 is turned on, and the third body diode D3 is equivalent to a resistor.

[0135] According to the voltage regulator 100 provided in the embodiment of the present application, in the case that the second regulator 120 is opened, the first end of the third switch S_BIAS3 is connected to the third end, the third end is connected to the gate of the second high voltage MOS tube PM2, so that the second body diode D2 and the third body diode D3 can be reversely connected in series as a new PMOS tube; or the third end is connected to the output end of the second clamping circuit VCLP2, so that the third body diode D3 is turned on, which ensures that the third body diode D3 keeps on in the case that the second regulator 120 is opened, reduces the voltage drop from the bias voltage pin VBIAS to the second input voltage pin VCC, and reduces the energy waste.

[0136] In some embodiments, the voltage regulator 100 can further include a first resistor RH, a second resistor RL and a target capacitor CO.

[0137] In this embodiment, one end of the first resistor RH is connected to the second input voltage pin VCC, the drain of the first high voltage MOS tube PM1 and the drain of the third high voltage MOS tube PM3 respectively.

[0138] The other end of the first resistor RH is connected to the first regulator 110 and the second regulator 120 respectively.

[0139] The other end of the first resistor RH can be connected to the inverting input end of the first amplifier OP_VIN and the inverting input end of the second amplifier OP_BIAS.

[0140] One end of the second resistor RL is connected to the other end of the first resistor RH.

[0141] The other end of the second resistor RL is grounded.

[0142] The resistance value of the first resistor RH is greater than that of the second resistor RL.

[0143] The voltage input to the second input voltage pin VCC can be adjusted by adjusting the resistance values of the first resistor RH and the second resistor RL.

[0144] In some embodiments, the voltage regulator 100 can further include a target capacitor CO.

[0145] In this embodiment, one end of the target capacitor CO is connected to the second input voltage pin VCC, and the other end of the target capacitor CO is grounded.

[0146] As shown in FIG. 1, in the actual execution process, the first regulator 110 can be operated based on the following logic: Figure 2

[0147] ​When the first enable signal EN_VIN received by the first regulator 110 is low, the first regulator 110 is in a closed state, the first amplifier OP_VIN is not working, and the first amplifier OP_VIN outputs high resistance; the first switch S_VIN is closed, and the gate GT1 of the first high-voltage MOS PM1 is connected to the first input voltage pin VIN, so that the first body diode D1 is closed.

[0148] When the first regulator 110 is closed, only a reverse diode exists between the first input voltage pin VIN and the second input voltage pin VCC, and the first voltage input pin VIN is connected to a voltage higher than that at the second input voltage pin VCC, so that no leakage occurs from the first input voltage pin VIN to the second input voltage pin VCC.

[0149] When the first enable signal EN_VIN received by the first regulator 110 is high, the first regulator 110 is in an open state, the first amplifier OP_VIN is working, and the first switch S_VIN is open.

[0150] The first regulator 110 can provide power supply from the first input voltage pin VIN to the second input voltage pin VCC: VCC = VR_VIN*(RH+RL) / RL, where VCC is the voltage at the second input voltage pin VCC, VR_VIN is the voltage at the first input voltage pin VIN, RH is the resistance of the first resistor RH, and RL is the resistance of the second resistor RL.

[0151] The second regulator 120 can operate based on the following logic:

[0152] When the second enable signal EN_BIAS received by the second regulator 120 is low, the second regulator 120 is closed, the second amplifier OP_BIAS is not working, and the second amplifier OP_BIAS outputs high resistance;

[0153] The second switch S_BIAS2 is closed, so that the gate GT2 of the second high-voltage MOS PM2 can be connected to VMID, thereby closing the second body diode D2;

[0154] The third switch S_BIAS3 is closed, the third switch S_BIAS3 is connected to "0", so that the gate GT3 of the third high-voltage MOS PM3 can be connected to VMID, thereby closing the third body diode D3;

[0155] When the second adjuster 120 is closed, there are two non-conducting, back-to-back diodes (i.e., the second body diode D2 and the third body diode D3) between the second input voltage pin VCC and the first input voltage pin VIN, so that there is no leakage between the first input voltage pin VIN and the second input voltage pin VCC.

[0156] When the second enable signal EN_BIAS received by the second adjuster 120 is high, the second adjuster 120 is opened, the second amplifier OP_BIAS works, the second switch S_BIAS2 is connected to "0", the second switch S_BIAS2 is disconnected; the third switch S_BIAS3 is connected to "1", so that the third body diode D3 is opened;

[0157] When the third end VON of the third switch S_BIAS3 is connected to the gate GT2 of the second high-voltage MOS tube PM2, the second body diode D2 and the third body diode D3 can be reversely connected in series as a new PMOS tube; when the third end VON is connected to the output end of the second clamping circuit VCLP2, the third body diode D3 is turned on; in the state that the third body diode D3 is turned on, the resistance of the third body diode D3 is small, which avoids the voltage drop between the bias voltage pin VBIAS and the second input voltage pin VCC when the second adjuster 120 is opened.

[0158] When the second adjuster 120 is opened, the power supply from the bias voltage pin VBIAS to the second input voltage pin VCC can be provided: VCC=VR_VBIAS*(RH+RL) / RL, wherein VCC is the voltage at the second input voltage pin VCC, VR_VBIAS is the voltage at the bias voltage pin VBIAS, RH is the resistance of the first resistor RH, and RL is the resistance of the second resistor RL.

[0159] When the second adjuster 120 is in the opened or closed state, based on the back-to-back arrangement of the second body diode D2 and the third body diode D3, there is always a voltage at VMID, so that the second amplifier OP_BIAS always has power.

[0160] In the present application, when the first adjuster 110 is opened and the second adjuster 120 is closed, by arranging the back-to-back second body diode D2 and the third body diode D3, leakage from the second input voltage pin VCC to the bias voltage pin VBIAS is avoided.

[0161] When the first adjuster 110 is closed and the second adjuster 120 is opened, the first voltage at the first input voltage pin VIN is high, and the first voltage is higher than the voltage at the output voltage pin VOUT, thereby avoiding the leakage from the second input voltage pin VCC to the first input voltage pin VIN.

[0162] In the present application, the architecture of the voltage adjuster 100 is realized by using the existing body diode in the BCD process, which has high realization and is easy to implement.

[0163] The embodiments of the present application are described above with reference to the drawings; however, the present application is not limited to the specific embodiments described above, which are merely illustrative, but not restrictive. Those skilled in the art can make many changes, modifications, replacements and variations to the embodiments of the present application without departing from the principles and spirit of the present application, and all these changes, modifications, replacements and variations shall fall within the scope of the present application.

[0164] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an illustrative embodiment", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0165] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A voltage regulator, characterized by, The voltage regulator is arranged on a circuit board of a DCDC converter, and the DCDC converter is arranged between a power supply and a chip. The first regulator comprises a first input voltage pin and a first high-voltage MOS tube, the first input voltage pin is used for receiving a first voltage, a source of the first high-voltage MOS tube is connected with the first input voltage pin, and a drain of the first high-voltage MOS tube is connected with a second input voltage pin of the chip. The second regulator comprises a bias voltage pin, a second high-voltage MOS tube and a third high-voltage MOS tube, the bias voltage pin is used for receiving a second voltage, the bias voltage pin is fixedly connected with a corresponding output voltage pin of the DCDC converter, a drain of the second high-voltage MOS tube is connected with the bias voltage pin, a drain of the third high-voltage MOS tube is connected with the first regulator and the second input voltage pin respectively, and a source of the third high-voltage MOS tube is connected with a source of the second high-voltage MOS tube. When a deviation between the second voltage and a target voltage threshold is within a target threshold range, the second regulator is configured to be turned on, and the first regulator is configured to be turned off; when the deviation between the second voltage and the target voltage threshold is not within the target threshold range, the first regulator is configured to be turned on, and the second regulator is configured to be turned off.

2. The voltage regulator of claim 1, wherein, A first body diode is connected in parallel between the drain and the source of the first high-voltage MOS tube.

3. The voltage regulator of claim 1, wherein, The first regulator comprises: A first switch, one end of the first switch is connected with the source of the first high-voltage MOS tube, and the other end of the first switch is connected with the gate of the first high-voltage MOS tube.

4. The voltage regulator of claim 3, wherein, The first regulator comprises: A first amplifier, a non-inverted input end of the first amplifier is used for receiving a third voltage, an inverted input end of the first amplifier is used for receiving a feedback voltage corresponding to a circuit where the voltage regulator is arranged, and an output end of the first amplifier is connected with the other end of the first switch and the gate of the first high-voltage MOS tube respectively.

5. The voltage regulator according to any one of claims 1-4, characterized in that, A second body diode is connected in parallel between the drain and the source of the second high-voltage MOS tube, and a third body diode is connected in parallel between the drain and the source of the third high-voltage MOS tube.

6. The voltage regulator according to any one of claims 1-4, characterized in that, The second regulator comprises: A second switch, one end of the second switch is connected with the gate of the second high-voltage MOS tube, and the other end of the second switch is connected with the source of the second high-voltage MOS tube.

7. The voltage regulator according to any one of claims 1-4, characterized in that, The second regulator comprises: A second amplifier, a non-inverted input end of the second amplifier is used for receiving a fourth voltage, an inverted input end of the second amplifier is used for receiving a feedback voltage corresponding to a circuit where the voltage regulator is arranged, and an output end of the second amplifier is connected with the gate of the second high-voltage MOS tube.

8. The voltage regulator of claim 7, wherein, The second regulator comprises: A second clamping circuit, a third port of the second clamping circuit is connected between a source of the second high-voltage MOS and a source of the third high-voltage MOS, a fourth port of the second clamping circuit is grounded, and an output of the second clamping circuit is connected with the second amplifier.

9. The voltage regulator of claim 8, wherein, The second adjuster comprises: A third switch, a first end of the third switch is connected with a gate of the third high-voltage MOS, and a second end of the third switch is connected with a source of the second high-voltage MOS; A third end of the third switch is connected with a gate of the second high-voltage MOS; Or, The third end is connected with an output of the second clamping circuit.

10. A DCDC converter, characterized by, The DCDC converter is arranged between a power supply and a chip. A circuit board; The voltage adjuster according to any one of claims 1-9 is arranged on the circuit board.

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