Frequency amplitude adjustable signal generation circuit and device based on FPGA
By using an FPGA-based frequency and amplitude adjustable signal generation circuit, the problem of the inflexible adjustment of frequency and amplitude in existing signal generators is solved, realizing the output of stable waveform signals with adjustable frequency and amplitude, and improving the flexibility and ease of adjustment of the signal generator.
Patent Information
- Application Number
- CN202423195532.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2034-12-20
AI Technical Summary
Existing signal generators cannot flexibly adjust frequency and amplitude, making adjustment difficult and inflexible.
An FPGA-based frequency and amplitude adjustable signal generation circuit is adopted, including a frequency control unit, a phase accumulation unit, a waveform storage unit, a digital-to-analog conversion unit, an amplitude adjustment unit, and a filtering unit. The frequency and amplitude can be flexibly adjusted through FPGA control.
It achieves stable waveform signal output with adjustable frequency and amplitude, improving the flexibility and ease of adjustment of the signal generator.
Smart Images
Figure CN223613316U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic communication technical field especially, and it is a kind of frequency amplitude adjustable signal generating circuit and device based on FPGA. BACKGROUND
[0002] In the field of electronic communication, signal generator is one of the most common electronic instruments, and almost all experiments or tests will use it to generate various waveform signals meeting the requirements.In related technologies, the waveform signal usually output by signal generator is not adjustable, that is, the frequency and amplitude are fixed, such as the signal generator built by commonly used DDS chip (such as model AD9835 and AD9954 DDS chip). If you want to adjust the frequency and amplitude, you need to manually replace the electronic component parameters in the signal generator to achieve it, which is difficult to adjust and has poor flexibility. SUMMARY
[0003] The technical problem to be solved by the utility model is to provide a frequency amplitude adjustable signal generating circuit and device based on FPGA.
[0004] The technical scheme adopted by the utility model to solve its technical problem is: a frequency amplitude adjustable signal generating circuit based on FPGA is constructed, comprising:
[0005] a frequency control unit for outputting accumulated frequency control signal;
[0006] an FPGA connected with the frequency control unit, the FPGA comprising a phase accumulation unit connected with the frequency control unit, for receiving the accumulated frequency control signal and outputting data address, and a waveform storage unit connected with the phase accumulation unit, for storing waveform data, receiving the data address and outputting waveform digital signal;
[0007] a digital-analog conversion unit connected with the waveform storage unit, for receiving the waveform digital signal and outputting waveform analog signal;
[0008] an amplitude adjustment unit connected with the digital-analog conversion unit, for amplifying the waveform analog signal and outputting amplified analog signal; and
[0009] a filtering unit connected with the amplitude adjustment unit, for receiving the amplified analog signal and outputting waveform signal.
[0010] Preferably, the amplitude adjustment unit comprises:
[0011] a first amplification unit connected with the digital-analog conversion unit, for amplifying the waveform analog signal by one stage;
[0012] A gain setting unit for outputting a gain setting signal; and
[0013] A second amplification unit connected with the first amplification unit, the gain setting unit and the filter unit, for performing secondary amplification on the waveform analog signal after primary amplification and outputting the amplified analog signal.
[0014] Preferably, the first amplification unit comprises a first operational amplifier U1, the positive phase input end of the first operational amplifier U1 is connected with the digital-analog conversion unit, the negative phase input end is grounded, and the output end is connected with the second amplification unit.
[0015] Preferably, the second amplification unit comprises a second operational amplifier U2 and a second resistance R2, the negative phase input end of the second operational amplifier U2 is connected with the output end of the first operational amplifier U1 through the second resistance R2, the positive phase input end is grounded, the negative phase input end of the second operational amplifier U2 is also connected with the output end of the second operational amplifier U2 through the gain setting unit, and the output end of the second operational amplifier U2 is connected with the filter unit.
[0016] Preferably, the gain setting unit comprises an adjustable resistance R12 and a third resistance R3, the first fixed end of the adjustable resistance R12 is connected with the first end of the third resistance R3 and the negative phase input end of the second operational amplifier U2, the second end of the third resistance R3 is connected with a reference voltage, and the second fixed end of the adjustable resistance R12 is connected with the movable end and then connected with the output end of the second operational amplifier U2.
[0017] Preferably, the filter unit comprises a low-pass filter.
[0018] Preferably, the low-pass filter comprises a first resistance R1 and a capacitor C1, the first end of the first resistance R1 is connected with the amplitude adjustment unit, the second end of the first resistance R1 outputs the waveform signal and is grounded through the capacitor C1.
[0019] Preferably, the digital-analog conversion unit comprises a digital-analog converter with model number of DAC0832 or AN9767.
[0020] Preferably, the waveform storage unit is a ROM memory in the FPGA.
[0021] The utility model further constructs a kind of frequency amplitude adjustable signal generating device based on FPGA, including the frequency amplitude adjustable signal generating circuit based on FPGA described above.
[0022] The utility model has the following beneficial effects: provide a kind of frequency amplitude adjustable signal generating circuit based on FPGA, can output adjustable frequency and amplitude, and stable waveform signal. Attached Figure Description
[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:
[0024] Figure 1 This is a circuit structure block diagram of an FPGA-based frequency amplitude adjustable signal generation circuit provided in one embodiment of the present invention;
[0025] Figure 2 This is a circuit schematic diagram of a digital-to-analog conversion unit, an amplitude adjustment unit, and a filtering unit provided in an embodiment of this utility model;
[0026] Figure 3 This is a waveform diagram of a reference clock signal, a waveform digital signal, and an amplified analog signal when the waveform signal type is a sine wave, according to an embodiment of this utility model.
[0027] Figure 4 This is a waveform diagram of a sine wave waveform signal provided in an embodiment of the present invention.
[0028] Original Symbol Table:
[0029] Frequency control unit 1; phase accumulation unit 21; waveform storage unit 22; digital-to-analog conversion unit 3; amplitude adjustment unit 4; first amplification unit 41; first operational amplifier U1; gain setting unit 42; adjustable resistor R12; third resistor R3; second amplification unit 43; second operational amplifier U2; second resistor R2; filter unit 5; first resistor R1; capacitor C1. Detailed Implementation
[0030] To provide a clearer understanding of the technical features, objectives, and effects of this utility model, the specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.
[0031] In the following description, it should be understood that the orientations or positional relationships indicated by terms such as "front," "rear," "up," "down," "left," "right," "longitudinal," "horizontal," "vertical," "horizontal," "top," "bottom," "inner," "outer," "head," and "tail" are based on the orientations or positional relationships shown in the accompanying drawings, and are constructed and operated in a specific orientation. They are only for the convenience of describing this technical solution and do not indicate that the device or component referred to must have a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0032] This invention provides a frequency-amplitude adjustable signal generation circuit based on FPGA. This FPGA-based frequency-amplitude adjustable signal generation circuit can output waveform signals with adjustable frequency and amplitude, wherein the types of waveform signals include, but are not limited to, sine waves, triangle waves, sawtooth waves and square waves.
[0033] Figure 1 is the circuit structure block diagram of the frequency amplitude adjustable signal generating circuit based on FPGA provided by an embodiment of the utility model. As shown in the figure, Figure 1 The frequency amplitude adjustable signal generating circuit based on FPGA can include frequency control unit 1, FPGA, digital analog conversion unit 3, amplitude adjustment unit 4 and filter unit 5. Wherein, FPGA can include phase accumulation unit 21 and waveform storage unit 22.
[0034] Frequency control unit 1 is used to output accumulated frequency control signal. Specifically, the accumulated frequency control signal is digital signal, and the accumulated frequency control signal can determine the size of frequency control word (as positive integer). Further, frequency control unit 1 can include button, mouse, keyboard, touch screen and other electronic components that can realize man-machine information interaction, so that the user can control the setting value of accumulated frequency control signal by operating frequency control unit 1, and then set the size of frequency control word.
[0035] Please refer to Figure 1 Phase accumulation unit 21 is connected with frequency control unit 1, and phase accumulation unit 21 is used to receive accumulated frequency control signal and output data address according to accumulated frequency control signal phase accumulation unit 21.
[0036] In some embodiments, phase accumulation unit 21 can include clock source and phase accumulator, wherein the clock source is used to output reference clock signal with frequency close to constant. Phase accumulator is connected with clock source to receive reference clock signal, and then determines accumulated frequency according to reference clock signal and the frequency control word, and based on the accumulated frequency, carries out accumulated counting and outputs accumulated value as the data address, and outputs data address to waveform storage unit 22. Wherein, the expression of accumulated frequency can be: Fo=(K / 2^N)*Fc, wherein Fo represents accumulated frequency, K represents frequency control word, N is the bit width of waveform storage unit 22, and Fc represents the frequency of reference clock signal.
[0037] It should be noted that FPGA refers to field programmable logic gate array, and the utility model designs language (such as Verilog HDL language) for circuit design of FPGA, and clock source and phase accumulator both belong to existing circuit that can be designed on FPGA.
[0038] The waveform storage unit 22 pre-stores waveform data, the waveform data contains a plurality of voltage values of a waveform signal to be output, and the waveform signal of a set shape can be obtained by connecting the voltage values, so that the type of the waveform signal output by the frequency amplitude adjustable signal generating circuit can be controlled by setting the stored waveform data, and the waveform data can be obtained by operating a host computer (such as a computer) to run MATLAB software. The waveform storage unit 22 is connected with the phase accumulation unit 21 to receive a data address, and then outputs a waveform digital signal according to the data address.
[0039] In some embodiments, the waveform storage unit 22 can be a ROM memory in the FPGA. It should be noted that the ROM memory is an inherent circuit in the IP core of the FPGA.
[0040] Referring to Figure 1 , the digital-to-analog conversion unit 3 is connected with the waveform storage unit 22 to receive the waveform digital signal, and then converts the waveform digital signal into an analog signal to obtain a waveform analog signal, and outputs the waveform analog signal to the amplitude adjustment unit 4.
[0041] In some embodiments, the digital-to-analog conversion unit 3 can include a digital-to-analog converter U4 with a model of DAC0832 or AN9767.
[0042] Referring to Figure 1 , the amplitude adjustment unit 4 is connected with the digital-to-analog conversion unit 3 to receive the waveform analog signal, and then amplifies the waveform analog signal to obtain an amplified analog signal, and outputs the amplified analog signal to the filter unit 5.
[0043] Figure 2 is a circuit principle diagram of the digital-to-analog conversion unit, the amplitude adjustment unit and the filter unit provided by an embodiment of the utility model. As shown in Figure 2 , the amplitude adjustment unit 4 can include a first amplification unit 41, a gain setting unit 42 and a second amplification unit 43.
[0044] Referring to Figure 2 , the first amplification unit 41 is connected with the digital-to-analog conversion unit 3 to receive the waveform analog signal, and then amplifies the waveform analog signal to obtain a first amplified waveform analog signal, and inputs the first amplified waveform analog signal to the second amplification unit 43.
[0045] In some embodiments, as Figure 2As shown, the first amplification unit 41 can include a first operational amplifier U1. The non-inverting input terminal of the first operational amplifier U1 is connected to the digital-to-analog conversion unit 3, the inverting input terminal of the first operational amplifier U1 is grounded, and the output terminal of the first operational amplifier U1 is connected to the second amplification unit 43. In this embodiment, the first operational amplifier U1 constitutes an open-loop amplification circuit and can amplify the waveform analog signal output by the digital-to-analog conversion unit 3. Correspondingly, in this embodiment, the digital-to-analog converter U4 included in the digital-to-analog conversion unit 3 is of the DAC0832 type. The data input terminal of the digital-to-analog converter U4 is connected to the waveform storage unit 22 to access the waveform digital signal. The first digital signal output terminal I out1 of the digital-to-analog converter U4 is connected to the inverting input terminal of the first operational amplifier U1, and the second digital signal output terminal I out2 is connected to the non-inverting input terminal of the first operational amplifier U1 to input the waveform digital signal to the first operational amplifier U1.
[0046] Figure 3 is a waveform diagram of the reference clock signal, the waveform digital signal, and the amplified analog signal when the waveform signal type is a sine wave according to an embodiment of the present application. Please refer to Figure 3 the waveform B in Figure 3 , the waveform B can be a reference clock signal output by a clock source.
[0047] Please refer to Figure 2 , the gain setting unit 42 is connected to the second amplification unit 43 to output a gain setting signal to the second amplification unit 43. The gain setting signal is a resistance signal.
[0048] In some embodiments, as shown in Figure 2 , the gain setting unit 42 can include an adjustable resistor R12 and a third resistor R3. The first fixed terminal of the adjustable resistor R12 is connected to the first terminal of the third resistor R3 and the first terminal of the first amplification unit 41, the second terminal of the third resistor R3 is connected to a reference voltage, the second fixed terminal of the adjustable resistor R12 is connected to the movable terminal of the adjustable resistor R12, and the movable terminal of the adjustable resistor R12 is also connected to the second terminal of the first amplification unit 41. In this embodiment, when the digital-to-analog converter included in the digital-to-analog conversion unit 3 is of the DAC0832 type, the second terminal of the third resistor R3 can be connected to the reference voltage output terminal of the digital-to-analog converter U4 to obtain the reference voltage.
[0049] Please refer to Figure 2 , the second amplification unit 43 is connected to the first amplification unit 41, the gain setting unit 42, and the filtering unit 5. The second amplification unit 43 is used to amplify the waveform analog signal after the first amplification (i.e., the waveform analog signal after the first amplification) to obtain the amplified analog signal, and output the amplified analog signal to the filtering unit 5.
[0050] In some embodiments, as shown in Figure 2 The second amplification unit 43 can include a second operational amplifier U2 and a second resistor R2. The negative input terminal of the second operational amplifier U2 is connected to the output terminal of the first operational amplifier U1 through the second resistor R2. The positive input terminal of the second operational amplifier U2 is grounded. The negative input terminal of the second operational amplifier U2 is also connected to the output terminal of the second operational amplifier U2 through the adjustable resistor R12 included in the gain setting unit 42. The output terminal of the second operational amplifier U2 is connected to the filtering unit 5. It should be noted that the negative input terminal of the second operational amplifier U2 corresponds to the second terminal of the first amplification unit 41, and the output terminal of the second operational amplifier U2 corresponds to the second terminal of the first amplification unit 41. In this embodiment, the second operational amplifier U2, the second resistor R2, the adjustable resistor R12 included in the gain setting unit 42, and the third resistor R3 form an inverting amplification circuit. The gain of the amplification circuit is determined by the resistance between the first fixed terminal and the movable terminal of the adjustable resistor R12 and the resistance of the third resistor R3. The user can adjust the resistance between the first fixed terminal and the movable terminal of the adjustable resistor R12, which is equivalent to adjusting the gain setting signal, thereby adjusting the gain of the amplification circuit and further adjusting the amplitude of the amplified analog signal.
[0051] Please refer to Figure 1 The filtering unit 5 is connected to the amplitude adjustment unit 4 to receive the amplified analog signal, filter the amplified analog signal, obtain a waveform signal, and output the waveform signal. It should be noted that the waveform storage unit 22 outputs the waveform digital signal sequentially, resulting in a discrete amplified analog signal in the form of a non-smooth waveform. The filtering unit 5 performs low-pass filtering on the amplified analog signal to convert the non-smooth waveform signal into a smooth waveform signal.
[0052] In some embodiments, the filtering unit 5 can include a low-pass filter. Further, as shown in Figure 2 The low-pass filter can include a first resistor R1 and a capacitor C1. The first end of the first resistor R1 is connected to the amplitude adjustment unit 4. The second end of the first resistor R1 outputs the waveform signal and is grounded through the capacitor C1. In this embodiment, the first resistor R1 and the capacitor C1 form an RC filter circuit. The passband range can be adjusted by adjusting the first resistor R1 and the capacitor C1, thereby achieving a low-pass filtering effect. Moreover, the circuit structure of this embodiment is simple and low in cost.
[0053] Figure 3 is a waveform diagram of the reference clock signal, the waveform digital signal, and the amplified analog signal when the type of the waveform signal is a sine wave according to an embodiment of the present application. Taking the type of the waveform signal as a sine wave as an example, please refer to Figures 1 to 4The working principle of this utility model is as follows: First, the phase accumulator will calculate the accumulating frequency control signal (equivalent to the frequency control word) output by the frequency control unit 1 and the reference clock signal output by the clock source (corresponding to the frequency control word). Figure 3 Waveform C in the ROM periodically outputs the data address; then, after each data address is received, the ROM memory outputs a waveform digital signal (corresponding to the voltage value) that controls the magnitude of the voltage value. Figure 3 As shown in waveform A), it can be understood that as long as the data address is the same, the waveform digital signal output by the ROM memory will also be the same. Therefore, when the phase accumulator repeatedly outputs the data address, the ROM memory also repeatedly outputs the corresponding waveform digital signal. That is, the waveform digital signal has the characteristic of high consistency, which helps to improve the stability of the waveform signal. Next, the digital-to-analog converter 3 converts the waveform digital signal into an analog signal, thereby obtaining the waveform analog signal. Then, the first operational amplifier U1 amplifies the waveform analog signal in one stage to obtain the waveform analog signal after one stage amplification. Next, the inverting amplifier circuit composed of the second operational amplifier U2, the second resistor R2, the adjustable resistor R12, and the third resistor R3 amplifies the waveform analog signal after one stage amplification in two stages to obtain the amplified analog signal (corresponding to...). Figure 3 The waveform D in the image is obtained, and its amplitude can be adjusted by operating the adjustable resistor R12. Finally, the amplified analog signal is low-pass filtered by the RC filter circuit composed of the first resistor R1 and the capacitor C1, thereby obtaining the final waveform. Figure 4 The sine wave shown.
[0054] Understandably, this invention can fully utilize the control flexibility of FPGA to build a phase accumulation unit and a waveform storage unit, enabling users to control the frequency of the waveform signal by adjusting the accumulation frequency control signal. It also utilizes the stability of the output digital signal of the waveform storage unit to improve the stability of the waveform signal, and achieves amplitude control of the waveform signal by operating the amplitude adjustment unit. Moreover, this invention also has the advantage of simple circuit structure.
[0055] This utility model also provides an FPGA-based frequency amplitude adjustable signal generator, including the FPGA-based frequency amplitude adjustable signal generator circuit provided in the embodiments of this utility model.
[0056] It can be understood that the above embodiment only expresses the preferred embodiment of the utility model, the description is more specific and detailed, but it can not be understood as the limitation of the utility model patent scope; it should be pointed out that for ordinary skilled person in the art, the above technical features can be freely combined without departing from the concept of the utility model, and a number of deformations and improvements can be made, which belong to the protection scope of the utility model; therefore, any equivalent transformation and modification within the scope of the utility model patent claim should belong to the scope of the utility model patent claim.
Claims
1. A frequency and amplitude adjustable signal generating circuit based on FPGA, characterized in that, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
2. The FPGA-based frequency and amplitude adjustable signal generating circuit according to claim 1, characterized in that, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
3. The FPGA-based frequency and amplitude adjustable signal generator circuit according to claim 2, wherein, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
4. The FPGA-based frequency and amplitude adjustable signal generating circuit according to claim 3, characterized in that, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
5. The FPGA-based frequency and amplitude adjustable signal generator circuit according to claim 4, characterized in that, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
6. The FPGA-based frequency and amplitude adjustable signal generator circuit according to claim 1, wherein, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
7. The FPGA-based frequency and amplitude adjustable signal generator circuit according to claim 6, characterized in that, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
8. The FPGA-based frequency and amplitude adjustable signal generator circuit according to claim 1, wherein, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
9. The FPGA-based frequency and amplitude adjustable signal generator circuit according to any one of claims 1 to 8, characterized in that, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA.
10. A frequency-amplitude adjustable signal generating device based on FPGA, characterized in that, The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. The application relates to a frequency-amplitude adjustable signal generating circuit based on FPGA. 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