IGBT (Insulated Gate Bipolar Translator) gate driving chip test system

Abstract

The utility model discloses an IGBT gate drive chip test system, comprising an IGBT gate drive chip test industrial personal computer which is electrically connected with an IGBT gate drive chip to be tested through an electric channel conversion box; the IGBT gate drive chip test industrial personal computer comprises a plurality of source measurement units, and the source measurement units, the signal control unit and the data processing unit are interconnected through a bus; the source measurement unit comprises a processor, and the processor is electrically connected with a current-increasing voltage-measuring FIMV module and a voltage-increasing current-measuring FVMI module through a DAC module and an ADC module. The IGBT gate drive chip test system disclosed by the utility model can output high voltage and drive large current, and is fast in test speed.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor testing technology, specifically to a semiconductor optocoupler testing system, and more particularly to an IGBT gate driver chip testing system. Background Technology

[0002] In recent years, with the development of domestic new energy vehicles, the demand for IGBT gate drive chips used in vehicle inverters and AC / DC motors has increased, and the quality of the chips directly affects driving safety.

[0003] Chip packaging manufacturers perform electrical tests on IGBT gate driver chips during the packaging stage to ensure production quality. These electrical tests include high current tests such as IOH, IOL, and IOLF; output voltage tests such as VOH and VOH; and other tests such as VDesat, Iclamp, Vclamp, and Vfault. Failure in any of these tests will result in a defective chip.

[0004] Therefore, it is particularly important to develop a domestically produced IGBT gate driver chip testing system for the chip packaging and testing stage. Utility Model Content

[0005] This invention overcomes the shortcomings of the prior art and provides an IGBT gate driver chip testing system that can output high voltage, drive large current, and test at high speed.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows: an IGBT gate driver chip testing system, comprising: an IGBT gate driver chip testing industrial control computer, which is electrically connected to the IGBT gate driver chip under test through an electrical channel conversion box;

[0007] The industrial control computer for testing IGBT gate driver chips includes several source measurement units, and the source measurement units, signal control units, and data processing units are interconnected via a bus.

[0008] The source measurement unit includes a processor, which is electrically connected to the applied current-to-voltage (FIMV) module and the applied voltage-to-current (FVMI) module via a DAC module and an ADC module.

[0009] In a preferred embodiment of this utility model, the electrical channel conversion box includes an opto-relay isolation module; the opto-relay isolation module is used to switch the power supply path for different electrical measurement items.

[0010] In a preferred embodiment of this utility model, the data processing unit sends circuit operation commands and commands for applying electrical measurement excitation parameters to the source measurement unit via a bus; the source measurement unit transmits the response values ​​of the electrical measurement items back to the data processing unit via the bus.

[0011] The processor of the source measurement unit is used to receive excitation commands or transmit response values;

[0012] Several source measurement units are independent of each other and are controlled only by the data processing unit. The source measurement units can be tested synchronously or asynchronously.

[0013] In a preferred embodiment of this utility model, the data processing unit sends a photorelay control command to the signal control unit via a bus; after receiving and processing the command, the signal control unit sends the control signal to the corresponding photorelay isolation module in the source measurement channel conversion box, and the photorelay isolation module controls the corresponding photorelay to be turned on or off in order to achieve the purpose of selecting different paths according to different electrical measurement items.

[0014] In a preferred embodiment of this utility model, the voltage-to-current (FVMI) module includes: a constant voltage source electrically connected to the DAC module, an operational amplifier connected to the ADC module, and a ground terminal, which serves as the COM terminal of the output terminal.

[0015] The output terminal of the constant voltage source is connected to one end of the sampling resistor Rs2. The other end of the sampling resistor Rs2 is led out as the HOT terminal. The connection node between the sampling resistor Rs2 and the constant voltage source is connected to the inverting terminal of the operational amplifier through attenuator one. The HOT terminal of the sampling resistor Rs2 is connected to the non-inverting terminal of the operational amplifier through buffer one and attenuator two connected in series.

[0016] In a preferred embodiment of this utility model, the applied current-to-voltage FIMV module includes: a constant current source electrically connected to the DAC module, and an operational amplifier II electrically connected to the ADC module;

[0017] One output of the constant current source is led out as the HOT terminal, and the output of the constant current source is also connected to the inverting terminal of the operational amplifier two through the series-connected buffer two and attenuator three. The non-inverting terminal of the operational amplifier two is led out as the COM terminal through attenuator four.

[0018] In a preferred embodiment of this utility model, when the ICCL test item is selected, the DAC module two and ADC module two of the source measurement unit two are respectively connected to the electrical channel conversion box through the voltage-to-current (FVMI) module two of the source measurement unit two. The HOT terminal of the voltage-to-current (FVMI) module two is connected to one end of the opto-relay Kv of the electrical channel conversion box, and the other end of the opto-relay Kv is connected to the VCC terminal of the gate driver chip of the IGBT under test. The COM terminal of the voltage-to-current (FVMI) module two is connected to one end of the opto-relay Ke of the electrical channel conversion box, and the other end of the opto-relay Ke is connected to the VEE terminal of the gate driver chip of the IGBT under test.

[0019] In a preferred embodiment of this utility model, when the VOH test item is selected, the plurality of source measurement units include source measurement unit one, source measurement unit two, and source measurement unit three;

[0020] The DAC module 1 of the source measurement unit 1 is connected to the electrical channel conversion box through the current-voltage measurement FIMV module 1 of the source measurement unit 1. The HOT terminal of the current-voltage measurement FIMV module 1 is connected to one end of the photorelay Ka, and the other end of the photorelay Ka is connected to the sampling terminal of the light source of the IGBT gate driver chip under test. The COM terminal of the current-voltage measurement FIMV module 1 is connected to one end of the photorelay Kc of the electrical channel conversion box, and the other end of the photorelay Kc is connected to the other sampling terminal of the IGBT gate driver chip under test.

[0021] The DAC module 2 of the source measurement unit 2 is connected to the electrical channel conversion box through the voltage-to-current (FVMI) module 2 of the source measurement unit 2. The HOT terminal of the voltage-to-current (FVMI) module 2 is connected to one end of the opto-relay Kv of the electrical channel conversion box, and the other end of the opto-relay Kv is connected to the VCC terminal of the gate driver chip of the IGBT under test. The COM terminal of the voltage-to-current (FVMI) module 2 is connected to one end of the opto-relay Ke of the electrical channel conversion box, and the other end of the opto-relay Ke is connected to the VEE terminal of the gate driver chip of the IGBT under test.

[0022] The DAC module three and ADC module three of the source measurement unit three are connected to the electrical channel conversion box through the voltage-to-current (FVMI) module three of the source measurement unit three. The HOT terminal of the voltage-to-current (FVMI) module three is connected to one end of the opto-relay Ko of the electrical channel conversion box, and the other end of the opto-relay Ko is connected to the VOUT output terminal of the gate driver chip of the IGBT under test. The COM terminal of the voltage-to-current (FVMI) module three is connected to one end of the opto-relay Ke2 of the electrical channel conversion box, and the other end of the opto-relay Ke2 is connected to the VEE terminal of the gate driver chip of the IGBT under test.

[0023] In a preferred embodiment of this invention, the constant voltage source and constant current source are OPA548 chips.

[0024] In a preferred embodiment of this invention, attenuators one, two, three, and four are all resistor voltage divider attenuators. Each resistor voltage divider attenuator includes resistors R1 and R2 connected in series. One end of resistor R1 is the U0 terminal, where the original voltage is connected to the sampling resistor Rs2. A lead from the connection point of resistors R1 and R2 is the U1 terminal, where the attenuated voltage is displayed. Furthermore, U1 = U0 * [R2 / (R1 + R2)]. Specifically, the resistor voltage divider attenuator uses precision resistors (0.05% accuracy) for voltage division.

[0025] Specifically, the opto-relays used in the electrical channel conversion box 8 are models AQY212SX and AQV252G3S. Operational amplifiers one and two are instrumentation amplifiers using the INA118U chip. Buffers one and two are voltage followers composed of OPA445BM chips. The non-inverting input of the resistor divider attenuator is connected to the HOT terminal, and the output is connected to the attenuator (U0 voltage).

[0026] This utility model solves the defects existing in the technical background, and the beneficial technical effects of this utility model are:

[0027] This invention relates to an IGBT gate driver chip testing system, which can output high voltage, drive large current, and test at high speed. Attached Figure Description

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0029] Figure 1 This is a schematic diagram of the overall circuit structure of a preferred embodiment of the present invention;

[0030] Figure 2 This is a pin definition diagram of an IGBT gate driver chip in the prior art detected in a preferred embodiment of this utility model;

[0031] Figure 3 This is a schematic diagram of the circuit structure of the voltage-to-current (FVMI) module of the signal source excitation superposition circuit in a preferred embodiment of this utility model.

[0032] Figure 4 This is a schematic diagram of the circuit structure of the current-measuring voltage FIMV module in the signal source excitation superposition circuit schematic diagram of a preferred embodiment of this utility model;

[0033] Figure 5 This is a schematic diagram of the VOH electrical measurement test circuit structure of the signal source excitation superposition circuit of the preferred embodiment of this utility model (the structure shown in the source measurement unit part of this figure is the structure used in this test project, and this test project only uses the FIMV module of source measurement unit one, the FVMI module of source measurement unit two, and the FIMV module of source measurement unit three).

[0034] Figure 6 This is a schematic diagram of the ICCL electrical test circuit structure for a preferred embodiment of the signal source excitation superposition circuit of this utility model (the structure of the source measurement unit shown in this figure is the structure used in this test project; and this test project only uses the FVMI module of source measurement unit two).

[0035] Figure 7The circuit diagram of the signal source excitation superposition circuit of the preferred embodiment of this utility model is a schematic diagram of the circuit structure of a resistor voltage divider attenuator. Detailed Implementation

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These drawings are simplified schematic diagrams, which are only used to illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0037] It should be noted that if directional indicators (such as up, down, bottom, top, etc.) are involved in the embodiments of this utility model, the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Unless otherwise explicitly specified and limited, the terms "set," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances. Example 1

[0038] like Figure 1 As shown, this patent discloses an industrial control computer for testing IGBT gate driver chips, comprising several source measurement units, a signal control unit 5 and a data processing unit 6 interconnected with the source measurement units, and an electrical channel conversion box 8. The electrical channel conversion box 8 includes several opto-relay isolation modules 81 for switching the power-on path for different electrical test items. In this embodiment, the source measurement units include source measurement unit 1, source measurement unit 2, source measurement unit 3, and source measurement unit 4, and are connected to the IGBT gate driver chip under test through the signal control unit 5, the data processing unit 6, and the electrical channel conversion box 8.

[0039] Specifically, each source measurement unit includes a processor, which is connected to a FIMV module and / or FVMI module via a DAC module and / or an ADC module. Specifically, source measurement unit 1 includes interconnected processor 11, DAC module 12, ADC module 13, FIMV module 14, and FVMI module 15; source measurement unit 2 includes interconnected processor 21, DAC module 22, ADC module 23, FIMV module 24, and FVMI module 25; source measurement unit 3 includes interconnected processor 31, DAC module 32, ADC module 33, FIMV module 34, and FVMI module 35; source measurement unit 4 includes interconnected processor 41, DAC module 42, ADC module 43, FIMV module 44, and FVMI module 45.

[0040] Data processing unit 6 sends circuit action commands and excitation parameter commands for electrical measurement items to source measurement unit 1, source measurement unit 2, source measurement unit 3, and source measurement unit 4 via bus 7; source measurement unit 1, source measurement unit 2, source measurement unit 3, and source measurement unit 4 transmit electrical measurement item response values ​​back to data processing unit 6 via bus 7; source measurement unit 1, source measurement unit 2, source measurement unit 3, and source measurement unit 4 receive excitation commands and transmit response values, respectively, which are implemented by processor 11, processor 21, processor 31, and processor 41.

[0041] Source measurement unit 1, source measurement unit 2, source measurement unit 3, and source measurement unit 4 are independent of each other and are only controlled by data processing unit 6. Each source measurement unit can be tested synchronously or asynchronously.

[0042] The data processing unit 6 sends a photorelay control command to the signal control unit 5 via the bus 7. After receiving and processing the command, the signal control unit 5 sends the control signal to the corresponding photorelay module of the source measurement channel conversion box 8 via the signal line 52, controlling the photorelay to turn on or off in order to achieve the purpose of selecting different paths according to different electrical measurement items.

[0043] Specifically, the voltage-to-current (FVMI) module includes:

[0044] A constant voltage source electrically connected to the DAC module, and an operational amplifier connected to the ADC module, and a ground terminal, with the ground terminal serving as the COM terminal of the output terminal; the output terminal of the constant voltage source is connected to one end of the sampling resistor Rs2, and the other end of the sampling resistor Rs2 is led out as the HOT terminal; the connection node between the sampling resistor Rs2 and the constant voltage source is connected to the inverting terminal of the operational amplifier 51 through attenuator 511; the HOT terminal of the sampling resistor Rs2 is connected to the non-inverting terminal of the operational amplifier 61 through a series buffer 311 and attenuator 411.

[0045] Specifically, the current-to-voltage (FIMV) module includes:

[0046] A constant current source electrically connected to the DAC module and an operational amplifier 62 electrically connected to the ADC module; one output of the constant current source is led out as the HOT terminal, and the output of the constant current source is also connected to the inverting terminal of the operational amplifier 62 through a series-connected buffer 312 and attenuator 512. The non-inverting terminal of the operational amplifier 62 is led out as the COM terminal through attenuator 412.

[0047] Specifically, the constant voltage source and constant current source use the OPA548 chip.

[0048] Specifically, the attenuator uses a resistor voltage divider attenuator; the attenuator includes resistors R1 and R2 connected in series. One end of resistor R1 is the U0 end, which is the original voltage connected to the sampling resistor Rs2. The connection point of resistors R1 and R2 leads out to the U1 end, which is the attenuated voltage; and U1 = U0 * [R2 / (R1 + R2)].

[0049] The working principle of the FVMI module is as follows:

[0050] During the power-on phase: The DAC converts the digital excitation into analog excitation and sends it to the constant voltage source of the FVMI module. The constant voltage source outputs DC voltage at the HOT terminal according to the set value.

[0051] Detection phase: A DC voltage is applied from the HOT terminal to the COM terminal. If a load is connected in between, a current is generated. The current flows through the sampling resistor Rs2, generating a sampling voltage Vs. One end of attenuator 511 is connected to one end of the sampling resistor Rs2, and the other end is connected to op-amp 61 (op-amp 61 is an instrumentation amplifier). The other end of the sampling resistor Rs2 is connected to buffer 311. One end of attenuator 411 is connected to buffer 3, and the other end is connected to the non-inverting input of instrumentation amplifier 6. The sampling voltage Vs is attenuated and processed by op-amp 61 before being sent to the ADC module.

[0052] The working principle of the FIMV module is as follows:

[0053] The power-on phase is as follows: the DAC module converts the digital excitation into analog excitation and sends it to the constant current source of the voltage measurement and current FIMV module. The constant current source outputs the corresponding current to the HOT terminal according to the set value.

[0054] If the two ends of the load are connected to the HOT and COM terminals respectively, the current flows out from the HOT terminal and into the COM terminal, and the current generates voltage through the load.

[0055] One end of buffer 3 is connected to the HOT terminal, one end of attenuator 312 is connected to the other end of buffer 2 312, the other end of attenuator 3 512 is connected to the inverting input terminal of op-amp 2 62 (op-amp 2 62 is an instrumentation amplifier), one end of attenuator 412 is connected to the COM terminal, and the other end is connected to the non-inverting input terminal of op-amp 2 62.

[0056] The detection phase is as follows: the sampled voltage is attenuated and then processed by the instrumentation amplifier 6 before being sent to the ADC module. Example 2

[0057] Based on Example 1, such as Figure 2 The diagram shows the circuit diagram for the ICCL electrical test project. A constant voltage of 30V is applied to the VCC2 terminal of the IGBT gate driver chip under test, and the ICCL current is detected.

[0058] When the ICCL test item is selected, the DAC module 22 and ADC module 23 of the source measurement unit 2 are connected to the electrical channel conversion box 8 through the voltage-to-current (FVMI) module 25 of the source measurement unit 2. The HOT terminal of the FVMI module 25 is connected to one end of the opto-relay Kv of the electrical channel conversion box 8, and the other end of the opto-relay Kv is connected to the VCC terminal of the gate driver chip of the IGBT under test. The COM terminal of the FVMI module 25 is connected to one end of the opto-relay Ke of the electrical channel conversion box 8, and the other end of the opto-relay Ke is connected to the VEE terminal of the gate driver chip of the IGBT under test.

[0059] Specifically, the photorelay is used as a switch in this circuit, selecting different paths when different switches are turned on:

[0060] according to Figure 6 When only the photorelays Kv and Ke are turned on, the power-on path for the ICCL electrical test item is formed; at this time, the source measurement unit 2 can measure the ICCL test value of the gate driver chip of the IGBT under test by performing power-on and detection.

[0061] The electrical channel control command is sent from the data processing unit 6 to the signal control unit 5 via the bus 7. The signal control unit 5 controls the two sets of optical relays Kv and Ke of the optical relay isolation module 81 of the electrical channel conversion box 8 to conduct, so that the source measurement unit and the corresponding pin of the material under test form a test path.

[0062] Simultaneously, the instruction is sent from the data processing unit 6 to the processor 21 via the bus 7. After processing by the processor 21, a DA digital excitation is sent to the DAC module 22. The DAC module 22 converts the digital excitation into an analog excitation and sends it to the voltage-to-current (VVMI) module 25. The HOT terminal of the VVMI module 25 is connected to one end of the opto-relay Kv of the opto-relay isolation module 81 of the electrical channel conversion box 8. The other end of the opto-relay Kv is connected to the VCC2 terminal of the test material. The COM terminal of the VVMI module 25 is connected to one end of the opto-relay Ke of the opto-relay isolation module 81 of the electrical channel conversion box 8. The other end of the opto-relay Ke is connected to the VEE terminal of the test material. When a voltage is applied to the VVMI module 25, a current ICCL is generated. After being detected by the VVMI module 25, the current is sent to the ADC module 23, converted into a digital response, and then transmitted back to the data processing unit (source measurement unit 2) by the processor 21 via the bus 7. Example 3

[0063] Based on Example 1, such as Figure 3 The circuit diagram shown is for the VOH electrical test project. The light source current is applied to the LED1 port of the material under test, the supply voltage is applied to the VCC2 port of the material under test, and the current is applied to the VOUT port of the material under test. The voltage VOH generated between the VOUT terminal and the VEE terminals of the material is tested. The instruction is sent from the data processing unit 6 to the processor 11, processor 21, and processor 31 through the bus 7 respectively.

[0064] When selecting the VOH test item, several source measurement units include source measurement unit 1, source measurement unit 2, and source measurement unit 3.

[0065] The DAC module 12 of the source measurement unit 1 is connected to the electrical channel conversion box 8 through the current-voltage measurement FIMV module 14 of the source measurement unit 1. The HOT terminal of the current-voltage measurement FIMV module 14 is connected to one end of the photorelay Ka, and the other end of the photorelay Ka is connected to the sampling terminal of the light source of the IGBT gate driver chip under test. The COM terminal of the current-voltage measurement FIMV module 14 is connected to one end of the photorelay Kc of the electrical channel conversion box 8, and the other end of the photorelay Kc is connected to the other sampling terminal of the IGBT gate driver chip under test.

[0066] The DAC module 22 of the source measurement unit 2 is connected to the electrical channel conversion box 8 through the voltage-to-current (FVMI) module 25 of the source measurement unit 2. The HOT terminal of the FVMI module 25 is connected to one end of the opto-relay Kv of the electrical channel conversion box 8, and the other end of the opto-relay Kv is connected to the VCC terminal of the gate driver chip of the IGBT under test. The COM terminal of the FVMI module 25 is connected to one end of the opto-relay Ke of the electrical channel conversion box 8, and the other end of the opto-relay Ke is connected to the VEE terminal of the gate driver chip of the IGBT under test.

[0067] The DAC module 32 and ADC module 33 of the source measurement unit 3 are connected to the electrical channel conversion box 8 through the voltage-to-current (FVMI) module 34 of the source measurement unit 3. The HOT terminal of the FVMI module 34 is connected to one end of the opto-relay Ko of the electrical channel conversion box 8. The other end of the opto-relay Ko is connected to the VOUT output terminal of the gate driver chip of the IGBT under test. The COM terminal of the FVMI module 34 is connected to one end of the opto-relay Ke2 of the electrical channel conversion box 8. The other end of the opto-relay Ke2 is connected to the VEE terminal of the gate driver chip of the IGBT under test.

[0068] Specifically, during the VOH test, the opto-relay isolation module performs the following actions simultaneously:

[0069] a. When photorelays Ka and Kc are turned on, the power supply path of the light source of the IGBT gate driver chip under test is turned on. At this time, the source measurement unit-1 can apply a constant current to light up the internal light source of the IGBT gate driver chip under test.

[0070] b. When photorelays Kv and Ke are turned on, they form a power supply path from the VCC terminal to the VEE terminal of the material under test. At this time, the source measurement unit 2 applies a constant voltage to provide VCC power to the gate driver chip of the IGBT under test (in the VOH project, it is only used for chip power supply).

[0071] c. When photorelays Kv and Ke are turned on, the Vout to VEE terminals of the gate driver chip of the IGBT under test are powered on, and the test path is turned on. At this time, the source measurement unit 3 applies a constant current and detects the voltage. The measured voltage value is VOH. The sampled VOH is attenuated and processed by operational amplifier 61 or operational amplifier 62 and then sent to ADC module 33 to be converted into a digital response. The processor 31 then transmits the response back to the data processing unit 6 via bus 7.

[0072] The electrical channel control command is sent from the data processing unit 6 to the signal control unit 5 via the bus 7. The signal control unit 5 controls the two sets of photorelays Ka and Kc to conduct, so that the source measurement unit and the light source LED1 pin of the material under test form a power-on path; controls the two sets of photorelays Kv and Ke to conduct, so that the source measurement unit and the gate driver chip of the IGBT under test form a power-on path; controls the two sets of photorelays Ko and Ke2 to conduct, so that the source measurement unit and the VOUT and VEE pins of the material under test form a power-on and testing path.

[0073] After the instruction to apply excitation to the light source of the test material is processed by the processor 11, the DA digital excitation is sent to the DAC module 12. The DAC module 12 converts the digital excitation into an analog excitation and sends it to the FIMV module 14. The HOT terminal of the FIMV module 14 is connected to one end of the photorelay Ka of the photorelay isolation module 81 of the electrical channel conversion box 8, and the other end of the photorelay Ka is connected to the Anode terminal of the test material. The COM terminal of the FIMV module 14 is connected to one end of the photorelay Kc of the photorelay isolation module 81 of the electrical channel conversion box 8, and the other end of the photorelay Kc is connected to the Cathode terminal of the test material. The FIMV module 14 applies a constant current to the light source LED1 (integrated in the test material) according to the set value. Only the power-on stage (source measurement unit 1) of the FIMV module 14 is used.

[0074] The instruction to supply power to the VCC2 terminal of the material under test is processed by processor 21 and then sent to DAC module 22 as a digital excitation. DAC module 22 converts the digital excitation into an analog excitation and sends it to voltage and current measurement FVMI module 25. The HOT terminal of voltage and current measurement FVMI module 25 is connected to one end of the photorelay Kv of the photorelay isolation module 81 of the electrical channel conversion box 8. The other end of photorelay Kv is connected to the VCC terminal of the gate driver chip of the IGBT under test. The COM terminal of voltage and current measurement FVMI module 25 is connected to one end of the photorelay Ke of the photorelay isolation module 81 of the electrical channel conversion box 8. The other end of photorelay Ke is connected to the VEE terminal of the gate driver chip of the IGBT under test. Voltage and current measurement FVMI module 25 provides a constant voltage to the VCC terminal of the gate driver chip of the IGBT under test according to the set value. Only the FVMI power-on stage (source measurement unit 2) is used.

[0075] The instruction to apply current to the VOUT terminal of the material under test and test the voltage VOH is processed by processor 31 and then sent to DAC 32 as a digital excitation. DAC 32 converts the digital excitation into an analog excitation and sends it to the current-voltage measurement FIMV module 34. The HOT terminal of the current-voltage measurement FIMV module 34 is connected to one end of the opto-relay Ko of the opto-relay isolation module 81 of the electrical channel conversion box 8. The other end of the opto-relay Ko is connected to the VOUT terminal of the material under test. The COM terminal of the current-voltage measurement FIMV module 34 is connected to one end of the opto-relay Ke2 of the opto-relay isolation module 81 of the electrical channel conversion box 8. The other end of the opto-relay Ke2 is connected to the VEE terminal of the material under test. The current-voltage measurement FIMV module 34 applies a constant current to the VOUT terminal of the material under test according to the set value and detects the generated voltage VOH. The value sampled by the current-voltage measurement FIMV module 34 is sent to ADC module 33, converted into a digital response, and then transmitted back to the data processing unit 6 by processor 31 via bus 7. The current-voltage measurement FIMV module 34 is powered on and detected (source measurement unit 33).

[0076] Working principle:

[0077] An IGBT gate driver chip testing system includes an IGBT gate driver chip testing industrial control computer and an electrical channel conversion box. The IGBT gate driver chip testing industrial control computer includes four sets of source measurement units, a signal control unit, and a data processing unit. The electrical channel conversion box 8 includes several opto-relay isolation modules 81 for switching the power-on path of different electrical test items. The source measurement units are composed of a processor, a DAC module, an ADC module, an applied current-to-voltage (FIMV) module, and an applied voltage-to-current (FVMI) module connected together. The data processing unit sends circuit action commands and applied electrical test item excitation parameter commands to the source measurement units via a bus. The source measurement units return the electrical test item response values ​​to the data processing unit via a bus. The source measurement units receive excitation commands and return response values, which is implemented by the processor. The four sets of source measurement units are independent of each other and are only controlled by the data processing unit. The source measurement units can be tested synchronously or asynchronously. The data processing unit sends photorelay control commands to the signal control unit via a bus. After receiving and processing the commands, the signal control unit sends the control signals to the corresponding photorelay modules in the source-measurement electrical channel conversion box via signal lines, controlling the photorelays to turn on or off to select different paths according to different electrical measurement items. The core of the signal control unit is a processor; the data processing unit is a computer.

[0078] The above specific embodiments are specific support for the proposed solution concept of this utility model, and should not be used to limit the protection scope of this utility model. Any equivalent changes or modifications made on the basis of this technical solution in accordance with the technical concept proposed by this utility model shall still fall within the protection scope of this utility model.

Claims

1. A testing system for IGBT gate driver chips, comprising: IGBT gate driver chip testing industrial control computer (10), wherein the IGBT gate driver chip testing industrial control computer (10) is electrically connected to the IGBT gate driver chip under test through an electrical channel conversion box (8), characterized in that: The IGBT gate drive chip test industrial control computer (10) includes several source measurement units, and the source measurement units, signal control unit (5), and data processing unit (6) are interconnected through a bus; The source measurement unit includes a processor, which is electrically connected to the applied current-to-voltage (FIMV) module and the applied voltage-to-current (FVMI) module via a DAC module and an ADC module.

2. The IGBT gate driver chip testing system according to claim 1, characterized in that: The electrical channel conversion box (8) includes an opto-relay isolation module (81); the opto-relay isolation module (81) is used to switch the power supply path for different electrical measurement items.

3. The IGBT gate driver chip testing system according to claim 2, characterized in that: The data processing unit (6) sends circuit operation instructions and electrical measurement item excitation parameter instructions to the source measurement unit through the bus (7); the source measurement unit sends back the electrical measurement item response value to the data processing unit (6) through the bus (7); The processor of the source measurement unit is used to receive excitation commands or transmit response values. Several source measurement units are independent of each other and are controlled only by the data processing unit (6). The source measurement units can be tested synchronously or asynchronously.

4. The IGBT gate driver chip testing system according to claim 3, characterized in that: The data processing unit (6) sends a photorelay control command to the signal control unit (5) via the bus (7); after receiving and processing, the signal control unit (5) sends the control signal to the corresponding photorelay isolation module (81) in the source measurement electrical channel conversion box (8), and the photorelay isolation module (81) controls the corresponding photorelay to be turned on or off in order to achieve the purpose of selecting different paths according to different electrical measurement items.

5. The IGBT gate driver chip testing system according to claim 4, characterized in that: The voltage-to-current (FVMI) module includes: a constant voltage source electrically connected to the DAC module, an operational amplifier (61) electrically connected to the ADC module, and a ground terminal, wherein the ground terminal serves as the COM terminal of the output terminal; The output terminal of the constant voltage source is connected to one end of the sampling resistor Rs2. The other end of the sampling resistor Rs2 is led out as the HOT terminal. The connection node between the sampling resistor Rs2 and the constant voltage source is connected to the inverting terminal of the operational amplifier (61) through attenuator one (511). The HOT terminal of the sampling resistor Rs2 is connected to the non-inverting terminal of the operational amplifier (61) through buffer one (311) and attenuator two (411) connected in series.

6. The IGBT gate driver chip testing system according to claim 5, characterized in that: The applied current-to-voltage FIMV module includes: a constant current source electrically connected to the DAC module, and an operational amplifier II (62) electrically connected to the ADC module. The output of the constant current source is led out as the HOT terminal, and the output of the constant current source is also connected to the inverting terminal of the operational amplifier two (62) through the series-connected buffer two (312) and attenuator three (512). The non-inverting terminal of the operational amplifier two (62) is led out as the COM terminal through attenuator four (412).

7. The IGBT gate driver chip testing system according to claim 6, characterized in that: When selecting the VOH test item, several source measurement units include source measurement unit one (1), source measurement unit two (2), and source measurement unit three (3). The DAC module 12 of the source measurement unit 1 (1) is connected to the electrical channel conversion box (8) through the current-voltage measurement FIMV module 14 of the source measurement unit 1 (1). The HOT terminal of the current-voltage measurement FIMV module 14 is connected to one end of the photorelay Ka, and the other end of the photorelay Ka is connected to the sampling terminal of the light source of the IGBT gate driver chip under test. The COM terminal of the current-voltage measurement FIMV module 14 is connected to one end of the photorelay Kc of the electrical channel conversion box (8), and the other end of the photorelay Kc is connected to the other sampling terminal of the IGBT gate driver chip under test. The DAC module 2 (22) of the source measurement unit 2 (2) is connected to the electrical channel conversion box (8) through the voltage-to-current measurement FVMI module 2 (25) of the source measurement unit 2 (2). The HOT terminal of the voltage-to-current measurement FVMI module 2 (25) is connected to one end of the opto-relay Kv of the electrical channel conversion box (8), and the other end of the opto-relay Kv is connected to the VCC terminal of the gate driver chip of the IGBT under test. The COM terminal of the voltage-to-current measurement FVMI module 2 (25) is connected to one end of the opto-relay Ke of the electrical channel conversion box (8), and the other end of the opto-relay Ke is connected to the VEE terminal of the gate driver chip of the IGBT under test. The DAC module three (32) and ADC module three (33) of the source measurement unit three (3) are respectively connected to the electrical channel conversion box (8) through the voltage-to-current measurement FVMI module three (34) of the source measurement unit three (3). The HOT terminal of the voltage-to-current measurement FVMI module three (34) is connected to one end of the opto-relay Ko of the electrical channel conversion box (8), and the other end of the opto-relay Ko is connected to the VOUT output terminal of the gate driver chip of the IGBT under test. The COM terminal of the voltage-to-current measurement FVMI module three (34) is connected to one end of the opto-relay Ke2 of the electrical channel conversion box (8), and the other end of the opto-relay Ke2 is connected to the VEE terminal of the gate driver chip of the IGBT under test.

8. The IGBT gate driver chip testing system according to claim 7, characterized in that: When the ICCL test item is selected, the DAC module 2 (22) and ADC module 2 (23) of the source measurement unit 2 (2) are connected to the electrical channel conversion box (8) through the voltage-to-current measurement FVMI module 2 (25) of the source measurement unit 2 (2). The HOT terminal of the voltage-to-current measurement FVMI module 2 (25) is connected to one end of the opto-relay Kv of the electrical channel conversion box (8), and the other end of the opto-relay Kv is connected to the VCC terminal of the gate driver chip of the IGBT under test. The COM terminal of the voltage-to-current measurement FVMI module 2 (25) is connected to one end of the opto-relay Ke of the electrical channel conversion box (8), and the other end of the opto-relay Ke is connected to the VEE terminal of the gate driver chip of the IGBT under test.

9. The IGBT gate driver chip testing system according to claim 6, characterized in that: The constant voltage source and constant current source use the OPA548 chip; And / or, the attenuator one (511), attenuator two (411), attenuator three (512), and attenuator four (412) are all resistor voltage divider attenuators; the resistor voltage divider attenuator includes resistors R1 and R2 connected in series, one end of resistor R1 is the U0 end, the U0 end is the original voltage connected to the sampling resistor Rs2, and the connection node of resistors R1 and R2 leads out one path to the U1 end, the U1 end is the attenuated voltage; and U1=U0*[R2 / (R1+R2)].

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