Double-channel CPU (central processing unit) server mainboard

Abstract

The utility model provides a double-channel CPU (central processing unit) server mainboard, which is applied to the technical field of server mainboards. The double-channel CPU server mainboard comprises a first CPU and a second CPU, the second CPU is connected with the first CPU; a PCH chip, wherein the PCH chip is connected with the first CPU; the DDR5 memory slot group comprises a plurality of DDR5 memory slots, and the plurality of DDR5 memory slots are connected with the second CPU and the first CPU; the MCIO interface group comprises a plurality of MCIO interfaces, and the plurality of MCIO interfaces are connected with the second CPU and the first CPU; and an OCP NIC 3.0 interface, wherein the OCP NIC 3.0 interface is connected with the first CPU. The utility model aims to improve the performance of the double-channel CPU server mainboard.

Description

Technical Field

[0001] This utility model relates to the field of server motherboard technology, and in particular to a dual-CPU server motherboard. Background Technology

[0002] A dual-CPU server motherboard is a motherboard architecture designed to house two processors. These two processors can execute tasks in parallel and independently, playing a crucial role in improving the overall computing performance of the server.

[0003] Although traditional dual-CPU server motherboards support multi-channel operation, their ability to maintain stable system operation remains poor in complex scenarios such as the deep application of virtualization technology and the massive demands of big data processing. Furthermore, the PCIe slot configuration on traditional dual-CPU server motherboards also limits their expandability to some extent. Therefore, traditional dual-CPU server motherboards suffer from technical issues related to performance limitations. Utility Model Content

[0004] This application proposes a dual-CPU server motherboard, aiming to solve the technical problem of how to improve the performance of a dual-CPU server motherboard.

[0005] To address the aforementioned problems, this application proposes a dual-CPU server motherboard, which includes:

[0006] First CPU;

[0007] A second CPU, which is connected to the first CPU;

[0008] The PCH chip is connected to the first CPU;

[0009] A DDR5 memory slot group, comprising a first memory slot unit and a second memory slot unit, wherein the first memory slot unit is connected to the second CPU, the second memory slot unit is connected to the first CPU, and both the first memory slot unit and the second memory slot unit include multiple DDR5 memory slots;

[0010] An MCIO interface group, comprising a first MCIO interface unit and a second MCIO interface unit, wherein the first MCIO interface unit is connected to the second CPU, and the second MCIO interface unit is connected to the first CPU, and both the first MCIO interface unit and the second MCIO interface unit include multiple MCIO interfaces;

[0011] The OCP NIC 3.0 interface is connected to the first CPU.

[0012] In one embodiment, the dual-CPU server motherboard further includes:

[0013] The first Riser card slot is connected to the second CPU.

[0014] The second Riser card slot is connected to the first CPU.

[0015] In one embodiment, the dual-CPU server motherboard further includes:

[0016] MiniSAS interface group, the MiniSAS interface group includes multiple MiniSAS interfaces, each of the MiniSAS interfaces is connected to the PCH chip;

[0017] The M.2 Key-M interface group includes multiple M.2 Key-M interfaces, each of which is connected to the PCH chip.

[0018] In one embodiment, the dual-CPU server motherboard further includes:

[0019] The first USB interface group includes various USB 2.0 TYPE-A interfaces, each of which is connected to the PCH chip;

[0020] The second USB interface group includes various USB 2.0 dual-header interfaces, each of which is connected to the PCH chip.

[0021] In one embodiment, the dual-CPU server motherboard further includes:

[0022] A network interface card (NIC) chipset, wherein the NIC chipset includes individual NIC chips, and each NIC chip is connected to the PCH chip;

[0023] A network port group, which includes various network interfaces, each of which is connected to a network card chip.

[0024] In one embodiment, the dual-CPU server motherboard further includes:

[0025] The BMC chip is connected to the PCH chip and the network interface card chipset.

[0026] In one embodiment, the dual-CPU server motherboard further includes:

[0027] A VGA display interface is connected to the BMC chip.

[0028] A fan interface is provided, which is connected to the BMC chip.

[0029] In one embodiment, the dual-CPU server motherboard further includes:

[0030] An unpacking detection interface is provided, which is connected to the BMC chip.

[0031] In one embodiment, the dual-CPU server motherboard further includes:

[0032] The RS232 serial port is connected to the BMC chip.

[0033] In one embodiment, the dual-CPU server motherboard further includes:

[0034] Main power supply;

[0035] A backup power supply, the negative terminal of which is connected to the negative terminal of the main power supply;

[0036] A first diode, the positive terminal of which is connected to the positive terminal of the main power supply;

[0037] The second diode has its anode connected to the anode of the backup power supply, and its cathode connected to the cathode of the first diode, the second CPU, the first CPU, the PCH chip, each of the DDR5 memory slots, each of the MCIO interfaces, and the OCP NIC 3.0 interface.

[0038] The dual-CPU server motherboard proposed in this application includes: a first CPU; a second CPU connected to the first CPU; a PCH chip connected to the first CPU; a DDR5 memory slot group, the DDR5 memory slot group including a first memory slot unit and a second memory slot unit, the first memory slot unit being connected to the second CPU, the second memory slot unit being connected to the first CPU, and both the first memory slot unit and the second memory slot unit including multiple DDR5 memory slots; an MCIO interface group, the MCIO interface group including a first MCIO interface unit and a second MCIO interface unit, the first MCIO interface unit being connected to the second CPU, the second MCIO interface unit being connected to the first CPU, and both the first MCIO interface unit and the second MCIO interface unit including multiple MCIO interfaces; and an OCP NIC 3.0 interface connected to the first CPU.

[0039] This application features multiple DDR5 memory slots to support the memory requirements of a dual-socket server; multiple MCIO interfaces save motherboard space while increasing data transmission bandwidth; a connection between the first CPU and the PCH chip enhances the overall response speed and data processing capabilities of the motherboard; and the OCP NIC 3.0 interface reduces the physical footprint of network interface cards and increases the overall server density. Therefore, this application improves the performance of a dual-socket CPU server motherboard by integrating DDR5 memory slots, MCIO interfaces, a PCH chip, and an OCP NIC 3.0 interface onto the motherboard. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the module connections in the first embodiment of the dual-CPU server motherboard of this application;

[0042] Figure 2 This is a schematic diagram of the module connections in the second embodiment of the dual-CPU server motherboard of this application;

[0043] Figure 3 This is a schematic diagram of the module connections in the third embodiment of the dual-CPU server motherboard of this application;

[0044] Figure 4 This is a schematic diagram of the module connections in the fourth embodiment of the dual-CPU server motherboard of this application;

[0045] Figure 5 This is a power connection diagram of an embodiment of a dual-CPU server motherboard according to this application.

[0046] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0047] Explanation of icon numbers:

[0048] 10. First CPU; 20. Second CPU; 30. PCH chip; 401. First memory slot unit; 402. Second memory slot unit; 501. First MCIO interface unit; 502. Second MCIO interface unit; 60. OCP NIC 3.0 interface; 70. First Riser card slot; 80. Second Riser card slot; 90. MiniSAS interface group; 100. M.2 Key-M interface group; 110. First USB interface group; 120. Second USB interface group; 130. Network card chipset; 140. Network port group; 150. BMC chip; 160. VGA display interface; 170. Fan interface; 180. Unpacking detection interface; 190. RS232 serial port. Detailed Implementation

[0049] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. If the embodiments of the present utility model involve descriptions such as "first" or "second", such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of such features.

[0050] This application proposes a dual-CPU server motherboard, aiming to solve the technical problem of how to improve the performance of a dual-CPU server motherboard.

[0051] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the module connections in the first embodiment of the dual-CPU server motherboard of this application. Figure 1 As shown, the dual-CPU server motherboard proposed in this application includes:

[0052] First CPU 10;

[0053] The second CPU 20 is connected to the first CPU 10;

[0054] PCH chip 30, which is connected to the first CPU 10;

[0055] A DDR5 memory slot group 40 includes a first memory slot unit 401 and a second memory slot unit 402. The first memory slot unit 401 is connected to the second CPU 20, and the second memory slot unit 402 is connected to the first CPU 10. Both the first memory slot unit 401 and the second memory slot unit 402 include multiple DDR5 memory slots.

[0056] MCIO interface group 50, the MCIO interface group 50 includes a first MCIO interface unit 501 and a second MCIO interface unit 502, the first MCIO interface unit 501 is connected to the second CPU 20, the second MCIO interface unit 502 is connected to the first CPU 10, and both the first MCIO interface unit 501 and the second MCIO interface unit 502 include multiple MCIO interfaces.

[0057] OCP NIC 3.0 interface 60, which is connected to the first CPU 10.

[0058] In this embodiment, the PCH chip 30 is used to connect peripherals, and the second CPU 20 and the first CPU 10 are the data processing center. Specifically, the second CPU 20 and the first CPU 10 can be Intel Xeon fourth-generation Scalable processors. Therefore, the multitasking capabilities and high performance of the second CPU 20 and the first CPU 10 can meet the needs of large-scale computing and data-intensive applications on a dual-CPU server motherboard. Furthermore, the second CPU 20 and the first CPU 10 can communicate via four sets of UPI buses, and the first CPU 10 communicates with the PCH chip 30 via the DMI bus, which can improve the overall response speed and processing power of the dual-CPU server motherboard.

[0059] In this embodiment, the first MCIO interface unit 501 may include eight MCIO interfaces, and the second MCIO interface unit 502 may include six MCIO interfaces. The MCIO interfaces can be connected to the CPU via the PCIe bus. It is understood that because the size of the MCIO interface is relatively small compared to a traditional PCIe slot, the MCIO interface in this application occupies a smaller area on the board, thereby saving space on the dual-CPU server motherboard while increasing data transmission bandwidth. Furthermore, signals between the CPU and the MCIO interface can be transmitted via cable to improve the motherboard's horizontal scalability. In addition, in this application, each MCIO interface can provide one set of PCIe 8X Gen5 high-speed resources to further improve the motherboard's data transmission efficiency.

[0060] In this embodiment, the dual-socket server motherboard proposed in this application can also adopt an eight-channel 2DPC design, providing 32 DDR5 memory slots. These DDR5 memory slots can be connected to the CPU via AH channels. Since the maximum supported memory capacity of the DDR5 memory slots is 8TB, the multiple DDR5 memory slots specified in this application can support the large-scale memory requirements of a dual-socket CPU server motherboard.

[0061] In this embodiment, the OCP NIC 3.0 interface 60 can be connected to the CPU via the PCIe bus. Furthermore, the OCP NIC 3.0 interface 60 can provide a set of PCIe 16X Gen5 signals for high-speed data transmission, and it also supports high-speed Ethernet connectivity. Therefore, connecting to the OCP NIC 3.0 interface 60 can meet the high-bandwidth, low-latency network requirements of dual-CPU server motherboards. Moreover, the OCP NIC 3.0 interface 60 also supports iSCSI and FCoE protocols, making it suitable for large-scale storage virtualization scenarios in dual-CPU server motherboards. In addition, compared to traditional network interface cards, the OCP NIC 3.0 card is smaller, further optimizing internal motherboard space, reducing physical footprint, and increasing overall server density. Furthermore, the OCP NIC 3.0 interface 60 has a high data transmission rate, meeting the bandwidth requirements of high-speed networks and storage devices, and reducing data transmission latency, making it suitable for data-intensive applications.

[0062] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the module connections for a second embodiment of the dual-CPU server motherboard of this application. In this embodiment, the dual-CPU server motherboard further includes:

[0063] The first Riser card slot 70 is connected to the second CPU 20;

[0064] The second Riser card slot 80 is connected to the first CPU 10.

[0065] In one feasible implementation, the dual-CPU server motherboard further includes:

[0066] MiniSAS interface group 90, the MiniSAS interface group 90 includes multiple MiniSAS interfaces, each of the MiniSAS interfaces is connected to the PCH chip 30;

[0067] M.2 Key-M interface group 100, the M.2 Key-M interface group 100 includes multiple M.2 Key-M interfaces, each of which is connected to the PCH chip 30.

[0068] In one feasible implementation, the dual-CPU server motherboard further includes:

[0069] The first USB interface group 110 includes various USB 2.0 TYPE-A interfaces, each of which is connected to the PCH chip 30.

[0070] The second USB interface group 120 includes various USB 2.0 dual-header interfaces, each of which is connected to the PCH chip 30.

[0071] In this embodiment, both the first Riser card slot 70 and the second Riser card slot 80 provide a set of PCIe 16X Gen5 signals and are connected to the CPU via the PCIE bus, thereby further improving the vertical space utilization of the dual-CPU server motherboard and thus enhancing the expandability of the motherboard and the flexibility of device installation.

[0072] In this embodiment, the MiniSAS interface is connected to the PCH chip 30 via the SATA bus to expand the storage space of the dual-CPU server motherboard. Specifically, the MiniSAS interface can support cascading connections of multiple devices, allowing multiple hard drives or storage devices to be connected through a single interface. In one feasible implementation, the dual-CPU server motherboard can be equipped with three MiniSAS 4i interfaces, providing a total of 12 SATA 3.0 signals to enhance the capacity and expandability of the motherboard's storage space.

[0073] In this embodiment, the M.2 Key-M interface is connected to the PCH chip 30 via the PCIe bus to improve data read and write speed. In one feasible implementation, each M.2 Key-M interface may contain one set of PCIe 2X signals.

[0074] In this embodiment, the USB 2.0 Type-A interface and the USB 2.0 dual-header interface are used to connect peripherals, thereby improving the scenario adaptability of the dual-CPU server motherboard of this application. Specifically, in one feasible implementation, the dual-CPU server motherboard may be equipped with three USB 2.0 Type-A interfaces and four sets of USB 2.0 dual-header interfaces.

[0075] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the module connections for a third embodiment of the dual-CPU server motherboard of this application. In this embodiment, the dual-CPU server motherboard further includes:

[0076] A network interface card (NIC) chipset 130, wherein the NIC chipset 130 includes various NIC chips, and each NIC chip is connected to the PCH chip 30;

[0077] The network port group 140 includes various network interfaces, each of which is connected to a network card chip.

[0078] In this embodiment, the network interface card (NIC) chip and network interface are used for communication between devices. Specifically, the NIC chip can be connected to the PCH chip 30 via a PCIe bus. In one feasible implementation, the NIC chipset 130 may include a 2.5GbE NIC chip and a 1GbE NIC chip, and the network port group 140 may include an RJ45 type 2.5GbE network port and an RJ45 type IPMI GbE network port.

[0079] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the module connections in the fourth embodiment of the dual-CPU server motherboard of this application. In one feasible implementation, the dual-CPU server motherboard further includes:

[0080] BMC chip 150 is connected to PCH chip 30 and network card chip group 130.

[0081] In one feasible implementation, the dual-CPU server motherboard further includes:

[0082] VGA display interface 160, which is connected to the BMC chip 150;

[0083] Fan interface 170 is connected to BMC chip 150.

[0084] In one feasible implementation, the dual-CPU server motherboard further includes:

[0085] An unpacking detection interface 180 is provided, which is connected to the BMC chip 150.

[0086] In one feasible implementation, the dual-CPU server motherboard further includes:

[0087] RS232 serial port 190 is connected to the BMC chip 150.

[0088] In this embodiment, the BMC chip 150 has remote and out-of-band management functions, which facilitates the use and maintenance of large numbers of servers. Furthermore, the BMC chip 150 allows administrators to remotely access the server via the network to monitor system hardware status and perform fault diagnosis, thereby improving management efficiency. In addition, the management functions of the BMC chip 150 are typically separated from the operating system, so the BMC chip 150 can still operate normally even if the operating system fails to boot. In this embodiment, the BMC chip 150 communicates with the PCH chip 30 via the ESPI bus, PCIe signal, and USB 2.0 signal, realizing system management and remote control functions. The BMC chip 150 is connected to one VGA display interface 160, two RS232 serial ports 190, ten FAN fan interfaces 170, and one unpacking detection interface 180.

[0089] Specifically, the VGA display interface 160 uses a traditional DB15 interface to output the data to be displayed; the RS232 serial port 190 is used to connect to external serial devices; the fan interface 170 is used to connect to the cooling fan inside the chassis, providing power and control signals to the fan to control and monitor the fan speed and ensure heat dissipation inside the computer; and the unpacking detection interface 180 is used to detect whether the chassis has been opened.

[0090] Please refer to Figure 5 , Figure 5 This is a power connection diagram of an embodiment of a dual-CPU server motherboard according to this application. In this embodiment, the dual-CPU server motherboard further includes:

[0091] Main power supply 200;

[0092] Backup power supply 210, the negative terminal of which is connected to the negative terminal of main power supply 200;

[0093] A first diode 220, the positive terminal of which is connected to the positive terminal of the main power supply 200;

[0094] The second diode 230 has its anode connected to the anode of the backup power supply 210, and its cathode connected to the cathode of the first diode 220, the second CPU 20, the first CPU 10, the PCH chip 30, each of the DDR5 memory slots, each of the MCIO interfaces, and the OCP NIC 3.0 interface 60.

[0095] In this embodiment, when the main power supply 200 is operating normally, the voltage of the main power supply 200 is higher than that of the backup power supply 210, so the first diode 220 corresponding to the main power supply 200 is turned on to supply power to the devices that need power; when the main power supply 200 fails and the voltage of the main power supply 200 drops, the second diode 230 corresponding to the backup power supply 210 is turned on to take over the power supply from the main power supply 200 to supply power to the devices that need power.

[0096] Therefore, the dual-redundant power input method adopted in this application can maintain the normal operation of the dual-CPU server motherboard through the backup power supply 210 when a single power supply fails, thereby effectively improving the reliability and stability of the power supply.

[0097] The above are merely optional embodiments of this utility model and do not limit the patent scope of this utility model. All equivalent structural transformations made based on the contents of this utility model specification and drawings under the utility model concept, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this utility model.

Claims

1. A dual-CPU server motherboard, characterized in that, The dual-CPU server motherboard includes: First CPU; A second CPU, which is connected to the first CPU; The PCH chip is connected to the first CPU; A DDR5 memory slot group, comprising a first memory slot unit and a second memory slot unit, wherein the first memory slot unit is connected to the second CPU, the second memory slot unit is connected to the first CPU, and both the first memory slot unit and the second memory slot unit include multiple DDR5 memory slots; An MCIO interface group, comprising a first MCIO interface unit and a second MCIO interface unit, wherein the first MCIO interface unit is connected to the second CPU, and the second MCIO interface unit is connected to the first CPU, and both the first MCIO interface unit and the second MCIO interface unit include multiple MCIO interfaces; The OCP NIC 3.0 interface is connected to the first CPU.

2. The dual-CPU server motherboard as described in claim 1, characterized in that, The dual-CPU server motherboard also includes: The first Riser card slot is connected to the second CPU. The second Riser card slot is connected to the first CPU.

3. The dual-CPU server motherboard as described in claim 1, characterized in that, The dual-CPU server motherboard also includes: MiniSAS interface group, the MiniSAS interface group includes multiple MiniSAS interfaces, each of the MiniSAS interfaces is connected to the PCH chip; The M.2 Key-M interface group includes multiple M.2 Key-M interfaces, each of which is connected to the PCH chip.

4. The dual-CPU server motherboard as described in claim 1, characterized in that, The dual-CPU server motherboard also includes: The first USB interface group includes various USB 2.0 TYPE-A interfaces, each of which is connected to the PCH chip; The second USB interface group includes various USB 2.0 dual-header interfaces, each of which is connected to the PCH chip.

5. The dual-CPU server motherboard as described in claim 1, characterized in that, The dual-CPU server motherboard also includes: A network interface card (NIC) chipset, wherein the NIC chipset includes individual NIC chips, and each NIC chip is connected to the PCH chip; A network port group, which includes various network interfaces, each of which is connected to a network card chip.

6. The dual-CPU server motherboard as described in claim 5, characterized in that, The dual-CPU server motherboard also includes: The BMC chip is connected to the PCH chip and the network interface card chipset.

7. The dual-CPU server motherboard as described in claim 6, characterized in that, The dual-CPU server motherboard also includes: A VGA display interface is connected to the BMC chip. A fan interface is provided, which is connected to the BMC chip.

8. The dual-CPU server motherboard as described in claim 6, characterized in that, The dual-CPU server motherboard also includes: An unpacking detection interface is provided, which is connected to the BMC chip.

9. The dual-CPU server motherboard as described in claim 6, characterized in that, The dual-CPU server motherboard also includes: The RS232 serial port is connected to the BMC chip.

10. The dual-CPU server motherboard as described in claim 1, characterized in that, The dual-CPU server motherboard also includes: Main power supply; A backup power supply, the negative terminal of which is connected to the negative terminal of the main power supply; A first diode, the positive terminal of which is connected to the positive terminal of the main power supply; The second diode has its anode connected to the anode of the backup power supply, and its cathode connected to the cathode of the first diode, the second CPU, the first CPU, the PCH chip, each of the DDR5 memory slots, each of the MCIO interfaces, and the OCP NIC 3.0 interface.

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