Packaging structure of semiconductor module

Abstract

The utility model discloses a packaging structure of a semiconductor module, and belongs to the technical field of module packaging. Comprising a copper-clad ceramic substrate; the at least two semiconductor chips are arranged on the copper-clad ceramic substrate; a bonding wire connected between the semiconductor chips; and the composite coating is arranged on the upper surface of the copper-clad ceramic substrate, the surface of the semiconductor chip and the surface of the bonding wire. The technical scheme has the beneficial effects that the composite coating is additionally arranged on the substrate, so that the layering condition can be effectively reduced, the difference of thermal expansion coefficients among materials is effectively reduced, and the reliability and the stability of the whole module packaging are improved.

Description

Technical Field

[0001] This utility model relates to the field of module packaging technology, and in particular to a packaging structure. Background Technology

[0002] With the goal of carbon neutrality and the advancement of related technological innovations, power modules, due to their advantages such as high integration, high reliability, energy saving, and environmental friendliness, have been widely used in various fields, including solar power generation, rail transportation, electric drives, and motor control. Furthermore, power modules also play a crucial role in drive control applications such as automotive drives, hybrid power systems, wind power, welding equipment, and locomotive traction.

[0003] In high-temperature applications, traditional power modules are typically soldered onto a PCB (printed circuit board). Due to differences in the coefficients of thermal expansion (CTE) between the materials, cracks of varying degrees often occur, affecting overall reliability. Furthermore, differences in physical properties between the DBC (copper-on-chip) and electronic module materials (such as EMC) can lead to delamination between the DBC and other components, reducing overall module reliability and, in severe cases, even causing module failure. Utility Model Content

[0004] The purpose of this utility model is to provide a packaging structure for a semiconductor module to solve the above-mentioned technical problems;

[0005] A semiconductor module packaging structure, comprising,

[0006] Copper-clad ceramic substrate;

[0007] At least two semiconductor chips are disposed on the copper-clad ceramic substrate;

[0008] Bonding wires connect the semiconductor chips;

[0009] A composite coating is applied to the upper surface of the copper-clad ceramic substrate, the surface of the semiconductor chip, and the surface of the bonding wire.

[0010] Preferably, the thickness of the composite coating is 10 μm to 200 μm.

[0011] Preferably, the porosity of the composite coating is 0-1%.

[0012] Preferably, it further includes a housing, which is connected to the back side of the copper-clad ceramic substrate and forms an accommodating space with the copper-clad ceramic substrate. The accommodating space contains the copper-clad ceramic substrate, the semiconductor chip, the bonding wire, and the composite coating.

[0013] Preferably, the accommodating space further includes a lead frame, which is connected to the bonding wire.

[0014] Preferably, the outer casing is an EMC encapsulated casing.

[0015] Preferably, the outer shell is a one-piece injection molded structure.

[0016] Preferably, the copper-clad ceramic substrate comprises,

[0017] First copper layer substrate;

[0018] A ceramic substrate is disposed above the first copper layer substrate;

[0019] The second copper layer substrate is disposed above the ceramic substrate.

[0020] Preferably, a plasma layer is provided between the composite coating and the copper-clad ceramic substrate, the semiconductor chip, and the bonding wire, respectively.

[0021] Preferably, the surface of the encapsulation structure is provided with the plasma layer.

[0022] The beneficial effects of this invention are: adding a composite coating to the substrate can effectively reduce delamination, effectively reduce the difference in thermal expansion coefficients between materials, and improve the reliability and stability of the overall module packaging. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the packaging structure of the semiconductor module of this utility model;

[0024] Figure 2 This is a schematic diagram of the plasma cleaning process before applying the composite coating according to this utility model;

[0025] Figure 3 This is a schematic diagram of plasma cleaning before mold forming, which is a feature of this invention.

[0026] In the attached figures: 1. Copper-clad ceramic substrate; 11. First copper layer substrate; 12. Ceramic substrate; 13. Second copper layer substrate; 2. Semiconductor chip; 3. Bonding wire; 4. Composite coating; 5. Housing; 6. Electrode plate; 7. Lead frame. Detailed Implementation

[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0029] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0030] A semiconductor module packaging structure, as shown in Figure 1, includes,

[0031] Copper-clad ceramic substrate 1;

[0032] At least two semiconductor chips 2 are disposed on a copper-clad ceramic substrate 1;

[0033] Bonding wire 3 connects the semiconductor chips 2;

[0034] The composite coating 4 is applied to the upper surface of the copper-clad ceramic substrate 1, the surface of the semiconductor chip 2, and the surface of the bonding wire 3.

[0035] Specifically, this utility model provides a semiconductor module packaging structure that combines a semiconductor chip 2, bonding wires 3, and a composite coating 4, resulting in stronger bonding and better consistency among the components. The composite coating 4 effectively reduces delamination and the difference in thermal expansion coefficients between materials, thereby improving the overall reliability and stability of the module packaging.

[0036] In a preferred embodiment, the thickness of the composite coating 4 is 10 μm to 200 μm.

[0037] Specifically, the thickness of the composite coating 4 helps to regulate the thermal conductivity of the module. The semiconductor chip 2 generates heat during operation. If the packaging is poor, the heat cannot be effectively dissipated, which may lead to overheating of the chip and reduce its performance or lifespan. By controlling the thickness of the composite coating 4, heat flow can be improved, temperature unevenness can be avoided, and the overall thermal management performance of the module can be improved.

[0038] A coating thickness of 10μm to 200μm can reduce stress concentration caused by the difference in thermal expansion between the semiconductor chip 2 and other materials. When different materials expand or contract due to temperature changes, the coating thickness can act as a buffer, reducing structural damage or cracks caused by thermal stress.

[0039] The thickness of the composite coating 4, ranging from 10μm to 200μm, provides better protection, preventing external factors such as impact and vibration from affecting the integrity of the package.

[0040] In a preferred embodiment, the porosity of the composite coating 4 is 0 to 1%.

[0041] Specifically, porosity refers to the volume percentage of micropores in a coating, and it directly affects the performance of the coating. Coatings with low porosity can effectively isolate external environmental factors such as moisture and oxygen, preventing them from corroding the semiconductor chip or degrading its electrical performance.

[0042] Coating materials with low porosity have more uniform thermal expansion characteristics, which can effectively alleviate the stress caused by the difference in thermal expansion coefficients between different materials and reduce the risk of cracking and failure.

[0043] In a preferred embodiment, it further includes a housing 5, which is connected to the back side of the copper-clad ceramic substrate 1 and forms an accommodating space with the copper-clad ceramic substrate 1. The accommodating space is provided with the copper-clad ceramic substrate 1, the semiconductor chip 2, the bonding wire 3 and the composite coating 4.

[0044] The housing also includes a lead frame 7, which is connected to the bonding wire 3, providing a robust electrical connection and mechanical support, which helps improve the overall system performance and reduce the possibility of electrical connection failures.

[0045] Outer shell 5 is an EMC-encapsulated outer shell;

[0046] The outer shell 5 is a one-piece injection molded structure.

[0047] Specifically, the EMC-encapsulated housing is designed with electromagnetic compatibility in mind, effectively shielding against external electromagnetic interference and preventing external electromagnetic waves from affecting the internal circuitry of the module. Simultaneously, the housing 5 also prevents electromagnetic waves generated by the internal circuitry of the module from leaking out, complying with electromagnetic compatibility standards.

[0048] Injection molding improves the sealing of the outer shell 5, preventing leakage current or radiation and enhancing the overall system's electromagnetic interference resistance.

[0049] Using injection molding as a one-piece molding process simplifies the production process and reduces manufacturing steps and costs. Furthermore, one-piece injection molding helps reduce material waste and allows for the production of shells of different sizes by adjusting the injection mold, thereby saving on raw material and mold adjustment costs.

[0050] In a preferred embodiment, the copper-clad ceramic substrate 1 includes,

[0051] First copper layer substrate 11;

[0052] A ceramic substrate 12 is disposed above the first copper layer substrate 11;

[0053] The second copper layer substrate 13 is disposed above the ceramic substrate 12.

[0054] Specifically, the copper-clad ceramic substrate 1 comprises a combination of a copper layer and a ceramic layer, which enables the optimization of various properties, including excellent thermal management, electrical performance, mechanical strength, and stability. The combination of the copper and ceramic layers simplifies the manufacturing process. The copper layer can be directly bonded to the ceramic substrate 12 through chemical or electroplating processes, avoiding the complex processes of multi-layer welding or bonding, thus reducing production costs and technical difficulties.

[0055] In a preferred embodiment, a plasma layer is provided between the composite coating 4 and the copper-clad ceramic substrate 1, the semiconductor chip 2, and the bonding wire 3, respectively.

[0056] Specifically, before applying the composite coating 4, refer to Figure 2 By placing electrode plates 6 at the top and bottom of the packaging structure and performing plasma cleaning, the surface hydrophilicity is increased. The composite coating 4 is sprayed within 30 minutes after plasma cleaning, which improves the adhesion of the coating to the copper-clad ceramic substrate 1, semiconductor chip 2 and bonding wire 3. The cleaning power is 30kw to 400kw.

[0057] In a preferred embodiment, the surface of the encapsulation structure is provided with a plasma layer.

[0058] Specifically, refer to Figure 3 After applying the composite coating 4 and before module encapsulation, the coating is cured in an oxygen-free baking oven at a temperature of 120℃~235℃. Then, electrode plates 6 are placed on the upper and lower positions of the encapsulation structure and plasma cleaning is performed to increase the hydrophilicity of the composite coating 4. Mold forming is performed within 30 minutes after plasma cleaning. The power of plasma cleaning is 30kw~200kw.

[0059] Meanwhile, the coating has a higher bonding strength with the semiconductor chip 2 and the outer shell 5 than the bonding strength between the two, reducing the phenomenon of delamination of the plastic shell after high temperature. It can also effectively prevent easily oxidized substrates before plastic encapsulation, and is suitable for most plastic-encapsulated power modules.

[0060] The above description is only a preferred embodiment of the present utility model and does not limit the implementation method and protection scope of the present utility model. Those skilled in the art should realize that all solutions obtained by equivalent substitutions and obvious changes made based on the description and illustrations of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A packaging structure for a semiconductor module, characterized in that, include, Copper-clad ceramic substrate; At least two semiconductor chips are disposed on the copper-clad ceramic substrate; Bonding wires connect the semiconductor chips; A composite coating is applied to the upper surface of the copper-clad ceramic substrate, the surface of the semiconductor chip, and the surface of the bonding wire.

2. The packaging structure of the semiconductor module according to claim 1, characterized in that, The thickness of the composite coating is 10μm to 200μm.

3. The packaging structure of the semiconductor module according to claim 1, characterized in that, The porosity of the composite coating is 0-1%.

4. The packaging structure of the semiconductor module according to claim 1, characterized in that, It also includes a housing, which is connected to the back of the copper-clad ceramic substrate and forms an accommodating space with the copper-clad ceramic substrate. The accommodating space contains the copper-clad ceramic substrate, the semiconductor chip, the bonding wire, and the composite coating.

5. The packaging structure of the semiconductor module according to claim 4, characterized in that, The accommodating space also includes a lead frame, which is connected to the bonding wire.

6. The packaging structure of the semiconductor module according to claim 4, characterized in that, The outer casing is an EMC encapsulated casing.

7. The packaging structure of the semiconductor module according to claim 4, characterized in that, The outer shell is a one-piece injection molded structure.

8. The packaging structure of the semiconductor module according to claim 1, characterized in that, The copper-clad ceramic substrate includes, First copper layer substrate; A ceramic substrate is disposed above the first copper layer substrate; The second copper layer substrate is disposed above the ceramic substrate.

9. The packaging structure of the semiconductor module according to claim 1, characterized in that, The composite coating is provided with a plasma layer between itself and the copper-clad ceramic substrate, the semiconductor chip, and the bonding wire.

10. The packaging structure of the semiconductor module according to claim 9, characterized in that, The surface of the encapsulation structure is provided with the plasma layer.

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