Chip packaging unit with double-sided rewiring layer

Abstract

The utility model discloses a chip packaging unit with double-sided rewiring layers, the chip packaging unit is formed by cutting a wafer, and the chip packaging unit comprises a chip, a first rewiring layer, a second rewiring layer and at least one side surface connecting line; wherein the chip is electrically connected with a plurality of external connecting bodies on each second guide connecting circuit through a plurality of crystal pads, each first guide connecting circuit, each side surface connecting circuit and each second guide connecting circuit of the chip in sequence, and then is externally and electrically connected through each external connecting body; the problem that the circuit layer design of an existing wafer is relatively complicated is solved through the rewiring layer technology, the structure thickness is reduced, the trend of pursuing light, thin, short and small products is met, the silicon through hole technology is prevented from being used on the structure, and the manufacturing cost of a manufacturing end is reduced.

Description

Technical Field

[0001] This utility model relates to a chip packaging unit, and more particularly to a chip packaging unit with a double-sided redistribution layer. Background Technology

[0002] In the field of chip packaging, an existing chip packaging unit uses multiple layers of circuitry to electrically connect the internal chip to one surface of the chip packaging unit and to the outside. As a result, the circuitry design of the existing chip packaging unit is relatively complex, and the overall thickness of the existing chip packaging unit is relatively thick due to the design of multiple circuitry layers. This makes it impossible to meet the current trend of pursuing thinner and smaller chip packaging products, and it is also not easy to reduce manufacturing costs.

[0003] In addition, through-silicon via (TSV) technology is also used to form multiple vias on the chip packaging unit, allowing the internal chip to be electrically connected from one surface of the chip packaging unit to another surface and then electrically connected to the outside. Therefore, existing chip packaging units also have the problem of complicated processing procedures, making it difficult to reduce manufacturing costs. Furthermore, using through-silicon via technology also carries the risk of damaging the structure, which is detrimental to the product's market competitiveness. Utility Model Content

[0004] The main objective of this invention is to provide a chip packaging unit with a double-sided redistribution layer. This chip packaging unit is formed by dicing a wafer and includes a chip, a first redistribution layer, a second redistribution layer, and at least one side connection line. The chip is electrically connected to multiple external interconnects on each second conductive line in sequence via multiple die pads, each first conductive line, each side connection line, and each second conductive line. It is then electrically connected to the outside via each external interconnect. The redistribution layer technology solves the problem of relatively complex circuit layer design on existing wafers, reduces structural thickness to meet the trend of products pursuing thinness and small size, and avoids the use of through silicon via (TSV) technology in the structure, effectively solving the problem of high manufacturing costs and reducing the risk of structural damage.

[0005] To achieve the above objectives, this utility model provides a chip packaging unit with a double-sided redistribution layer. The chip packaging unit is a rectangular structure with four sides. It includes a chip, a first redistribution layer, a second redistribution layer, and at least one side connection line. The chip has a first surface and a second surface opposite to the first surface. The first surface of the chip has multiple die pads. The chip is a rectangular structure with four sides. The first redistribution layer utilizes a redistribution layer (RDL). The first redistribution layer is formed on the first surface of the chip using a redistribution layer technique. The first redistribution layer includes multiple first conductive lines, each of which is electrically connected to each die pad. Each first conductive line is made of a metal material. The second redistribution layer is formed on the second surface of the chip using a redistribution layer technique. The second redistribution layer includes multiple second conductive lines and multiple external connectors. Each second conductive line is made of a metal material, and each external connector is made of a metal material and is disposed on each second conductive line. Each side connection... The circuit is made of metal material. Each side connection line is located on each side of the chip packaging unit and is fully covered on at least one side of the chip. Each side connection line is located between the first wiring layer and the second wiring layer, and each side connection line is electrically connected to each first conductive line and each second conductive line. The chip is electrically connected to each external connector in sequence via each die pad, each first conductive line, each side connection line and each second conductive line, and then electrically connected to the outside via each external connector.The chip packaging unit is formed by dicing a wafer. The wafer has a first surface and a second surface opposite to the first surface. Multiple chip packaging units are arranged adjacently in an array on the wafer. A dicing region is located between two adjacent chip packaging units. Each dicing region has multiple vias extending axially from the first surface to the second surface. Each via is located at the outer edge of at least one side of the chip in each chip packaging unit. Each via contains an axial connection line made of metal material, and each axial connection line is located within each chip packaging unit. The first and second wiring layers are electrically connected to each of the first and second conductive lines. The dicing operation involves a dicing tool cutting the wafer along each dicing region. Each dicing region forms a dicing channel with a width smaller than that region after dicing. Simultaneously, a portion of the vias and a portion of the axial connection lines are removed during the formation of each dicing channel. The remaining portion of the axial connection lines, along with the remaining portion of the vias, is retained at the outer edge of at least one side of each chip, thus forming the side connection lines of each chip package unit.

[0006] In a preferred embodiment of the present invention, the diameter of each via on the wafer is further greater than the width of each dicing track.

[0007] In a preferred embodiment of the present invention, the first redistribution layer further includes a first dielectric layer having a plurality of first grooves, each of the first grooves being for each of the chip pads to be exposed to the outside, wherein each of the first conductive lines is formed by filling the first groove with metal paste; wherein the second redistribution layer further includes a second dielectric layer having a plurality of second grooves, wherein each of the second conductive lines is formed by filling the second groove with metal paste.

[0008] In a preferred embodiment of the present invention, the metal paste used in each of the first conductive lines comprises silver paste, nano silver paste, copper paste or nano copper paste; wherein the metal paste used in each of the second conductive lines comprises silver paste, nano silver paste, copper paste or nano copper paste.

[0009] In a preferred embodiment of the present invention, each of the external connectors is further defined as a solder ball. Attached Figure Description

[0010] Figure 1 This is a side view of a cross-sectional planar schematic diagram of an embodiment of the chip packaging unit of this utility model.

[0011] Figure 2This is a top plan view of an embodiment of the wafer of this utility model.

[0012] Figure 3 This is a side view of a wafer according to an embodiment of the present invention.

[0013] Figure 4 yes Figure 3 A magnified view of a portion of the image.

[0014] Figure 5 This is a side view of the chip of this utility model.

[0015] Figure 6 Is Figure 5 A schematic diagram showing an axial connection line set on the outer edge of the side of the chip.

[0016] Figure 7 Is Figure 6 A schematic diagram showing the first dielectric layer disposed on the chip.

[0017] Figure 8 Is Figure 7 A schematic diagram of filling the first groove with metal paste.

[0018] Figure 9 It is Figure 8 A schematic diagram of the first conductive line formed by grinding and shaping the metal paste in the process.

[0019] Figure 10 Is Figure 9 A schematic diagram showing the second dielectric layer disposed on the chip.

[0020] Figure 11 Is Figure 10 A schematic diagram of filling the second groove with metal paste.

[0021] Figure 12 It is Figure 11 A schematic diagram of the second conductive line formed by grinding the metal paste.

[0022] Figure 13 Is Figure 12 A schematic diagram showing the external connection body installed on the second conductor line.

[0023] Figure 14 This is a top view schematic diagram of another embodiment of the wafer of this utility model.

[0024] Figure 15 This is a side view of another embodiment of the chip packaging unit of this utility model.

[0025] Explanation of reference numerals in the attached figures: 1-Chip packaging unit; 1a-Side panel; 10-Chip; 11-First surface; 12-Second surface; 13-Crystal pad; 14-Side panel; 20-First redistribution layer; 21-First dielectric layer; 211-First groove; 22-First conductive line; 22a-Metal paste; 30-Second redistribution layer; 31-Second dielectric layer; 311-Second groove; 32-Second conductive line; 32a-Metal paste; 33-External interconnect; 40-Side connection line; 2-Wafer; 2a-First surface; 2b-Second surface; 2c-Cut area; 2d-Through hole; 2e-Axial connection line; 2f-Cut track. Detailed Implementation

[0026] The structure and technical features of this utility model are described in detail below with reference to the illustrations. The illustrations are only used to illustrate the structural relationships and related functions of this utility model. Therefore, the dimensions of each component in the illustrations are not drawn to actual proportions and are not intended to limit this utility model.

[0027] refer to Figure 1 The present invention provides a chip packaging unit 1 with a double-sided redistribution layer. The chip packaging unit 1 is a rectangular structure with four sides 1a. The chip packaging unit 1 includes a chip 10, a first redistribution layer 20, a second redistribution layer 30 and at least one side connection line 40.

[0028] The chip 10 has a first surface 11 and a second surface 12 opposite to the first surface 11. The first surface 11 of the chip 10 has a plurality of crystal pads 13, such as... Figure 5 As shown; the chip 10 is a rectangular structure with four sides 14, as... Figure 2 As shown; in Figure 1 In the embodiment shown, there are two of each crystal pad 13, but this is not limited.

[0029] The first redistribution layer 20 is formed on the first surface 11 of the chip 10 using redistribution layer (RDL) technology. The first redistribution layer 20 includes multiple first conductive lines 22, such as... Figure 1 As shown; each of the first conductive lines 22 is electrically connected to each crystal pad 13, such as... Figure 1 As shown; each of the first conductive lines 22 is made of metallic material.

[0030] The second redistribution layer 30 is formed on the second surface 12 of the chip 10 using redistribution layer technology. The second redistribution layer 30 includes multiple second conductive lines 32 and multiple external interconnects 33, such as... Figure 1As shown; each of the second conductive lines 32 is made of metal; each of the external connectors 33 is made of metal and is disposed on each of the second conductive lines 32, such as... Figure 1 , Figure 13 and Figure 15 As shown.

[0031] The side connection lines 40 are made of metal material. Each side connection line 40 is located on each side 1a of the chip packaging unit 1 and is fully covered on at least one side 14 of the chip 10, such as... Figure 1 As shown; wherein each side connection line 40 is located between the first rewiring layer 20 and the second rewiring layer 30, and each side connection line 40 is electrically connected to each first conductive line 22 and each second conductive line 32, as shown. Figure 1 As shown.

[0032] The chip 10 is electrically connected to each external connector 33 sequentially via each crystal pad 13, each first conductive line 22, each side connection line 40, and each second conductive line 32, and then electrically connected to the outside via each external connector 33, such as... Figure 1 and Figure 15 As shown.

[0033] The chip packaging unit 1 is further formed by dicing a wafer 2. The wafer 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a. Figure 3 As shown; wherein the wafer 2 has a plurality of chip packaging units 1 arranged adjacently in an array, and a cutting region 2c is provided between two adjacent chip packaging units 1, as shown. Figure 2 As shown, each cutting area 2c has multiple through holes 2d that extend axially from the first surface 2a to the second surface 2b, such as... Figure 3 and Figure 4 As shown, each via 2d is located at the outer edge of at least one side 14 of the chip 10 in each chip packaging unit 1, such as... Figure 2 As shown, each through-hole 2d contains an axial connection line 2e made of metallic material, such as... Figure 2 and Figure 14 As shown, each axial connection line 2e is located between the first redistribution layer 20 and the second redistribution layer 30 of each chip packaging unit 1, as... Figure 3 and Figure 4 As shown, and electrically connected to each of the first conductive lines 22 and each of the second conductive lines 32, as follows. Figure 13 As shown; the dicing operation involves a dicing tool cutting the wafer 2 along each dicing region 2c, and after dicing, a dicing path 2f with a width and diameter smaller than that of each dicing region 2c is formed on each dicing region 2c, as shown. Figures 2 to 4Furthermore, while each cutting channel 2f is formed, a portion of each through hole 2d and a portion of each axial connecting line 2e are also removed together, such as... Figure 2 As shown, the axial connection lines 2e, whose portions have not been removed, along with the vias 2d, whose portions have not been removed, remain at the outer edge of at least one side 10 of each chip 10, thereby forming the side connection lines 40 of each chip package unit 1, as shown. Figure 2 As shown.

[0034] refer to Figure 2 The aperture of each via 2d on the wafer 2 is further greater than the width of each dicing channel 2f, but is not limited thereto.

[0035] refer to Figure 7 The first redistribution layer 20 further includes a first dielectric layer 21, but is not limited thereto. The first dielectric layer 21 has multiple first grooves 211, each first groove 211 being for exposing each die pad 13 of the chip 10 to the outside. Each first conductive line 22 is formed by filling each first groove 211 with metal paste 22a. Figure 9 As shown; wherein the second redistribution layer 30 further includes a second dielectric layer 31, but is not limited thereto, the second dielectric layer 31 having multiple second grooves 311, such as Figure 10 As shown, each of the second conductive lines 32 is composed of metal paste 32a filled in each of the second grooves 311, as... Figure 12 As shown.

[0036] refer to Figure 9 The metal paste 22a used in each of the first conductive lines 22 may include silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto. The nano-silver paste material has the characteristics of low cost, high conductivity, and low-temperature sintering capability, but since nano-silver paste material is a common material, it will not be described in detail here.

[0037] refer to Figure 12 The metal paste 32a used in each of the second conductive lines 32 may include silver paste, nano silver paste, copper paste or nano copper paste, but is not limited thereto.

[0038] refer to Figure 15 Each external connector 33 is further made of solder balls, but not limited to them, which is conducive to the diversified application of the product.

[0039] The method of manufacturing the chip packaging unit 1 of this utility model may include, but is not limited to:

[0040] Step S1: Provide a wafer 2, the wafer 2 having a first surface 2a and a second surface 2b opposite to the first surface 2a, such as Figure 3 As shown, the wafer 2 has multiple chips 10 arranged adjacently in an array, such as... Figure 2As shown, each chip 10 has four sides 14, as... Figure 2 As shown; each chip 10 has a first surface 11 and a second surface 12, and the first surface 11 of each chip 10 has a plurality of crystal pads 13, such as Figure 5 As shown; there is a cutting region 2c between two adjacent chips 10, as... Figure 2 As shown, each diced region 2c has a plurality of vias 2d extending axially from the first surface 2a of the wafer 2 to the second surface 2b, such as... Figure 3 and Figure 4 As shown, each via 2d is located at at least one outer edge of the side 14 of each chip 10, such as... Figure 2 As shown, each through-hole 2d contains an axial connecting line 2e, such as... Figure 2 As shown; the axial connecting lines 2e are made of metallic material.

[0041] Step S2: Using redistribution layer (RDL) technology, a first redistribution layer 20 is laid on the first surface 11 of each chip 10, the first surface 2a of the wafer 2, and one end of each axial connection line 2e, such as... Figure 7 As shown; wherein the first redistribution layer 20 has multiple first conductive lines 22, and each first conductive line 22 is electrically connected to each axial connecting line 2e, such as Figure 9 As shown; each of the first conductive lines 22 is made of metallic material.

[0042] Step S3: Using redistribution layer technology, a second redistribution layer 30 is laid on the second surface 12 of each chip 10, the second surface 2b of the wafer 2, and one end of each axial connection line 2e, such as... Figure 10 As shown; wherein the second redistribution layer 30 has multiple second conductive lines 32, and each second conductive line 32 is electrically connected to each axial connection line 2e, such as Figure 12 As shown; each of the second conductive lines 32 is made of metal; and each of the second conductive lines 32 is provided with multiple external connectors 33, such as... Figure 13 As shown, each of the external connectors 33 is made of metallic material.

[0043] Step S4: Using a cutting tool, cut the wafer 2 along each cutting region 2c. After cutting, a cutting path 2f with a width and diameter smaller than that of each cutting region 2c is formed on each cutting region 2c, such as... Figure 2As shown, while each cutting channel 2f is formed, a portion of each via 2d and a portion of each axial connection line 2e are cut off together. The portion of each axial connection line 2e that is not cut off, together with the portion of each via 2d that is not cut off, is retained at the outer edge of at least one side surface 14 of each chip 10, thereby forming at least one side connection line 40. Figure 2 As shown; wherein each side connection line 40 is located between the first rewiring layer 20 and the second rewiring layer 30, and each side connection line 40 is electrically connected to each first conductive line 22 and each second conductive line 32, as shown. Figure 1 As shown.

[0044] Step S5: After the wafer 2 is cut, multiple chip packaging units 1 are formed, such as... Figure 3 As shown; in each chip packaging unit 1, the chip 10 is electrically connected to each external connector 33 sequentially via each die pad 13, each first conductive line 22, each side connection line 40, and each second conductive line 32, and then electrically connected to the external connector 33, as shown. Figure 1 , Figure 13 and Figure 15 As shown.

[0045] refer to Figure 9 In step S2, the first redistribution layer 20 further utilizes a technique of first filling the grooves with metal paste and then grinding to form conductive lines to form multiple first conductive lines 22 on each chip 10: firstly, a first dielectric layer 21 is laid on the first surface 11 of each chip 10, the first surface 2a of the wafer 2, and one end of each axial connection line 2e, such as... Figure 7 As shown, multiple first grooves 211 are then formed horizontally on the first dielectric layer 21, and each first groove 211 exposes one end of each axial connection line 2e to the outside, as shown. Figure 7 As shown, metal paste 22a is then filled into each of the first grooves 211, and the thickness of the metal paste 22a is higher than the surface of the first dielectric layer 21, as shown. Figure 8 As shown, the metal paste 22a, which is higher than the surface of the first dielectric layer 21, is finally polished so that the surface of the metal paste 22a is flush with the surface of the first dielectric layer 21 to form the first conductive lines 22, as shown. Figure 9As shown. The process of fabricating the first conductive line 22 can be considered a key step in fabricating the redistribution layer (RDL) of the chip packaging unit 1. It can utilize a technique of first filling the grooves with metal paste and then grinding to form the conductive lines to create multiple conductive lines on the dielectric layer. Since this is a process that is easy to implement precisely, the process is relatively simple, allowing the conductive lines in the redistribution layer (RDL) to achieve XY plane electrical extension and interconnection while maintaining or achieving a certain degree of thinness and compactness in the finished chip packaging unit 1. The above is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

[0046] refer to Figure 12 In step S3, the second redistribution layer 30 further utilizes a technique of first filling the grooves with metal paste and then grinding to form conductive lines to form multiple second conductive lines 32 on each chip 10: first, a second dielectric layer 31 is deposited on the second surface 12 of each chip 10, the second surface 2b of the wafer 2, and one end of each axial connection line 2e, such as... Figure 10 As shown, multiple second grooves 311 are then formed horizontally on the second dielectric layer 31, and each second groove 311 exposes one end of each axial connection line 2e to the outside, as shown. Figure 10 As shown, metal paste 32a is then filled into each of the second grooves 311, and the thickness of the metal paste 32a is higher than the surface of the second dielectric layer 31, as shown. Figure 11 As shown, the metal paste 32a, which is higher than the surface of the second dielectric layer 31, is finally polished so that the surface of the metal paste 32a is flush with the surface of the second dielectric layer 31 to form each second conductive line 32, as shown. Figure 12 As shown. The fabrication process of each of the second conductive lines 32 can be considered a key step in fabricating the redistribution layer (RDL) of the chip packaging unit 1. It utilizes a technique of first filling the grooves with metal paste and then grinding to form the conductive lines to create multiple conductive lines on the dielectric layer. Because this is a process that is easy to implement with precision, the process is relatively simplified. This allows the conductive lines in the redistribution layer (RDL) to achieve XY plane electrical extension and interconnection while simultaneously ensuring that the finished chip packaging unit 1 maintains or achieves a certain degree of thinness and compactness. The above is merely a technique used in a preferred embodiment of this utility model and is not intended to limit the scope of this utility model.

[0047] Compared with existing chip packaging unit technologies, the chip packaging unit 1 of this invention has the following advantages:

[0048] (1) The first redistribution layer 20 and the second redistribution layer 30 of this utility model are formed on the chip 10 using redistribution layer technology, rather than being stacked on the chip in layers. This effectively solves the problem of relatively complex circuit layer design of existing chip packaging units, meets the current trend of pursuing thin and light chip packaging products, and helps to reduce manufacturing costs.

[0049] (2) The chip 10 of this utility model is electrically connected to each external connector 33 sequentially via each crystal pad 13, each first conductive line 22, each side connecting line 40, and each second conductive line 32, and then electrically connected to the outside via each external connector 33, such as... Figure 1 and Figure 15 As shown, this allows for more diverse electrical connection designs for each chip 20, enabling further electrical connections between the chips on their respective surfaces via side-connecting lines 40. This eliminates the need for through-silicon vias (TSVs), simplifying the manufacturing process and reducing costs. Furthermore, besides simplifying the process and reducing the complexity of circuit design, it also avoids structural damage, thus enhancing the product's market competitiveness.

[0050] (3) In the manufacturing process of the chip packaging unit 1 of this utility model, step S4 reveals that the wafer 2 can be cut along each cutting region 2c of the wafer 2 using a cutting tool, and a cutting path 2f with a width diameter smaller than that of each cutting region 2c is formed on each cutting region 2c after cutting, such as Figure 2 As shown, while each cutting channel 2f is formed, a portion of each via 2d and a portion of each axial connection line 2e are cut off together. The portion of each axial connection line 2e that is not cut off, together with the portion of each via 2d that is not cut off, is retained at at least one outer edge of each side 14 of each chip 10 and can thus form at least one side connection line 40, as shown. Figure 2 As shown, when the cutting is completed, the connecting lines 40 on each side are formed at each side 1a of the chip packaging unit 1, without having to wait until the chip packaging unit is formed before processing the side line layer on the side of the chip packaging unit, which simplifies the process and helps reduce manufacturing costs.

[0051] The above are merely preferred embodiments of the present utility model and are illustrative rather than restrictive. Those skilled in the art will understand that many changes, modifications, and even equivalent alterations can be made to the present utility model within the spirit and scope defined by the claims, but all such changes will fall within the protection scope of the present utility model.

Claims

1. A chip packaging unit with a double-sided redistribution layer, the chip packaging unit being a rectangular structure with four sides, characterized in that, The chip packaging unit includes: A chip having a first surface and a second surface opposite the first surface, the first surface of the chip having a plurality of crystal pads; wherein the chip is a rectangular structure and has four sides; A first redistribution layer is formed on the first surface of the chip using redistribution layer technology. The first redistribution layer includes a plurality of first conductive lines; wherein each of the first conductive lines is electrically connected to each of the die pads; wherein each of the first conductive lines is made of a metallic material. A second redistribution layer, formed on the second surface of the chip using redistribution layer technology, includes multiple second conductive lines and multiple external connectors; wherein each second conductive line is made of a metal material; wherein each external connector is made of a metal material and is disposed on each second conductive line; and At least one side connection line, each side connection line is made of metal material, each side connection line is located on each side of the chip packaging unit and is fully covered on the at least one side of the chip; wherein each side connection line is located between the first wiring layer and the second wiring layer, and each side connection line is electrically connected to each first conductive line and each second conductive line. The chip is electrically connected to each external connector in sequence via each of the crystal pads, each of the first conductive lines, each of the side connection lines and each of the second conductive lines, and then electrically connected to the outside via each of the external connectors. The chip packaging unit is formed by dicing a wafer. The wafer has a first surface and a second surface opposite to the first surface. Multiple chip packaging units are arranged adjacently in an array on the wafer. A dicing region is provided between two adjacent chip packaging units. Each dicing region has multiple vias extending axially from the first surface to the second surface. Each via is located at the outer edge of at least one side of the chip in each chip packaging unit. Each via contains an axial connection line made of metal material, and each axial connection line is located within each chip packaging unit. The first and second wiring layers are electrically connected to each of the first and second conductive lines; wherein the dicing operation is performed by a dicing tool cutting the wafer along each of the dicing regions of the wafer, and a dicing channel with a width diameter smaller than each dicing region is formed on each dicing region after dicing, and a portion of the via and a portion of the axial connection lines are removed together when each dicing channel is formed, and the portion of the axial connection lines that are not removed, together with the portion of the vias that are not removed, are retained at the outer edge of at least one side of each chip and thereby constitute the side connection lines of each chip packaging unit.

2. The chip packaging unit as described in claim 1, characterized in that, The diameter of each via on the wafer is greater than the width of each dicing pass.

3. The chip packaging unit as described in claim 1, characterized in that, The first wiring layer further includes a first dielectric layer having multiple first grooves, each first groove being for exposing each of the chip's die pads to the outside, wherein each first conductive line is formed by filling each first groove with metal paste; wherein the second wiring layer further includes a second dielectric layer having multiple second grooves, wherein each second conductive line is formed by filling each second groove with metal paste.

4. The chip packaging unit as described in claim 3, characterized in that, The metal paste used in each of the first conductive lines is silver paste, nano silver paste, copper paste or nano copper paste; and the metal paste used in each of the second conductive lines is silver paste, nano silver paste, copper paste or nano copper paste.

5. The chip packaging unit as described in claim 1, characterized in that, Each of these external connectors is a solder ball.

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