Server power-on detection device

Abstract

The utility model discloses a server power-on detection device, and relates to the technical field of servers, the server power-on detection device comprises a clock detection circuit, a power-on control circuit and a state indication circuit, the clock detection circuit and the power-on control circuit reuse a complex programmable logic device; the clock detection circuit is used for detecting an internal clock signal of the complex programmable logic device; the power-on control circuit is used for sending a power-on control signal to the at least one step-down power supply module through the complex editable logic device, the power-on control signal is used for indicating to execute power-on operation on the server, and the at least one step-down power supply module is used for executing power-on operation on at least one server component in the server; the state indicating circuit comprises a display unit, and the display unit is used for displaying the power-on sequence of the at least one step-down power supply module, so that the power-on detection efficiency of the server is improved, and the problem that the power-on detection efficiency of the server is low in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and particularly relates to a server power-on detection device. BACKGROUND

[0002] In the related art server power-on detection scene, engineers usually need to rely on expensive and precise instruments such as oscilloscopes to measure the voltage changes of each power rail and the clock signal output situation one by one, so as to determine whether the power-on timing is correct and locate the fault link. In this process, multiple test points need to be repeatedly operated, which is not only tedious and time-consuming, but also limited by the use scene of the oscilloscope, resulting in low efficiency of server power-on detection. CONTENT OF THE UTILITY MODEL

[0003] The present application provides a server power-on detection device to at least solve the problem of low accuracy of log analysis in the related art.

[0004] The present application provides a server power-on detection device, which comprises a clock detection circuit, a power-on control circuit and a state indication circuit, the clock detection circuit and the power-on control circuit are multiplexed with a complex programmable logic device;

[0005] The clock detection circuit is used to detect the internal clock signal of the complex programmable logic device.

[0006] The power-on control circuit is used to send a power-on control signal to at least one step-down power supply module through the complex programmable logic device, the power-on control signal is used to instruct to perform a power-on operation on the server, and the at least one step-down power supply module is used to perform a power-on operation on at least one server component in the server.

[0007] The state indication circuit comprises a display unit, and the display unit is used to display the power-on sequence of the at least one step-down power supply module.

[0008] The present application further provides a server, which comprises a case and the above-mentioned server power-on detection device, and the server power-on detection device is arranged in the case.

[0009] Through the clock detection circuit, the internal clock signal of the complex programmable logic device is detected, so that the complex programmable logic device has an accurate time reference, and power-on control timing confusion caused by an abnormal internal clock signal is avoided; the power-on control circuit sends a power-on control signal to at least one voltage reduction power supply module by means of the multiplexed complex programmable logic device, so as to accurately control the power-on operation of the server component; the state indication circuit displays the power-on sequence of the at least one voltage reduction power supply module through the display unit, so that an engineer can intuitively obtain power-on sequence information without relying on an oscilloscope and the like, and quickly judge whether the power-on timing meets the requirements, and when power-on abnormality occurs, the fault link can be quickly located through the displayed power-on sequence, thereby solving the problem of low efficiency of server power-on detection caused by the dependence on the oscilloscope measurement, the complicated debugging operation, and the time-consuming fault location, so as to achieve the technical effects of simplifying the debugging process and improving the efficiency of server power-on detection. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the drawings required in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0011] Figure 1 A hardware structure block diagram of a server device of a server power-on detection device provided by the embodiments of the present application;

[0012] Figure 2 A schematic diagram of an optional server power-on detection device according to the embodiments of the present application;

[0013] Figure 3 A schematic diagram of an optional clock detection circuit according to the embodiments of the present application;

[0014] Figure 4 A schematic diagram of an optional power-on control circuit according to the embodiments of the present application;

[0015] Figure 5 A schematic diagram of an optional state display sub-circuit according to the embodiments of the present application;

[0016] Figure 6 A schematic diagram of an optional timing display sub-circuit according to the embodiments of the present application;

[0017] Figure 7 A schematic diagram of an optional complex programmable logic device according to the embodiments of the present application;

[0018] Figure 8FIG. 2 shows a schematic diagram of another optional server power-on detection device according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, but not all embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0020] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0021] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0022] According to an aspect of an embodiment of the present application, a server power-on detection device is provided. As an optional embodiment, the server power-on detection device can be applied in, but is not limited to, a hardware environment as shown in FIG. 1. The server can include, but is not limited to, one or more (only one is shown in FIG. 1) central processing units (CPUs) 11, a root complex 12, a memory 13 for storing data, and a switch 14. Those skilled in the art can understand that the structure shown in FIG. 1 is only schematic, and does not limit the structure of the server. For example, the server can include more or fewer components than those shown in FIG. 1, or have a different configuration from that shown in FIG. 1. The host can be connected to one or more peripheral component interconnect express (PCIe) devices 21 through a PCIe interface, or connected to a PCIe-PCI bridge 22. Those skilled in the art can understand that the PCIe interface can be replaced by another interface, and the PCIe device can be replaced by another device. Figure 1 Figure 1 The server can include, but is not limited to, one or more (only one is shown in FIG. 1) central processing units (CPUs) 11, a root complex 12, a memory 13 for storing data, and a switch 14. Those skilled in the art can understand that the structure shown in FIG. 1 is only schematic, and does not limit the structure of the server. For example, the server can include more or fewer components than those shown in FIG. 1, or have a different configuration from that shown in FIG. 1. The host can be connected to one or more peripheral component interconnect express (PCIe) devices 21 through a PCIe interface, or connected to a PCIe-PCI bridge 22. Those skilled in the art can understand that the PCIe interface can be replaced by another interface, and the PCIe device can be replaced by another device. Figure 1 The structure shown in FIG. 1 is only schematic, and does not limit the structure of the server. For example, the server can include more or fewer components than those shown in FIG. 1, or have a different configuration from that shown in FIG. 1. The host can be connected to one or more peripheral component interconnect express (PCIe) devices 21 through a PCIe interface, or connected to a PCIe-PCI bridge 22. Those skilled in the art can understand that the PCIe interface can be replaced by another interface, and the PCIe device can be replaced by another device. Figure 1 The structure shown in FIG. 1 is only schematic, and does not limit the structure of the server. For example, the server can include more or fewer components than those shown in FIG. 1, or have a different configuration from that shown in FIG. 1. The host can be connected to one or more peripheral component interconnect express (PCIe) devices 21 through a PCIe interface, or connected to a PCIe-PCI bridge 22. Those skilled in the art can understand that the PCIe interface can be replaced by another interface, and the PCIe device can be replaced by another device. Figure 1 The structure shown in FIG. 1 is only schematic, and does not limit the structure of the server. For example, the server can include more or fewer components than those shown in FIG. 1, or have a different configuration from that shown in FIG. 1. The host can be connected to one or more peripheral component interconnect express (PCIe) devices 21 through a PCIe interface, or connected to a PCIe-PCI bridge 22. Those skilled in the art can understand that the PCIe interface can be replaced by another interface, and the PCIe device can be replaced by another device.​Figure 1 The structures and connection manners shown are only schematic and do not limit the structures between the host and the PCIe device.

[0023] The central processing unit (CPU) 11 can be responsible for executing program instructions and processing data. In the PCIe architecture, the CPU is usually connected to a root complex. The CPU is connected to the root complex through a high-speed interconnect, such as a cache coherent interconnect or a dedicated PCIe channel, to achieve fast transmission of data and instructions.

[0024] The root complex (ROOT Complex) 12 is the top layer of the PCIe bus hierarchy, which serves as an interface between the CPU and the PCIe bus. The root complex may include multiple components, such as a processor interface, a DRAM interface, an input / output (I / O) controller, etc. In some systems, the root complex may be integrated within the CPU chip or placed adjacent to the CPU chip as a separate chip. The root complex is responsible for managing PCIe bus transactions initiated from the CPU, including memory access, device communication, etc. In the PCIe system, data flows through the root complex, through a PCIe switch or other bridge device, to the target PCIe device.

[0025] The memory (Memory) 13 is a hardware component for storing data and programs, which can be a random access memory (RAM), a read-only memory (ROM), a static random access memory (SRAM), etc.

[0026] The switch (Switch) 14 can be used to connect multiple devices and forward data packets. In the PCIe architecture, the switch is a PCIe switch, which allows multiple PCIe devices to be connected to a PCIe port, expanding the connection capabilities of the system. The PCIe switch can connect multiple PCIe terminal devices or root complexes, supporting more complex system topologies, while managing the routing and forwarding of data packets between devices.

[0027] PCIe device (PCI Express Endpoint) 21 refers to a device connected to a PCIe bus. PCIe Endpoint often exists in the form of a board card, such as a graphics card, a solid state disk (SSD), a network card, etc., which communicates with other parts of the system through a PCIe interface. The PCIe device can receive and send data, and it can be an initiator or a terminator of bus operation.

[0028] PCIe bridge (PCI Express-PCI Bridge) 22 can allow communication between a PCIe interface and an old PCI (Peripheral Component Interconnect) or PCI-X (PCI eXtended) interface. It can make it possible to use old PCIe devices in a new PCIe system, while also allowing old PCI systems to be connected to PCIe devices. Supporting compatibility between PCI Express and PCI / PCI-X allows the use of PCI devices in a PCIe system.

[0029] Embodiments of the present application provide a server power-on detection device, Figure 2 is a schematic diagram of an optional server power-on detection device according to an embodiment of the present application; as Figure 2 shown, the server power-on detection device comprises:

[0030] a clock detection circuit 202, a power-on control circuit 204 and a state indication circuit 206, the clock detection circuit 202 and the power-on control circuit 204 being multiplexed with a complex programmable logic device 208;

[0031] The clock detection circuit 202 is configured to detect an internal clock signal of the complex programmable logic device 208.

[0032] The power-on control circuit 204 is configured to send a power-on control signal to at least one step-down power supply module 210 through the complex programmable logic device 208, the power-on control signal being configured to instruct to perform a power-on operation on the server, and the at least one step-down power supply module 210 being configured to perform a power-on operation on at least one server component 212 in the server.

[0033] The state indication circuit 206 comprises a display unit 214, which is configured to display the power-on sequence of the at least one step-down power supply module.

[0034] It should be noted that the clock detection circuit 202 is a circuit for detecting whether the internal clock signal of the complex programmable logic device 208 is working normally and ensuring the accuracy of its counting time, which can provide a standard time reference for subsequent calculation of the server power-on timing. If the clock signal is abnormal, it will be fed back in time to avoid the confusion of the power-on timing caused by the error of the time reference.

[0035] Optionally, in the embodiment, the power-on control circuit 204 is a circuit for realizing accurate control of the server power-on process by relying on the complex programmable logic device 208, for sending a power-on control signal to the step-down power supply module 210, to ensure that the required power supply of each component of the server can be normally powered on.

[0036] Optionally, in the embodiment, the state indication circuit 206 is a circuit for intuitively displaying the power-on state of the server, which can enable engineers to quickly determine whether the power-on is normal and locate the fault link without the aid of professional instruments such as oscilloscopes, thereby improving the debugging efficiency.

[0037] Optionally, in the embodiment, the complex programmable logic device 208 (CPLD) is a logic device with high integration and flexible programming, which is multiplexed by the clock detection circuit 202 and the power-on control circuit 204 in the embodiment, and undertakes tasks such as logic control, time calculation, and signal processing, and is the control center for realizing server power-on detection and fault positioning.

[0038] Optionally, in the embodiment, the step-down power supply module 210 is a power supply module that can convert the input high voltage into a lower stable voltage required by each component of the server, and its main function is to provide power supply meeting the voltage requirements for different components such as CPU, memory, and chipset in the server, and is the energy source for ensuring the normal work of each component of the server. In the server, different components have different voltage requirements, while the external input voltage of the server is usually higher than the voltage requirement of each component, and at this time, different specifications of the step-down power supply module 210 are needed for voltage conversion.

[0039] Optionally, in the embodiment, the server component 212 is the core hardware unit for realizing various functions in the server, including but not limited to central processing unit (CPU), memory (RAM), chipset, hard disk, network card, etc., and these components need to rely on the stable power provided by the step-down power supply module 210 to work normally.

[0040] Optionally, in the embodiment, after the internal clock signal of the complex programmable logic device 208 is acquired by the clock detection circuit 202, it is determined whether the internal clock signal is normal; if the internal clock signal is normal, the complex programmable logic device 208 is further caused to send a power-on control signal to at least one step-down power supply module 210 by the power-on control circuit, and the step-down power supply module 210 receives the power-on control signal and then supplies power to at least one server component 212.

[0041] Through the embodiment provided in the application, the internal clock signal of the complex programmable logic device is detected by the clock detection circuit, so that the complex programmable logic device can have an accurate time reference, and power-on control timing disorder caused by an abnormal internal clock signal can be avoided; the power-on control circuit sends a power-on control signal to at least one voltage reduction power supply module by means of the multiplexed complex programmable logic device, so as to realize accurate control of the power-on operation of the server assembly; the state indication circuit displays the power-on sequence of the at least one voltage reduction power supply module through the display unit, so that engineers can intuitively obtain power-on sequence information without relying on an oscilloscope and the like, and can quickly judge whether the power-on timing meets the requirements, and at the same time, when power-on abnormality occurs, the displayed power-on sequence can be used to quickly locate the fault link, thereby solving the problem of low efficiency of server power-on detection caused by the dependence on an oscilloscope for measurement, complicated debugging operation and time-consuming fault location in the prior art, so as to achieve the technical effects of simplifying the debugging process and improving the efficiency of server power-on detection.

[0042] As an optional solution, Figure 3 A schematic diagram of a clock detection circuit of the embodiment is shown in Figure 3 As shown in the figure, the clock detection circuit 202 comprises a complex programmable logic device 208, an external crystal oscillator 302, a digital-to-analog converter 304 and a comparator 306.

[0043] The external crystal oscillator 302 is connected to the complex programmable logic device 208, and the external crystal oscillator 302 is used to obtain a clock count value, and the clock count value is used to indicate the internal clock signal of the complex programmable logic device 208.

[0044] The digital-to-analog converter 304 is connected to the complex programmable logic device 208, and the digital-to-analog converter 304 is used to convert the clock count value into an analog voltage.

[0045] The comparator 306 is connected to the complex programmable logic device 208, and the comparator 306 is used to compare the analog voltage with a voltage standard value.

[0046] Optionally, in the embodiment, the external crystal oscillator 302 is an electronic element capable of generating a stable pulse signal, which is directly connected to the complex programmable logic device 208, and its main function is to provide a stable clock count source for the complex programmable logic device 208, so that the complex programmable logic device 208 can generate a clock count value for indicating the internal clock signal based on the pulse signal. In actual application, the frequency of the external crystal oscillator 302 determines the period of the output pulse signal, and thus affects the accuracy of the clock count value generated by the complex programmable logic device 208.

[0047] Optionally, in the embodiment, the digital-to-analog converter 304 is a signal conversion component connected to the complex programmable logic device 208, and has the function of converting a digital signal into an analog signal. The main function of the digital-to-analog converter 304 is to convert the digital form clock count value generated by the complex programmable logic device 208 for indicating the internal clock signal into an analog voltage. For example, if the clock count value generated by the complex programmable logic device 208 based on the external crystal oscillator 302 is 1000, which corresponds to 1 ms of standard time, the digital-to-analog converter 304 will convert the digital 1000 into a corresponding analog voltage according to the preset conversion rule.

[0048] Optionally, in the embodiment, the comparator 306 is a signal comparison component connected to the complex programmable logic device 208, and has the function of comparing the sizes of two analog voltage signals. The main function of the comparator 306 is to compare the analog voltage converted by the digital-to-analog converter 304 with the preset voltage standard value, and feed back the comparison result to the complex programmable logic device 208. In the actual detection process, the voltage standard value is preset based on the standard time required by the server power-on timing.

[0049] Through the embodiment provided in the application, the clock detection circuit 202 is formed by the complex programmable logic device 208, the external crystal oscillator 302, the digital-to-analog converter 304 and the comparator 306, and the detection of the internal clock signal is completed, so that the reliable standard time reference for the server power-on timing calculation is provided, the confusion of the power-on timing caused by the abnormal clock is avoided, and the stability of the server power-on is ensured.

[0050] As an optional solution, the clock detection circuit 202 further comprises a first buzzer.

[0051] The first buzzer is connected to the comparator 306, and the first buzzer is used to send the first warning information. The first warning information is used to indicate that the internal clock signal of the complex programmable logic device 208 is abnormal.

[0052] Optionally, in the embodiment, the first buzzer is a sound emitting component for abnormal alarm in the clock detection circuit 202, and is directly connected to the comparator 306. The main function of the first buzzer is to intuitively remind the engineer that there is a problem in the clock system by sending the first warning information when the comparator 306 detects that the internal clock signal of the complex programmable logic device 208 is abnormal, so as to quickly intervene in the troubleshooting, and avoid the influence of the abnormal clock signal on the server power-on timing control.

[0053] For example, assuming that the server power-on timing calculation needs to take 1 ms as the standard time unit, and the preset standard value of the analog voltage corresponding to the standard time is 2 V. When the comparator 306 compares the analog voltage output by the digital-to-analog converter 304, such as 1.8 V, with the standard value 2 V, and finds that the two are not equal, the comparator 306 sends a trigger signal to the first buzzer, and the first buzzer immediately issues the first warning information.

[0054] Through the embodiments provided in the present application, the first buzzer is connected with the comparator 306, and the first warning information is immediately issued when the clock is abnormal, so that the technical effect of intuitively reminding the engineer of the fault and avoiding the power-on timing confusion and device damage caused by the failure to find the clock abnormality in time is achieved.

[0055] As an optional solution, Figure 4 FIG. 1 shows a schematic diagram of an embodiment of a power-on control circuit of the present application. As shown in the figure, the power-on control circuit 204 includes a complex programmable logic device 208, at least one step-down power supply module 210, and at least one server component 212. Figure 4

[0056] The complex programmable logic device 208 is connected with the at least one step-down power supply module 210 through a first signal line 402, and the first signal line 402 is used to transmit a power-on control signal.

[0057] Each step-down power supply module 210 is connected with at least one server component 212, and the step-down power supply module 210 supplies power to the at least one server component 212.

[0058] Optionally, in the embodiment, the first signal line 402 is a physical signal transmission link connecting the complex programmable logic device 208 and the at least one step-down power supply module 210, and is used to transmit the power-on control signal to the at least one step-down power supply module 210 in the case where the comparison result indicates that the internal clock signal of the complex programmable logic device 208 is normal.

[0059] Optionally, in the embodiment, the step-down power supply module is used to perform a power-on operation on the connected at least one server component 212 in the case where the power-on control signal transmitted by the complex programmable logic device 208 is received through the first signal line 402.

[0060] Through the embodiments provided in the present application, the step-down power supply module 210 is driven by the power-on control circuit 204 to supply power to the at least one server component 212, so that the technical effect of guaranteeing the reliable start of the server and improving the stability of the server is achieved.

[0061] As an optional solution, the power-on control circuit 204 further includes an initial power supply module.

[0062] ​The initial power module is connected with the at least one step-down power module 210, and the initial power module is used to provide an initial voltage for the at least one step-down power module 210, and the step-down power module 210 is used to convert the initial voltage into a voltage matched with the server.

[0063] Optionally, in the embodiment, the initial power module is a basic power supply component in the power-on control circuit 204 for providing the initial voltage for the step-down power module 210, and is directly connected with the at least one step-down power module 210, and the main function of the initial power module is to output a stable initial voltage, and to provide a prerequisite for the voltage conversion function of the step-down power module 210. Only after the initial voltage is obtained, the step-down power module 210 can convert the initial voltage into a voltage matched with the server component 212 according to the power-on control information of the complex programmable logic device 208.

[0064] Through the embodiment provided in the application, the initial voltage is provided for the at least one step-down power module 210 through the initial power module, and the problem that the step-down power module 210 cannot realize voltage conversion without the initial voltage is solved, so that the stable energy source for the power-on process is provided, and the technical effect of guaranteeing the normal start of the step-down power module 210 is realized.

[0065] As an optional solution, the state indication circuit 206 includes a state display sub-circuit and a time sequence display sub-circuit, and the state display sub-circuit and the time sequence display sub-circuit multiplex the complex programmable logic device 208.

[0066] The state display sub-circuit is used to display the power-on result of the at least one step-down power module 210 through the complex programmable logic device 208.

[0067] The time sequence display sub-circuit includes a display unit 214, and the time sequence display sub-circuit is used to display the power-on sequence of the at least one step-down power module 210 through the display unit 214.

[0068] Optionally, in the embodiment, the state display sub-circuit is a functional sub-module focusing on the feedback of the power-on result in the state indication circuit 206, and multiplexes the complex programmable logic device 208, and the main function of the state display sub-circuit is to rely on the complex programmable logic device 208 to collect the power-on state signal of the at least one step-down power module 210 in real time, such as a PG signal, and to display the power-on result.

[0069] Optionally, in the embodiment, the timing display sub-circuit is a functional sub-module of the state indication circuit 206 for presenting the power-on sequence, and includes a display unit 214 and a complex programmable logic device 208. The main function of the timing display sub-circuit is to record the power-on sequence and timing interval of the at least one step-down power supply module 210 through the complex programmable logic device 208, and then display the sequence in a visual or readable form through the display unit 214, so that the engineers can intuitively confirm whether the power-on timing meets the preset requirements, and solve the cumbersome problem of measuring the timing with a traditional oscilloscope.

[0070] According to the embodiment provided in the present application, the state display sub-circuit relies on the complex programmable logic device 208 to feed back the power-on result of the at least one step-down power supply module 210, so that the engineers can quickly determine whether the power-on is normal without using an oscilloscope to measure the voltage one by one, thereby achieving the technical effects of reducing the debugging steps and lowering the difficulty of power-on result determination. The timing display sub-circuit relies on the complex programmable logic device 208 and the display unit 214 to display the power-on sequence, so that the engineers can intuitively obtain the timing information without building an oscilloscope test environment, thereby achieving the technical effects of simplifying the timing verification process and improving the timing determination efficiency.

[0071] As an optional solution, Figure 5 FIG. 1 shows a schematic diagram of a state display sub-circuit according to an embodiment of the present application. As shown in FIG. 1, the state display sub-circuit includes a complex programmable logic device 208, at least one step-down power supply module 210, and at least one LED lamp 502. Figure 5

[0072] The complex programmable logic device 208 is connected with the at least one step-down power supply module 210 through a second signal line 504. The second signal line is used for transmitting state information. The state information is used for indicating the health state of the step-down power supply module 210. The power-on result includes the state information.

[0073] The first output port 506 of the complex programmable logic device 208 is connected with the at least one LED lamp. The at least one LED lamp 502 is used for indicating the position of the abnormal step-down power supply module 210.

[0074] Optionally, in the embodiment, the at least one LED lamp 502 is an intuitive indication component in the state display sub-circuit, which is connected with the first output port 506 of the complex programmable logic device 208. The main function of the at least one LED lamp 502 is to intuitively display the health state of the at least one step-down power supply module 210 in the state of lighting or extinguishing according to the control signal sent by the complex programmable logic device 208, so as to help the engineers quickly locate the abnormal step-down power supply module without measuring the module voltage one by one, thereby reducing the difficulty of troubleshooting.

[0075] ​For example, if the complex programmable logic device 208 detects that the PG normal output, that is, the corresponding power supply module is powered on normally, at this time, the complex programmable logic device 208 defines the counter to accumulate the number of PGs. In this example, if 9 power supplies output normal PG, the counter is finally 9, which is displayed in binary as 1001, and the corresponding LED is on-off-off-on. If the LED state is off-on-off-on, it can be calculated that 0101=5, which indicates that the 6th power supply module outputs abnormally, and the fault point can be directly located.

[0076] Optionally, in this embodiment, the second signal line 504 is a state information transmission link in the state display sub-circuit, connecting the complex programmable logic device 208 and the at least one power supply module 210, and mainly serving to transmit the state information generated by the power supply module 210 to the complex programmable logic device 208, so as to ensure that the complex programmable logic device 208 can receive the real module health state data.

[0077] Optionally, in this embodiment, the first output port 506 is a physical interface of the complex programmable logic device 208 for outputting the LED control signal, and mainly serves to output the control signal generated by the complex programmable logic device 208 after analyzing the state information to the at least one LED lamp 502, so as to be a control signal channel between the complex programmable logic device 208 and the LED lamp, and ensure that the control instruction can be accurately conveyed to the LED lamp.

[0078] Optionally, in this embodiment, the state information is an electrical signal generated by the at least one power supply module 210 and used for reflecting the health state of the power supply module, such as a PG signal, and mainly serves as a basis for the complex programmable logic device 208 to judge the power-on result, and is core data for transmitting the module health state in the state display sub-circuit. Generally, a high level indicates normal power-on, and a low level indicates abnormal power-on.

[0079] Optionally, in this embodiment, the power-on result is a judgment result of the complex programmable logic device 208 on the module power-on state based on the state information transmitted by the power supply module 210, and mainly serves to provide a direct basis for the state control of the LED lamp 502.

[0080] Through the embodiments provided in the present application, the state information of the power supply module 210 is transmitted through the second signal line 504, so that the complex programmable logic device 208 can obtain the health state without directly measuring the module voltage, thereby avoiding the cumbersome operation of the traditional measurement relying on an oscilloscope, and thus achieving the technical effects of simplifying the power-on state acquisition process and reducing the dependence on hardware measurement.

[0081] As an optional solution, the state display sub-circuit further comprises a binary converter and a second buzzer.

[0082] The binary converter is connected with the complex programmable logic device 208, and the binary converter is used for converting state information into binary information used for indicating a display state of the at least one LED lamp.

[0083] The second output port of the complex programmable logic device 208 is connected with the second buzzer, and the second buzzer is used for sending second warning information used for indicating that there is an abnormal voltage reduction power module 210.

[0084] Optionally, in the embodiment, the binary converter is a key component for signal format conversion in the state display sub-circuit, and is connected with the complex programmable logic device 208. The main function of the binary converter is to receive state information transmitted by the complex programmable logic device 208, and convert the state information into binary information.

[0085] Optionally, in the embodiment, the second buzzer is a sound component for abnormal alarm in the state display sub-circuit, and is connected with the second output port of the complex programmable logic device 208. The main function of the second buzzer is to receive a trigger signal sent by the complex programmable logic device 208 when the complex programmable logic device 208 detects that the state information of the at least one voltage reduction power module 210 is abnormal, and send second warning information. The warning information can quickly remind an engineer of the existence of power-on abnormality in the form of sound, so as to avoid missing faults of the engineer due to not observing the LED lamp in time, and realize double abnormality prompt of vision and hearing.

[0086] Optionally, in the embodiment, the second output port is a physical interface of the complex programmable logic device 208 used for connecting the second buzzer and outputting an alarm trigger signal. The main function of the second output port is to output a high-level trigger signal to the second buzzer to drive the second buzzer to send second warning information when the complex programmable logic device 208 determines that there is an abnormal voltage reduction power module 210. The second output port is a control signal channel between the complex programmable logic device 208 and the second buzzer, and ensures that the abnormal alarm instruction can be timely and accurately conveyed.

[0087] Through the embodiment provided in the application, the state information is converted into binary information by the binary converter, the state of the plurality of voltage reduction power modules is displayed by using a small amount of LED lamps, the circuit complexity problem caused by a large amount of LED lamps in the traditional one-to-one indication is avoided, and therefore the technical effects of simplifying circuit layout and reducing hardware cost are achieved. The second warning information is sent by the second buzzer, and the visual indication is supplemented in the form of hearing, so as to avoid missing faults of the engineer due to not observing the LED lamp in time, and therefore the technical effects of improving fault response speed and adapting to multi-task debugging scenes are achieved.

[0088] As an optional solution, Figure 6 A timing display sub-circuit of the embodiment is shown in FIG. 4.Figure 6 The timing display sub-circuit is shown to include: a complex programmable logic device 208, a central processing unit 602 of the server, and a display unit 214.

[0089] The complex programmable logic device 208 is connected with the central processing unit through a serial peripheral interface bus 604, and the central processing unit 602 is configured to acquire power-on sequence information from the complex programmable logic device 208, the power-on sequence information being used to indicate a power-on sequence of the at least one step-down power supply module 210.

[0090] The central processing unit is connected with the display unit 214.

[0091] Optionally, in the embodiment, the central processing unit 602 of the server is a core component for receiving, analyzing and displaying driving of the power-on sequence information in the timing display sub-circuit, and is connected with the complex programmable logic device 208 through the serial peripheral interface bus 604 and is connected with the display unit 214. The main function of the central processing unit 602 is to acquire the power-on sequence information from the complex programmable logic device 208, analyze the information, and then generate a driving signal to control the display unit 214 to present the power-on sequence. In addition, the central processing unit 602 also belongs to the server component 212.

[0092] Optionally, in the embodiment, the serial peripheral interface bus 604 is a high-speed data transmission link for connecting the complex programmable logic device 208 and the central processing unit 602 in the timing display sub-circuit, and the main function of the serial peripheral interface bus 604 is to realize transmission of the power-on sequence information between the complex programmable logic device 208 and the central processing unit 602, so as to ensure that the timing data recorded by the complex programmable logic device 208 can be accurately transmitted to the central processing unit 602, and avoid display deviation of the power-on sequence caused by data transmission error.

[0093] Optionally, in the embodiment, the timing display sub-circuit is composed of the complex programmable logic device 208, the central processing unit 602 of the server and the display unit 214, and is a cooperative work system for realizing data transmission through the serial peripheral interface bus. The working process is as follows: during the power-on process of the server, the complex programmable logic device 208 monitors the power-on trigger and completion signals of the at least one step-down power supply module 210 in real time, records the power-on sequence, start time and timing interval of each module, and generates power-on sequence information; then, the complex programmable logic device 208 transmits the power-on sequence information to the central processing unit 602 through the serial peripheral interface bus; after receiving the information, the central processing unit 602 analyzes and processes the information, and converts the original data into readable structured information; finally, the central processing unit 602 sends a driving signal to the display unit 214 to control the display unit 214 to directly display the power-on sequence of the at least one step-down power supply module 210 in the form of text, table or timing diagram, and complete the complete process from collection to display of the timing information.

[0094] Through the embodiment provided in the application, the power-on sequence information of the step-down power supply module 210 is recorded in real time by the complex programmable logic device 208, without relying on the oscilloscope to measure the timing, avoiding the tedious operation of repeatedly building a test environment in the traditional debugging, so as to achieve the technical effects of simplifying the timing information collection process and reducing the dependence on professional instruments. The data transmission between the complex programmable logic device 208 and the central processing unit 602 is realized through the serial peripheral interface bus, ensuring high-speed and accurate transmission of the power-on sequence information, avoiding timing display deviation caused by data transmission error or delay, so as to achieve the technical effects of improving the reliability of timing information transmission and ensuring the accuracy of display. The power-on sequence information is parsed by the central processing unit 602 and the display unit 214 is driven to intuitively display, which converts the original data into readable structured information, so that the engineer can quickly master the power-on sequence without interpreting complex data, thereby achieving the technical effects of reducing the difficulty of understanding timing information and improving the debugging efficiency.

[0095] As an optional solution, Figure 7 A schematic diagram of a complex programmable logic device in the embodiment is shown in FIG. 7. Figure 7 As shown in FIG. 7, the complex programmable logic device 208 includes a counter 702, a register 704, and a power-on timing generator 706.

[0096] The counter 702 is configured to obtain the accumulated time between adjacent two state information.

[0097] The register 704 is configured to store the accumulated time.

[0098] The power-on timing generator 706 is configured to generate the power-on sequence information based on the accumulated time.

[0099] Optionally, in the embodiment, the counter 702 is a functional unit in the complex programmable logic device 208 for time measurement, which mainly functions to obtain the accumulated time between adjacent two state information output by the step-down power supply module 210 in units of standard time required by the power-on timing. The accumulated time directly reflects the interval length of the power-on of adjacent modules, and is the core original data for generating the power-on sequence information and verifying whether the timing meets the preset requirements.

[0100] Optionally, in the embodiment, the register 704 is a functional unit in the complex programmable logic device 208 for data storage, which cooperates with the counter 702 and mainly functions to receive and stably store the accumulated time between adjacent two state information obtained by the counter 702, avoiding the loss or covering of the accumulated time data in the subsequent processing process, providing a stable and callable time data source for the power-on timing generator 706, and ensuring that the accumulated time can be accurately read when the power-on sequence information is generated.

[0101] Optionally, in the embodiment, the power-on timing generator 706 is a functional unit in the complex programmable logic device 208 for timing information integration, which functions to calculate the power-on time of each step-down power supply module 210 based on the adjacent state information cumulative time stored in the register 704, in combination with the preset power-on start time, such as the first module power-on time of 0 ms, and further integrate to generate the power-on sequence information containing the module number, power-on time, and adjacent interval.

[0102] It can be understood that the complex programmable logic device 208 is a logic device integrating the counter 702, the register 704, and the power-on timing generator 706. First, when the server is powered on and the first step-down power supply module 210 outputs the power-on normal state information, the counter 702 starts counting in the standard time unit of the power-on timing; when the adjacent next step-down power supply module outputs the power-on normal state information, the counter 702 stops counting and obtains and outputs the cumulative time between the two; then, the register 704 receives and stably stores the cumulative time to avoid data loss; when the cumulative times of all adjacent modules are measured and stored, the power-on timing generator 706 calls all the cumulative times stored in the register 704, in combination with the preset first module power-on start time, to calculate the power-on time of each step-down power supply module, and finally integrate to generate the power-on sequence information containing the module number, power-on time, and adjacent cumulative time.

[0103] Through the embodiments provided in the application, the counter 702 measures the cumulative time of adjacent state information in the standard time unit, avoiding the cumbersome operation of traditional time interval measurement relying on an oscilloscope, thereby achieving the technical effects of simplifying the time sequence time collection process and improving the accuracy of cumulative time measurement. The register 704 stably stores the cumulative time, ensures that the cumulative time data can be stably called in the subsequent timing information generation process, avoids the timing calculation error caused by data loss or coverage, thereby achieving the technical effects of ensuring the reliability of time data and providing a stable data source for timing generation. The power-on timing generator 706 automatically generates structured power-on sequence information based on the cumulative time, without the need for manual arrangement of timing data, avoiding the error caused by manual processing, thereby achieving the technical effects of improving the generation efficiency and accuracy of power-on sequence information.

[0104] As an optional solution, Figure 8 For another server power-on detection device in the embodiment, such as Figure 8As shown, the complex programmable logic device 208 is connected to an external crystal oscillator 302, a digital-to-analog converter 304, a binary converter 806, a comparator 306, a buzzer 802, a first output port, and at least one LED 502. A second output port 810 is connected to the buzzer 808. The complex programmable logic device 208 is connected to at least one step-down power supply module 210 via a first signal line 402 and a second signal line 504. Each step-down power supply module 210 is connected to at least one server component 212. An initial power supply module 804 is connected to at least one step-down power supply module 210. The complex programmable logic device 208 is connected to a central processing unit 602 via a serial peripheral bus 604. The central processing unit 602 is connected to a display unit 214.

[0105] Optionally, in this embodiment, when the complex programmable logic device 208 is powered on, it first counts a standard time using an external crystal oscillator 302. Since timing parameters are typically in the millisecond range, the complex programmable logic device 208 can calculate a theoretical standard time of 1ms. This is then converted from digital to analog via a digital-to-analog converter, compared with the standard value of 1 by a comparator 306, and the result is fed back to the complex programmable logic device 208. If the values ​​are not equal, a buzzer sounds, prompting the engineer to investigate clock-related issues. If the values ​​are equal, it indicates that the external clock module of the complex programmable logic device 208 is functioning correctly and the internal standard time calculation is correct. The complex programmable logic device 208 can then control the power supply of other chips.

[0106] Next, the EN signal of at least one step-down power supply module 210 is controlled by the complex programmable logic device 208 to control the power-on of the corresponding step-down power supply module 210, and the PG signal is used to determine whether the step-down power supply module 210 has been successfully powered on.

[0107] Then, the power-on status is displayed using a binary LED display, with at least one LED 502 indicating the specific status of multiple power supplies. If the complex programmable logic unit 208 detects that the power supply PG is outputting normally, it means that the corresponding power supply is powered on normally. At this time, the counter defined by the complex programmable logic unit 208 accumulates the number of PGs. In this example, if all 9 power supplies output normal PGs, the counter will eventually be 9, which is 1001 in binary display. The corresponding LED will be on and off. If the server buzzer alarm is detected, it means that a power supply is abnormally powered on. The specific abnormal one can be determined by the LED status. For example, if the buzzer alarm is detected and the LED status is on and off, then 0101=5, which means that the 6th power supply is outputting abnormally, and the fault point can be directly located.

[0108] Finally, the power-on time is directly displayed through the serial port, and the complete power-on time information can be directly and conveniently obtained without an oscilloscope. After the clock module is correctly powered on and judged, the complex and editable logic device 208 initializes the counter and initializes the register storing the timing to 0. The power supply PG signal is used as the starting flag, and the standard time is used as the accumulation unit. The counting is performed before the next power supply PG is generated. When the next power supply PG arrives, the counting is stopped, and the value counted by the counter is stored in the register. The counter is cleared to 0 to perform the next round of counting. After the power supply is completely powered on, the power-on timing information is read, and finally the display unit 214 is used for display, so that the complete power-on timing can be displayed.

[0109] The embodiments of the present application also provide a server, which comprises a case and the server power-on detection device.

[0110] The skilled person can further realize that, in order to clearly illustrate the interchangeability of hardware and software, the components of each example described in conjunction with the embodiments disclosed herein have been generally described in the above description in terms of functions. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0111] The above describes in detail the server power-on detection device provided by the present application. The principles and implementation manners of the present application are described by using specific examples in the present application. The above description of the examples is only used to help understand the method of the present application and its core idea. It should be pointed out that, for the ordinary skilled person in the technical field, some improvements and modifications can be made to the present application without departing from the principles of the present application. These improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A server power-on detection apparatus, characterized by, The application relates to a power-on control circuit for a server, which comprises a clock detection circuit, a power-on control circuit and a state indication circuit. The clock detection circuit and the power-on control circuit are multiplexed with a complex programmable logic device; The clock detection circuit is used for detecting an internal clock signal of the complex programmable logic device; The power-on control circuit is used for sending a power-on control signal to at least one step-down power supply module through the complex programmable logic device, wherein the power-on control signal is used for indicating a power-on operation of a server, and at least one step-down power supply module is used for performing the power-on operation on at least one server component in the server; The state indication circuit comprises a display unit, which is used for displaying a power-on sequence of at least one step-down power supply module.

2. The apparatus of claim 1, wherein, The clock detection circuit comprises the complex programmable logic device, an external crystal oscillator, a digital-to-analog converter and a comparator; The external crystal oscillator is connected with the complex programmable logic device, and is used for acquiring a clock count value, which is used for indicating the internal clock signal of the complex programmable logic device; The digital-to-analog converter is connected with the complex programmable logic device, and is used for converting the clock count value into an analog voltage; The comparator is connected with the complex programmable logic device, and is used for comparing the analog voltage with a voltage standard value.

3. The apparatus of claim 2, wherein, The clock detection circuit further comprises a first buzzer; The first buzzer is connected with the comparator, and is used for sending first warning information, which is used for indicating that the internal clock signal of the complex programmable logic device is abnormal.

4. The apparatus of claim 2, wherein, The power-on control circuit comprises the complex programmable logic device, at least one step-down power supply module and at least one server component; The complex programmable logic device is connected with at least one step-down power supply module through a first signal line, and the first signal line is used for transmitting the power-on control signal; Each step-down power supply module is connected with at least one server component, and the step-down power supply module supplies power for at least one server component.

5. The apparatus of claim 4, wherein, The power-on control circuit further comprises an initial power supply module; The initial power supply module is connected with at least one step-down power supply module, and is used for providing an initial voltage for at least one step-down power supply module, and the step-down power supply module is used for converting the initial voltage into a voltage matched with the server.

6. The apparatus of claim 1, wherein, The state indication circuit comprises a state display sub-circuit and a time sequence display sub-circuit, which are multiplexed with the complex programmable logic device; The state display sub-circuit is used for displaying a power-on result of at least one step-down power supply module through the complex programmable logic device; The time sequence display sub-circuit comprises the display unit, and is used for displaying a power-on sequence of at least one step-down power supply module through the display unit.

7. The apparatus of claim 6, wherein, The state display sub-circuit comprises the complex programmable logic device, at least one step-down power supply module and at least one LED lamp. The complex programmable logic device is connected with at least one of the voltage reduction power supply modules through a second signal line, the second signal line is used for transmitting state information, the state information is used for indicating a health state of the voltage reduction power supply module, and the power-on result comprises the state information. A first output port of the complex programmable logic device is connected with at least one of the LED lamps, and the at least one of the LED lamps is used for indicating a position of an abnormal voltage reduction power supply module.

8. The apparatus of claim 7, wherein, The state display sub-circuit further comprises a binary converter and a second buzzer. The binary converter is connected with the complex programmable logic device, and is used for converting the state information into binary information, the binary information being used for indicating a display state of the at least one of the LED lamps. A second output port of the complex programmable logic device is connected with the second buzzer, and the second buzzer is used for emitting second warning information, the second warning information being used for indicating the existence of the abnormal voltage reduction power supply module.

9. The apparatus of claim 7, wherein, The timing display sub-circuit comprises the complex programmable logic device, a central processing unit of the server and the display unit. The complex programmable logic device is connected with the central processing unit through a serial peripheral interface bus, and the central processing unit is used for acquiring power-on sequence information from the complex programmable logic device, the power-on sequence information being used for indicating a power-on sequence of the at least one of the voltage reduction power supply modules. The central processing unit is connected with the display unit.

10. The apparatus of claim 9, wherein, The complex programmable logic device comprises a counter, a register and a power-on timing generator. The counter is used for acquiring cumulative time between adjacent two state information. The register is used for storing the cumulative time. The power-on timing generator is used for generating the power-on sequence information based on the cumulative time.

Images