Circuit assembly and power module packaging structure

Abstract

The utility model belongs to the technical field of semiconductor devices, and discloses a circuit assembly and a power module packaging structure, first chips and second chips are mutually staggered in the transverse direction and the longitudinal direction to form step-shaped arrangement, and the staggered distances of any two adjacent chips in the transverse direction and the longitudinal direction are the same. The unique arrangement mode enables the path lengths from the grid electrode and the Kelvin electrode of each chip to the corresponding pins to realize accurate equal-length connection through the connecting pieces extending longitudinally and transversely; through the design, the parasitic inductance difference between the SiC MOSFET chips connected in parallel is remarkably reduced, so that the inconsistent conduction sequence and unbalanced current distribution caused by nonuniform inductance in the high-speed switching process are avoided; in addition, according to the technical scheme, current oscillation and voltage overshoot in the chip turn-off stage are effectively restrained, the EMI risk is reduced, and the device aging process is slowed down.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a circuit assembly and a power module packaging structure. BACKGROUND

[0002] Some existing silicon carbide (SiC) power module packaging structures include a metal backplane, a circuit assembly arranged on the upper side of the metal backplane, and an outer shell arranged on the metal backplane and the circuit assembly, and the space between the outer shell and the circuit assembly is filled with gel. As shown in the figure, the circuit assembly usually includes a DBC substrate 1' and a plurality of SiC MOSFET chips 2' arranged on the DBC substrate 1', and these SiC MOSFET chips 2' are connected to form a parallel half-bridge circuit through bonding wires 3' and copper electrodes 4' arranged on the surface of the DBC substrate 1' and pins 5' arranged on the DBC substrate 1'; these SiC MOSFET chips 2' are usually arranged in a straight line. Figure 4

[0003] Although this arrangement is convenient for mounting, it inevitably causes differences in path length: the loops of SiC MOSFET chips 2' close to the pins 5' are shorter, and the loops of SiC MOSFET chips 2' far from the pins 5' are longer. Further, the length, span, and arc height of the bonding wires 3' further amplify this imbalance, causing the parasitic inductance difference between the parallel SiC MOSFET chips 2' to reach several nH (nanohenry).

[0004] This inductance difference manifests as inconsistent conduction during high-speed switching, leading to unbalanced current distribution; it also causes current oscillation and voltage overshoot during chip shutdown, increasing the risk of EMI (electromagnetic interference) and accelerating the aging process of the device. As the operating frequency and power density increase, this problem becomes more pronounced, so reducing the parasitic inductance difference is not only crucial for improving the stability and reliability of modules in parallel applications, but also a key bottleneck limiting module performance and reliability. In particular, in a multi-chip parallel structure, the consistency of parasitic inductance between paths directly determines the uniformity of current distribution, and the smaller the inductance difference, the more synchronized the dynamic response between parallel chips, and the lower the risk of system oscillation and overheating.

[0005] Therefore, a new layout is needed to reduce the equivalent "circuit conduction path" (hereinafter referred to as "path") length of SiC MOSFET chips and pins, thereby reducing the parasitic inductance difference between parallel SiC MOSFET chips. CONTENT OF THE INVENTION

[0006] ​The purpose of the present application is to provide a circuit assembly and a power module packaging structure, aiming to solve the problem of uneven parasitic inductance caused by path length difference when SiC MOSFET chips are arranged in a straight line in the existing silicon carbide power module packaging structure, which further leads to current distribution imbalance, current oscillation, voltage overshoot, increased EMI risk, and accelerated device aging.

[0007] In a first aspect, the present application provides a circuit assembly, comprising a DBC substrate and a plurality of SiC MOSFET chips arranged on the DBC substrate, the SiC MOSFET chips being connected in parallel to form a half-bridge circuit through bonding wires and copper electrodes arranged on the surface of the DBC substrate and pins arranged on the DBC substrate; the plurality of SiC MOSFET chips include a plurality of first chips connected in parallel and a plurality of second chips connected in parallel;

[0008] The drain of each first chip is attached to a first drain copper electrode with a first drain pin, and each first chip is staggered in the lateral and longitudinal directions to form a stepped arrangement structure; the staggered distance of any two adjacent first chips in the lateral and longitudinal directions is the same, the gate of each first chip is connected to the same first gate pin through a longitudinally extending connector and a laterally extending connector in sequence, so that the path length from the gate of each first chip to the first gate pin is equal, and the Kelvin pole of each first chip is connected to the same first Kelvin pin through a longitudinally extending connector and a laterally extending connector in sequence, so that the path length from the Kelvin pole of each first chip to the first Kelvin pin is equal;

[0009] The drain of each second chip is attached to a second drain copper electrode with a second drain pin, and each second chip is staggered in the lateral and longitudinal directions to form a stepped arrangement structure; the staggered distance of any two adjacent second chips in the lateral and longitudinal directions is the same, the gate of each second chip is connected to the same second gate pin through a longitudinally extending connector and a laterally extending connector in sequence, so that the path length from the gate of each second chip to the second gate pin is equal, and the Kelvin pole of each second chip is connected to the same second Kelvin pin through a longitudinally extending connector and a laterally extending connector in sequence, so that the path length from the Kelvin pole of each second chip to the second Kelvin pin is equal;

[0010] The longitudinal direction and the lateral direction are two perpendicular directions on the upper surface of the DBC substrate.

[0011] Preferably, the parallel half-bridge circuit comprises a plurality of the first chips, a plurality of the second chips, a source pin, the first Kelvin pin, the first gate pin, the first drain pin, the second Kelvin pin, the second gate pin, and the second drain pin;

[0012] The sources and Kelvin electrodes of all the first chips are connected to the source pin; the drains of all the first chips and the sources and Kelvin electrodes of all the second chips are connected to the first drain pin; the drains of all the second chips are connected to the second drain pin.

[0013] Preferably, each of the first chips has the same orientation, and the laterally extending connections connected to the first chips comprise a laterally extending first gate copper electrode and a laterally extending first Kelvin copper electrode disposed on the DBC substrate, one end of the first gate copper electrode being connected to the first gate pin, and one end of the first Kelvin copper electrode being connected to the first Kelvin pin; the gate electrodes of each of the first chips are each connected to the first gate copper electrode through a longitudinally extending connection; and the Kelvin electrodes of each of the first chips are each connected to the first Kelvin copper electrode through a longitudinally extending connection.

[0014] Preferably, the connection between the Kelvin electrode of at least one of the first chips and the first Kelvin copper electrode comprises a bonding wire and a transition copper electrode connected to each other to form a spanning bonding structure.

[0015] Preferably, each of the second chips has the same orientation, and the laterally extending connections connected to the second chips comprise a laterally extending second gate copper electrode and a laterally extending second Kelvin copper electrode disposed on the DBC substrate, one end of the second gate copper electrode being connected to the second gate pin, and one end of the second Kelvin copper electrode being connected to the second Kelvin pin; the gate electrodes of each of the second chips are each connected to the second gate copper electrode through a longitudinally extending connection; and the Kelvin electrodes of each of the second chips are each connected to the second Kelvin copper electrode through a longitudinally extending connection.

[0016] Preferably, the connection between the Kelvin electrode of at least one of the second chips and the second Kelvin copper electrode comprises a bonding wire and a transition copper electrode connected to each other to form a spanning bonding structure.

[0017] Preferably, the first gate copper electrode and the first Kelvin copper electrode are disposed on the same side of the longitudinal direction of the first drain copper electrode, the other side of the longitudinal direction of the first drain copper electrode further comprising a first source copper electrode, the source pin being disposed on the first source copper electrode, and the sources and Kelvin electrodes of all the first chips being connected to the first source copper electrode through bonding wires.

[0018] Preferably, the second gate copper electrode and the second Kelvin copper electrode are arranged on the same side of the longitudinal direction of the second drain copper electrode, and the other side of the longitudinal direction of the second drain copper electrode is further provided with a second source copper electrode, the source and the Kelvin electrode of all the second chips are connected with the second source copper electrode through bonding wires, and the second source copper electrode is connected with the first drain copper electrode through a copper clip.

[0019] Preferably, the first gate pin and the first Kelvin pin are arranged at one end of the transverse direction of the DBC substrate, and the second gate pin and the second Kelvin pin are arranged at the other end of the transverse direction of the DBC substrate; the first drain pin is arranged at one end of the first drain copper electrode away from the second drain copper electrode, and the second drain pin is arranged at one end of the second drain copper electrode away from the first drain copper electrode.

[0020] In a second aspect, the present application provides a power module packaging structure, comprising a metal base plate, a circuit assembly as described above and a plastic package shell, the circuit assembly is arranged on the upper side of the metal base plate, the plastic package shell covers the metal base plate and the circuit assembly, and the space between the plastic package shell and the circuit assembly is filled with an organic silicone gel.

[0021] Beneficial effects: the circuit assembly and the power module packaging structure provided by the present application, each first chip and each second chip are staggered in the transverse direction and the longitudinal direction to form a stepped arrangement, and the staggered distance of any two adjacent chips in the transverse direction and the longitudinal direction is the same. This unique arrangement allows the path length from the gate and the Kelvin electrode of each chip to the corresponding pin to be accurately equalized through the longitudinal and transverse extending connectors. Through this design, the parasitic inductance difference between each parallel SiC MOSFET chip is significantly reduced, thereby avoiding inconsistent conduction and current distribution imbalance caused by uneven inductance during high-speed switching. In addition, this technical solution effectively suppresses current oscillation and voltage overshoot during chip shutdown, reduces EMI risk, and slows down the device aging process. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A schematic diagram of a circuit assembly provided by the present application.

[0023] Figure 2 A circuit structure diagram of a circuit assembly provided by the present application.

[0024] Figure 3 An exploded view of a power module packaging structure provided by the present application.

[0025] Figure 4A schematic diagram of a circuit assembly in the prior art.

[0026] Figure 5 An exploded view of a conventional power module package structure.

[0027] Figure 6 A heat dissipation simulation result of a conventional power module package structure.

[0028] Figure 7 A temperature distribution of SiC MOSFET chips in a heat dissipation simulation result of a conventional power module package structure.

[0029] Figure 8 A temperature distribution of copper electrodes in a heat dissipation simulation result of a conventional power module package structure.

[0030] Figure 9 A heat dissipation simulation result of a power module package structure of the present application.

[0031] Figure 10 A temperature distribution of SiC MOSFET chips in a heat dissipation simulation result of a power module package structure of the present application.

[0032] Figure 11 A temperature distribution of copper electrodes in a heat dissipation simulation result of a power module package structure of the present application.

[0033] BRIEF DESCRIPTION OF THE DRAWINGS: 1. DBC substrate; 2. bonding wire; 3. first chip; 4. second chip; 5. first drain pin; 6. first drain copper electrode; 7. first gate pin; 8. first Kelvin pin; 9. second drain pin; 10. second drain copper electrode; 11. second gate pin; 12. second Kelvin pin; 13. source pin; 14. first gate copper electrode; 1401. first extension; 15. first Kelvin copper electrode; 16. transition copper electrode; 17. second gate copper electrode; 1701. second extension; 18. second Kelvin copper electrode; 19. first source copper electrode; 20. second source copper electrode; 21. copper clip; 100. metal backplate; 101. circuit assembly; 102. plastic package; 103. silicone-based gel; 104. heat sink. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0035] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0036] Please refer to Figures 1-2 In some embodiments of the present application, a circuit component includes a DBC substrate 1 and a plurality of SiC MOSFET chips arranged on the DBC substrate 1, and the SiC MOSFET chips are connected in parallel to form a half-bridge circuit (circuit structure reference Figure 2 ) through bonding wires 2 and copper electrodes (patterned copper layers) arranged on the surface of the DBC substrate 1 and pins arranged on the DBC substrate 1;

[0037] The drain of each first chip 3 is attached to the same first drain copper electrode 6 provided with a first drain pin 5, and each first chip 3 is staggered in the lateral and longitudinal directions to form a stepped arrangement structure; the staggered distance of any two adjacent first chips 3 in the lateral and longitudinal directions is the same, the gate of each first chip 3 is connected to the same first gate pin 7 through a longitudinally extending connecting member and a laterally extending connecting member in sequence, so that the path length of the gate of each first chip 3 to the first gate pin 7 is equal, and the Kelvin pole of each first chip 3 is connected to the same first Kelvin pin 8 through a longitudinally extending connecting member and a laterally extending connecting member in sequence, so that the path length of the Kelvin pole of each first chip 3 to the first Kelvin pin 8 is equal;

[0038] The drain of each second chip 4 is attached to the same second drain copper electrode 10 provided with a second drain pin 9, and each second chip 4 is staggered in the lateral and longitudinal directions to form a stepped arrangement structure; the staggered distance of any two adjacent second chips 4 in the lateral and longitudinal directions is the same, the gate of each second chip 4 is connected to the same second gate pin 11 through the longitudinally and laterally extending connectors in sequence, so that the path length of the gate of each second chip 4 to the second gate pin 11 is equal, and the Kelvin pole of each second chip 4 is connected to the same second Kelvin pin 12 through the longitudinally and laterally extending connectors in sequence, so that the path length of the Kelvin pole of each second chip 4 to the second Kelvin pin 12 is equal;

[0039] The longitudinal and lateral directions are two mutually perpendicular directions on the upper surface of the DBC substrate 1 (for example, the lateral direction can be the length direction of the DBC substrate 1, and the longitudinal direction can be the width direction of the DBC substrate 1, but not limited thereto).

[0040] The circuit assembly proposed in the present application effectively balances the parasitic inductance of each parallel SiC MOSFET chip through a clever chip arrangement and connection method. The DBC substrate 1 (copper-clad ceramic substrate) is a commonly used power module substrate, which has excellent heat dissipation and electrical insulation performance, providing a stable working environment for SiC MOSFET chips. SiC MOSFET chips are silicon carbide metal-oxide-semiconductor field effect transistors, which are widely used in the power electronics field due to their high voltage resistance, low loss, and high switching frequency. The bonding wire 2 is usually made of aluminum or copper, which is used to connect the chip electrodes and copper electrodes or pins. The copper electrode is a conductive layer provided on the surface of the DBC substrate 1, which is used to realize the electrical connection between the chip and the pin. The pin is the interface for connecting the circuit assembly to the external circuit. The parallel half-bridge circuit is a common power conversion circuit topology, which works by connecting multiple SiC MOSFET chips in parallel to achieve higher current carrying capacity. The longitudinal and lateral directions refer to the two perpendicular directions on the upper surface of the DBC substrate 1, which are used to describe the arrangement of the chips and the extension direction of the connectors.

[0041] The circuit assembly of the present application effectively solves the problem of uneven parasitic inductance of parallel SiC MOSFET chips in the prior art through a unique stepped chip arrangement structure and equal-length path connection design. Specifically, the traditional existing SiC MOSFET chips are usually arranged in a straight line, which results in shorter chip loops near the pins and longer chip loops away from the pins, thereby causing differences in parasitic inductance. This uneven inductance can cause current distribution imbalance during high-speed switching, leading to inconsistent chip conduction, and further causing current oscillation and voltage overshoot, which not only increases the risk of electromagnetic interference (EMI), but also accelerates the aging process of the device.

[0042] The present application forms a stepped arrangement structure by staggering the plurality of first chips 3 and the plurality of second chips 4 in the lateral direction and the longitudinal direction respectively, and ensures that the staggering distance of any two adjacent chips in the lateral direction and the longitudinal direction is the same, so that the path length of the gate to the gate pin of each chip is equal, and the path length of the Kelvin to the Kelvin pin of each chip is equal. This design makes the parasitic inductance of the control signal path and the Kelvin sensing path of each parallel chip consistent. When the parasitic inductance of the gate drive path and the Kelvin sensing path of all parallel chips is equal, the conduction and turn-off of each chip will be more synchronized and the current distribution will be more uniform during high-speed switching. As a result, the risk of current oscillation and voltage overshoot can be significantly reduced, the stability and reliability of the module can be improved, and electromagnetic interference can be effectively reduced. The present application ingeniously realizes the equal path length of the gate and Kelvin of each parallel chip to the corresponding pin by introducing a stepped arrangement combined with longitudinally and laterally extending connecting pieces. This design significantly reduces the difference in parasitic inductance of each parallel chip, thereby achieving more uniform current distribution and more synchronized switching behavior during high-speed switching.

[0043] Specifically, see Figure 2 The parallel half-bridge circuit includes a plurality of first chips 3, a plurality of second chips 4, a source pin 13, a first Kelvin pin 8, a first gate pin 7, a first drain pin 5, a second Kelvin pin 12, a second gate pin 11, and a second drain pin 9.

[0044] The source and Kelvin of all first chips 3 are connected to the source pin 13, the Kelvin of all first chips 3 is also connected to the first Kelvin pin 8, and the gate of all first chips 3 is connected to the first gate pin 7; the drain of all first chips 3 and the source and Kelvin of all second chips 4 are connected to the first drain pin 5; the Kelvin of all second chips 4 is also connected to the second Kelvin pin 12, the gate of all second chips 4 is connected to the second gate pin 11, and the drain of all second chips 4 is connected to the second drain pin 9.

[0045] The source pin 13 is usually connected as the common negative pole or DC negative bus connection point of the half-bridge circuit, used to collect the source current of all first chips 3. The first Kelvin pin 8 and the second Kelvin pin 12 are respectively used for independent sensing of the Kelvin poles of the first chip group (i.e. all first chips 3) and the second chip group (i.e. all second chips 4), to provide more accurate voltage feedback, which is crucial for realizing accurate gate drive control and overcurrent protection. The first gate pin 7 and the second gate pin 11 are respectively used for providing independent drive signals to the gates of the first chip group and the second chip group, so as to realize independent control of the high-side and low-side switches of the half-bridge circuit. The first drain pin 5 is the key connection point of the half-bridge circuit, which connects the drains of all first chips 3 with the sources and Kelvin poles of all second chips 4, forming the middle output node of the half-bridge, which is usually connected to the load. The second drain pin 9 is the common positive pole or DC positive bus connection point of the half-bridge circuit, used to connect the drains of all second chips 4. Through such a clear connection configuration, the electrical topology of the half-bridge circuit is clear and functional.

[0046] Through the above technical solution, the present application can provide a parallel half-bridge circuit with clear structure and definite function. Such a clear pin connection mode helps to realize more balanced current distribution among the parallel chips, reduces the risk of local hot spots, and thus improves the reliability and life of the power module. In addition, the independent gate pin and Kelvin pin design enables the high-side and low-side switches to be independently and accurately controlled and monitored, which has significant advantages for optimizing switch performance, reducing switch loss, and realizing fast-response protection functions. Overall, this scheme effectively improves the electrical performance and operating stability of the half-bridge circuit.

[0047] In some preferred embodiments, see Figure 1 , each first chip 3 is oriented in the same direction, and the laterally extending connecting member connected to the first chip 3 includes a laterally extending first gate copper electrode 14 and a laterally extending first Kelvin copper electrode 15 provided on the DBC substrate 1, one end of the first gate copper electrode 14 being connected to the first gate pin 7, and one end of the first Kelvin copper electrode 15 being connected to the first Kelvin pin 8; the gate of each first chip 3 is connected to the first gate copper electrode 14 through a longitudinally extending connecting member; and the Kelvin pole of each first chip 3 is connected to the first Kelvin copper electrode 15 through a longitudinally extending connecting member.

[0048] Specifically, the first chips 3 are oriented in the same direction, which means that the placement direction of all the first chips 3 on the DBC substrate 1 is consistent, so that the relative positions of their gate electrodes and Kelvin electrodes are predictable and consistent, which helps to simplify the subsequent wiring design. The DBC substrate 1 is provided with a first gate copper electrode 14 extending in the transverse direction and a first Kelvin copper electrode 15 extending in the transverse direction, which serve as common busbars for collecting or distributing gate signals and Kelvin signals from multiple first chips. Among them, one end of the first gate copper electrode 14 is connected to the first gate pin 7, and one end of the first Kelvin copper electrode 15 is connected to the first Kelvin pin 8, thereby electrically connecting these common busbars to the external control or detection circuit. Further, the gate of each first chip 3 is connected to the first gate copper electrode 14 through a longitudinally extending connection, and the Kelvin electrode of each first chip 3 is connected to the first Kelvin copper electrode 15 through a longitudinally extending connection. The longitudinally extending connection here can be understood as a bonding wire or other conductive connection structure, which mainly extends in the longitudinal direction of the DBC substrate 1 to connect the corresponding electrodes of each first chip 3 to the transversely extending common copper electrode.

[0049] The scheme of the present application effectively simplifies the connection path from each first chip 3 to the corresponding pin by introducing the first gate copper electrode 14 and the first Kelvin copper electrode 15 extending in the transverse direction as common busbars, and connecting the gate and Kelvin electrodes of each first chip 3 to these common busbars through longitudinally extending connections. Since the first chips 3 are arranged in a stepped manner, their gate and Kelvin electrodes are longitudinally misaligned, while the transversely extending common copper electrode can span these longitudinal misalignments, so that each chip only needs to be connected to the common electrode through a relatively simple longitudinal connection. This design avoids the need to design complex longitudinal and transverse combined connections for each chip, thereby reducing wiring complexity. At the same time, by carefully designing the width and thickness of the common copper electrode, and the length and material of the longitudinal connection, the overall path length from the gate and Kelvin electrodes of each first chip 3 to the corresponding pin can still be kept highly consistent, thereby maintaining the performance advantages of current sharing and switch synchronization.

[0050] Through the above technical scheme, the wiring complexity of the circuit assembly can be significantly reduced, especially when multiple SiC MOSFET chips are arranged in a stepped manner, the connection structure of the gate and Kelvin electrodes can be effectively simplified. In addition, this scheme helps to optimize the space utilization on the DBC substrate 1, reducing the area occupied by the connections, thereby possibly achieving higher power density or more compact packaging. At the same time, due to the simplification and standardization of the connection path, it is also beneficial to improve manufacturing efficiency and reduce production cost, and under the premise of ensuring the consistency of the path length, the overall performance and reliability of the circuit assembly are further improved.

[0051] In some preferred embodiments, referring to Figure 1 The connection between the Kelvin pole of the at least one first chip 3 and the first Kelvin copper electrode 15 comprises a bonding wire 2 and a transition copper electrode 16 connected to each other to form a spanning bonding structure.

[0052] Specifically, the above connection is no longer a single longitudinally extending structure, but is jointly formed by the bonding wire 2 and the transition copper electrode 16 to form a spanning bonding structure. The bonding wire 2 generally refers to a metal wire such as a gold wire, an aluminum wire or a copper wire that connects the chip electrode and the copper electrode on the substrate through a bonding process. The transition copper electrode 16 here refers to an intermediate copper layer arranged on the surface of the DBC substrate 1 for connecting the bonding wire 2 and the first Kelvin copper electrode 15. The spanning bonding structure can be understood as that the bonding wire 2 is drawn from the Kelvin pole of the chip, connected to the transition copper electrode 16 on the DBC substrate 1, and then connected to the transition copper electrode 16 and the first Kelvin copper electrode 15 through the bonding wire 2. This structure allows the bonding wire 2 to be more flexible in space for wiring, thereby optimizing the connection path.

[0053] Through the above technical solution, since the spanning bonding structure formed by the bonding wire 2 and the transition copper electrode 16, the connection path between the Kelvin pole of the first chip 3 and the corresponding copper electrode is optimized. This optimization helps to achieve lower parasitic inductance and more uniform current distribution, especially when multiple first chips 3 work in parallel, which can effectively improve the consistency of the Kelvin pole sensing signals between the chips, thereby improving the switching efficiency and reliability of the entire circuit assembly; in addition, it can avoid the deformation of the bonding wire 2 during the encapsulation process due to its excessive length, which can cause electrical failure. Compared with a simple longitudinally extending connection, the present solution not only ensures electrical performance, but also enhances the mechanical strength and thermal stability of the connection, further improving the overall performance and service life of the power module.

[0054] Further, referring to Figure 1 The first gate copper electrode 14 is provided with a first extension 1401 extending towards the at least one first chip 3, and the first extension 1401 is connected to the gate of the corresponding first chip 3 through a bonding wire 2.

[0055] Due to the adoption of the bonding wire 2 and the first extension 1401, the connection path between the gate of the first chip 3 and the corresponding first gate copper electrode 14 is optimized. This optimization helps to achieve lower parasitic inductance and more uniform current distribution, especially when multiple first chips 3 work in parallel, which can effectively improve the consistency of the gate sensing signal between chips, thereby improving the switching efficiency and reliability of the entire circuit assembly; in addition, it can avoid the deformation of the bonding wire 2 during the encapsulation process due to its excessive length, which can cause electrical failure. Compared with a simple longitudinal extension connector, the present scheme not only ensures electrical performance, but also enhances the mechanical strength and thermal stability of the connection, further improving the overall performance and service life of the power module.

[0056] In some embodiments, see Figure 1 , the orientations of the second chips 4 are the same, and the transversely extending connectors connected to the second chips 4 include a transversely extending second gate copper electrode 17 and a transversely extending second Kelvin copper electrode 18 provided on the DBC substrate 1, one end of the second gate copper electrode 17 is connected to the second gate pin 11, and one end of the second Kelvin copper electrode 18 is connected to the second Kelvin pin 12; the gates of each second chip 4 are respectively connected to the second gate copper electrode 17 through a longitudinally extending connector; and the Kelvin poles of each second chip 4 are respectively connected to the second Kelvin copper electrode 18 through a longitudinally extending connector.

[0057] Specifically, the orientations of the second chips 4 being the same means that the placement directions of all the parallelly connected second chips 4 on the DBC substrate 1 are consistent. This consistency helps to simplify the overall layout design and ensures that the electrical characteristics of each chip have higher consistency when working in parallel. Among them, the DBC substrate 1 is provided with a transversely extending second gate copper electrode 17 and a transversely extending second Kelvin copper electrode 18, which serve as the main conduction path for collecting or distributing signals from or to the second gate pin 11 and the second Kelvin pin 12. The transversely extending arrangement of these copper electrodes, in cooperation with the stepped arrangement structure of the second chips 4, can form a regular wiring channel. One end of the second gate copper electrode 17 is connected to the second gate pin 11, and one end of the second Kelvin copper electrode 18 is connected to the second Kelvin pin 12, thereby effectively leading the gate and Kelvin pole signals of the internal chips to the external pins. In addition, the gates of each second chip 4 are respectively connected to the second gate copper electrode 17 through a longitudinally extending connector, and the Kelvin poles of each second chip 4 are respectively connected to the second Kelvin copper electrode 18 through a longitudinally extending connector. The longitudinally extending connector here can be understood as a wire or copper trace leading from the gate or Kelvin pole of each second chip 4 and connected to the transversely extending copper electrode. The combination of this longitudinal connection and transverse main electrode provides a structural basis for achieving equal-length paths.

[0058] The technical scheme of the present application sets all the second chips 4 to the same orientation, and uses the second gate copper electrodes 17 and the second Kelvin copper electrodes 18 extending in the lateral direction as the main trunk lines, and then connects the gate and the Kelvin electrode of each second chip 4 to the corresponding lateral copper electrode through the longitudinal connecting members. This layout makes the length of the longitudinal connecting members of each second chip 4 to its corresponding lateral copper electrode be precisely controlled and designed, thereby ensuring that the path length of the gate of all the second chips 4 to the second gate pin 11 and the path length of the Kelvin electrode to the second Kelvin pin 12 can be kept highly consistent. Meanwhile, due to the staggered arrangement of the second chips 4 in the lateral and longitudinal directions, this combination of the lateral main electrodes and the longitudinal branch connections can effectively adapt to the staggered arrangement, avoiding complex cross-wiring and simplifying the design and manufacturing process.

[0059] Through the above technical scheme, since the orientations of the second chips 4 are consistent, and the gate and the Kelvin electrode are connected through the copper electrodes extending in the lateral direction and the connecting members extending in the longitudinal direction, the wiring structure is more regular and symmetrical. This not only simplifies the manufacturing process of the circuit assembly and reduces the production cost, but also more accurately controls the path length of the gate and the Kelvin electrode of each parallel second chip, thereby effectively reducing the electrical parameter difference between the chips and improving the current sharing performance and switching synchronization of parallel operation. In addition, this layout also helps to optimize the space utilization on the DBC substrate 1 and reduce the parasitic inductance and parasitic resistance, further improving the overall electrical performance and reliability of the circuit assembly.

[0060] Preferably, as shown in Figure 1 , the connecting member between the Kelvin electrode of at least one second chip 4 and the second Kelvin copper electrode 18 comprises a bonding wire 2 and a transition copper electrode 16 connected to each other to form a spanning bonding structure.

[0061] Specifically, the above connecting member is no longer a single longitudinal extension structure, but is composed of the bonding wire 2 and the transition copper electrode 16, and forms a spanning bonding structure. The bonding wire 2 generally refers to a metal wire such as a gold wire, an aluminum wire or a copper wire for connecting the chip electrode and the copper electrode on the substrate through a bonding process. The transition copper electrode 16 here refers to an intermediate copper layer arranged on the surface of the DBC substrate 1 for connecting the bonding wire 2 and the second Kelvin copper electrode 18. The spanning bonding structure can be understood as that the bonding wire 2 is drawn from the Kelvin electrode of the chip, connected to the transition copper electrode 16 on the DBC substrate 1, and then connected the transition copper electrode 16 and the second Kelvin copper electrode 18 through the bonding wire 2. This structure allows the bonding wire 2 to be more flexible in space, thereby optimizing the connection path.

[0062] By the technical scheme, the connection path between the Kelvin pole of the second chip 4 and the corresponding copper electrode is optimized due to the spanning bonding structure formed by the bonding wire 2 and the transition copper electrode 16. The optimization helps to realize lower parasitic inductance and more uniform current distribution, especially when multiple second chips 4 work in parallel, which can effectively improve the consistency of the Kelvin pole sensing signal between the chips, thereby improving the switching efficiency and reliability of the entire circuit assembly; in addition, the deformation of the bonding wire 2 during the encapsulation glue filling process due to the overlong bonding wire 2 can be avoided, which can cause electrical failure. Compared with a simple longitudinal extension connector, the scheme not only ensures the electrical performance, but also enhances the mechanical strength and thermal stability of the connection, further improving the overall performance and service life of the power module.

[0063] Further, see Figure 1 The second gate copper electrode 17 is provided with a second extension part 1701 extending towards at least one second chip 4, and the second extension part 1701 is connected with the gate of the corresponding second chip 4 through the bonding wire 2.

[0064] Due to the bonding wire 2 and the second extension part 1701, the connection path between the gate of the second chip 4 and the corresponding second gate copper electrode 17 is optimized. The optimization helps to realize lower parasitic inductance and more uniform current distribution, especially when multiple second chips 4 work in parallel, which can effectively improve the consistency of the gate sensing signal between the chips, thereby improving the switching efficiency and reliability of the entire circuit assembly; in addition, the deformation of the bonding wire 2 during the encapsulation glue filling process due to the overlong bonding wire 2 can be avoided, which can cause electrical failure. Compared with a simple longitudinal extension connector, the scheme not only ensures the electrical performance, but also enhances the mechanical strength and thermal stability of the connection, further improving the overall performance and service life of the power module.

[0065] In some embodiments, see Figure 1 The first gate copper electrode 14 and the first Kelvin copper electrode 15 are arranged on the same side of the longitudinal direction of the first drain copper electrode 6, and the other side of the longitudinal direction of the first drain copper electrode 6 is further provided with a first source copper electrode 19, and the source pin 13 is arranged on the first source copper electrode 19, and the source and the Kelvin pole of all the first chips 3 are connected with the first source copper electrode 19 through the bonding wire 2.

[0066] In particular, the first gate copper electrode 14 and the first Kelvin copper electrode 15 are arranged on the same side of the longitudinal direction of the first drain copper electrode 6, which means that on the surface of the DBC substrate 1, these electrodes are in the same direction relative to the first drain copper electrode 6 in the longitudinal direction. At the same time, the other side of the longitudinal direction of the first drain copper electrode 6 is used to arrange the first source copper electrode 19, thereby forming a symmetrical or semi-symmetrical layout, so that the first drain copper electrode 6 is sandwiched between the first gate copper electrode 14 / first Kelvin copper electrode 15 and the first source copper electrode 19. The first source copper electrode 19 is an independent copper electrode area, which aims to provide a common connection point for the source and Kelvin electrodes of all first chips 3. The source pin 13 is directly arranged on the first source copper electrode 19 to ensure a low-impedance connection of the main current path. The source and Kelvin electrodes of all first chips 3 are connected to the first source copper electrode 19 through bonding wires 2, which can provide reliable electrical connection as a common connection method.

[0067] In some embodiments, see Figure 1 The first gate copper electrode 14 is arranged between the first Kelvin copper electrode 15 and the first drain copper electrode 6.

[0068] The scheme of the present application realizes the clarification and modularization of the electrode layout by arranging the first gate copper electrode 14 and the first Kelvin copper electrode 15 on the same side of the longitudinal direction of the first drain copper electrode 6, and arranging the first source copper electrode 19 on the other side of the longitudinal direction of the first drain copper electrode 6. This layout helps to optimize the wiring path on the DBC substrate 1, reduce the intersection and overlap between different electrodes, and thus reduce the complexity of the wiring. It is due to the fact that the first source copper electrode 19 is specially arranged for connecting the source and Kelvin electrodes of all first chips 3, and the source pin 13 is directly arranged on the first source copper electrode 19, that the source current path of the first chip 3 is concentrated and shortened, effectively reducing the parasitic inductance and parasitic resistance, which is crucial for improving the switching speed and efficiency of the SiC MOSFET chip.

[0069] Through the above technical scheme, due to the optimization of the electrode layout and the introduction of the first source copper electrode 19, the overall wiring of the circuit assembly becomes more regular and compact, effectively improving the space utilization. More importantly, the scheme significantly reduces the parasitic inductance and parasitic resistance of the first chip 3 source loop, thereby reducing the voltage overshoot and current oscillation in the switching transient process, and improving the switching performance and reliability of the SiC MOSFET chip. In addition, concentrating the connection of the source and Kelvin electrodes of all first chips 3 to the same first source copper electrode 19 helps to improve the current sharing characteristics between parallel chips, further improving the overall performance and stability of the circuit assembly.

[0070] Further, seeFigure 1 The second gate copper electrode 17 and the second Kelvin copper electrode 18 are arranged on the same side of the longitudinal direction of the second drain copper electrode 10. The other side of the longitudinal direction of the second drain copper electrode 10 is also provided with a second source copper electrode 20. The source and the Kelvin electrode of all the second chips 4 are connected to the second source copper electrode 20 through the bonding wires 2. The second source copper electrode 20 is connected to the first drain copper electrode 6 through the copper clip 21.

[0071] Specifically, the second gate copper electrode 17 and the second Kelvin copper electrode 18 are arranged on the same side of the longitudinal direction of the second drain copper electrode 10. This layout helps to effectively isolate or optimize the wiring of the control signal (gate) and the sensing signal (Kelvin electrode) from the main current path (drain), thereby reducing mutual interference and facilitating subsequent connection.

[0072] The other side of the longitudinal direction of the second drain copper electrode 10, i.e. the side opposite to the second gate copper electrode 17 and the second Kelvin copper electrode 18, is provided with a second source copper electrode 20. This second source copper electrode 20 is specially used to collect the current of the source and the Kelvin electrode of all the second chips 4. By providing a separate second source copper electrode 20, a clear and concentrated connection point can be provided for the source and the Kelvin electrode of the second chip 4, avoiding current dispersion and thereby optimizing the current collection path.

[0073] In actual application, the source and the Kelvin electrode of all the second chips 4 are connected to the second source copper electrode 20 through the bonding wires 2. As a common connection method, the bonding wires 2 can reliably connect the corresponding terminals of the second chip 4 to the second source copper electrode 20. This connection method ensures that the source and the Kelvin electrode of the second chip 4 can effectively form an electrical connection with the second source copper electrode 20, laying the foundation for subsequent current transmission.

[0074] Among them, the second source copper electrode 20 is connected to the first drain copper electrode 6 through the copper clip 21. The copper clip 21 is a kind of connecting piece with good electrical conductivity and mechanical strength, and its purpose is to establish a low-resistance and low-inductance electrical path between the second source copper electrode 20 and the first drain copper electrode 6. In a half-bridge circuit, the source and the Kelvin electrode of the second chip 4 are usually connected to the drain of the first chip 3 to form the middle node of the half-bridge. By using the copper clip 21 for connection, the current path of the middle node can be significantly shortened, and the connection resistance and parasitic inductance can be reduced, thereby improving the switching speed and efficiency of the half-bridge circuit.

[0075] In some embodiments, see Figure 1 The second gate copper electrode 17 is arranged between the second Kelvin copper electrode 18 and the second drain copper electrode 10.

[0076] The scheme of the present application realizes the optimized layout of the electrode connection points of the second chip 4 by arranging the second gate copper electrode 17 and the second Kelvin copper electrode 18 on the same side of the longitudinal direction of the second drain copper electrode 10 and introducing the independent second source copper electrode 20 on the other side of the second drain copper electrode 10. Due to this layout, the control signal and the main current path can be effectively distinguished and optimized. Further, by collecting the sources and Kelvin electrodes of all the second chips 4 to the second source copper electrode 20 and connecting the second source copper electrode 20 with the first drain copper electrode 6 by the copper clip 21, a short and wide current path is formed at the middle node of the half-bridge circuit. This design effectively shortens the current path from the second chip source to the middle node of the half-bridge, significantly reduces the parasitic inductance and resistance on the path, thereby reducing the switching loss and improving the dynamic performance.

[0077] Through the above technical scheme, due to the optimized layout of the second gate copper electrode 17, the second Kelvin copper electrode 18 and the second source copper electrode 20, and the connection between the second source copper electrode 20 and the first drain copper electrode 6 by the copper clip 21, the current path of the second chip 4 is significantly optimized. This not only effectively reduces the parasitic inductance and resistance and reduces the switching loss, but also improves the switching speed and efficiency of the circuit component. In addition, the copper clip connection mode also enhances the mechanical strength and heat dissipation performance of the connection, thereby improving the reliability and power density of the circuit component.

[0078] In some possible implementations, as shown in Figure 3 , the first gate pin 7 and the first Kelvin pin 8 are arranged at one end of the transverse direction of the DBC substrate 1, and the second gate pin 11 and the second Kelvin pin 12 are arranged at the other end of the transverse direction of the DBC substrate 1; the first drain pin 5 is arranged at one end of the first drain copper electrode 6 away from the second drain copper electrode 10, and the second drain pin 9 is arranged at one end of the second drain copper electrode 10 away from the first drain copper electrode 6.

[0079] Through the above technical scheme, the circuit component of the present application can significantly optimize the layout of the main power pins, thereby effectively reducing the parasitic inductance of the entire parallel half-bridge circuit, especially the parasitic inductance of the main current loop. This optimization helps to reduce the voltage overshoot and current oscillation in the switching transient process, improves the switching speed and efficiency. At the same time, the symmetrical or opposite layout of the pins makes the current distribution on the DBC substrate 1 more uniform, which helps to improve the current sharing between the chips and avoid local hot spots, thereby improving the reliability and life of the power module. In addition, the clear pin interface design also simplifies the integration and external connection of the power module, reducing the complexity of the system-level design.

[0080] In the present application, the material and size of the bonding wire 2 can be set according to actual needs. For example, in some possible embodiments, the bonding wires connected to the gates and Kelvin electrodes of the first chip 3 and the second chip 4 are all aluminum wires with a wire diameter of 5 mil, and the bonding wires connected to the sources are all aluminum wires with a wire diameter of 15 mil.

[0081] Reference Figure 1 The present application provides a power module packaging structure, which comprises a metal base plate 100, a circuit assembly 101 as described above, and a plastic encapsulation shell 102. The circuit assembly 101 is arranged on the upper side of the metal base plate 100, and the plastic encapsulation shell 102 is arranged on the metal base plate 100 and the circuit assembly 101. The space between the plastic encapsulation shell 102 and the circuit assembly 101 is filled with an organic silicone-based gel 103.

[0082] Specifically, the metal base plate 100 is usually made of a material with good thermal conductivity and mechanical strength, such as copper, aluminum, copper alloy, or aluminum alloy. Its main function is to provide mechanical support for the circuit assembly 101 and serve as the main heat dissipation path to effectively conduct the heat generated by the circuit assembly 101 during operation. The circuit assembly 101 is arranged on the upper side of the metal base plate 100 and is usually tightly connected to the metal base plate 100 through welding, sintering, or thermal conductive glue, etc. to ensure good thermal contact and mechanical fixation.

[0083] The plastic encapsulation shell 102 is used to protect the circuit assembly 101 externally and is usually made of an insulating and environment-resistant material, such as epoxy resin, phenolic resin, or ceramic, etc. The plastic encapsulation shell 102 is arranged on the metal base plate 100 and the circuit assembly 101 to form a closed cavity, which isolates the circuit assembly 101 from the external environment. The space between the plastic encapsulation shell 102 and the circuit assembly 101 is filled with an organic silicone-based gel 103. The organic silicone-based gel 103 (such as a silicone ester gel) has excellent insulation performance, high-temperature resistance, and good flexibility, which can effectively fill the gaps around the circuit assembly 101, prevent moisture and contaminants from entering, and also buffer mechanical stress, further assisting heat dissipation, and improving the reliability of the package.

[0084] By the technical solution, the power module packaging structure can provide comprehensive protection and optimized thermal management for the circuit component 101. Specifically, the introduction of the metal backplane 100 significantly enhances the heat dissipation capacity of the module, effectively reduces the working temperature of the SiC MOSFET chip, thereby prolonging the service life of the device and improving the power output capacity of the module. The setting of the plastic package shell 102 ensures the reliable operation of the circuit component in harsh environments, effectively resisting the invasion of external factors such as moisture, dust, and mechanical stress. The filling of the organic silicone gel 103 further improves the insulation performance and thermal stress resistance of the module, avoiding internal short circuit and structural damage caused by thermal expansion mismatch. Therefore, the power module packaging structure not only improves the reliability and stability of the circuit component, but also enables it to adapt to a wider and more severe application environment, achieving high-performance and high-reliability packaging of the power module.

[0085] Further, a heat sink 104 can be provided at the bottom of the metal backplane 100.

[0086] The working states of the circuit components in Figure 4 and Figure 1 are simulated respectively to analyze and compare the parasitic inductance of each current path of the SiC MOSFET chips. The simulation conditions include: the simulation current is applied according to the given continuous forward current (62A) size of the SiC MOSFET chip specification book, the SiC MOSFET chip duty cycle is set to 0.5, and the sweep frequency is 100 kHz; the simulation results are shown in Table 1, wherein GKS1_1, GKS1_2, GKS1_3 represent the gate-Kelvin electrode current path of the first, second, and third SiC MOSFET chips (for Figure 1 , corresponding to the three second chips 4) on the left side, respectively (for Figure 1 , the second gate pin 11-second chip 4-gate of the second chip 4-second Kelvin pin 12 path); GKS2_1, GKS2_2, GKS2_3 represent the gate-Kelvin electrode current path of the first, second, and third SiC MOSFET chips (for Figure 1 , corresponding to the three first chips 3) on the right side, respectively (for Figure 1 , the first gate pin 7-first chip 3-gate of the first chip 3-first Kelvin pin 8 path); DS1_1, DS1_2, DS1_3 represent the source-drain current path of the first, second, and third SiC MOSFET chips (for Figure 1DS1_1, DS1_2, DS1_3 represent the source-drain current paths of the first, second, third SiC MOSFET chip from left to right (for the first chip 3, the second chip 4, and the third chip 5, respectively) in the first structure; DS2_1, DS2_2, DS2_3 represent the source-drain current paths of the first, second, third SiC MOSFET chip from right to left (for the third chip 5, the second chip 4, and the first chip 3, respectively) in the second structure. Figure 1 , and the improvement of the parasitic inductance difference of the structure of Figure 4 , the downward arrow represents a decrease, and the upward arrow represents an increase. Figure 5 , the downward arrow represents a decrease, and the upward arrow represents an increase.

[0087] Table 1

[0088]

[0089] From the above table, it can be seen that the circuit component layout of the present application significantly reduces the inductance difference between the current paths of adjacent SiC MOSFET chips relative to the traditional circuit component layout. This makes the current distribution consistent when multiple SiC MOSFET chips are operated in parallel, fundamentally reducing the risk of uneven current and oscillation in parallel structures. Especially in high-frequency and high-current applications, this consistency plays a crucial role in improving system efficiency and reliability.

[0090] The heat dissipation of the power module packaging structure of the present application and the traditional power module packaging structure (the difference between the two is only in the circuit component layout, and the specific structure of the traditional power module packaging structure is shown in Figures 6-8 ) was simulated when working. In the simulation model, the two power module packaging structures were placed on the same heat sink, and the simulation conditions included: a wind speed of 0.5 m / s was applied at the same position in the air domain of both, simulating real environment heat dissipation and applying a square wave current of 62A current, a duty cycle of 0.5 and a sweep frequency of 100 kHz at the source-drain input end, and a square wave current of 0.25A, a duty cycle of 0.5 and a sweep frequency of 100 kHz at the gate and Kelvin input end, simulating half-bridge module switching control. The simulation results of the traditional power module packaging structure are shown in Figures 9-11 , and the simulation results of the power module packaging structure of the present application are shown in Figure 6 ; wherein, Figure 9 shows the overall temperature distribution of the traditional power module packaging structure; Figure 7 shows the overall temperature distribution of the power module packaging structure of the present application; Figure 8 shows the temperature distribution of the SiC MOSFET chip of the traditional power module packaging structure, Figure 10 shows the temperature distribution of the corresponding copper electrode; Figure 11A temperature distribution diagram of a SiC MOSFET chip of the power module packaging structure of the application is shown, ​ A temperature distribution diagram of a corresponding copper electrode is shown. From the simulation results, the highest case temperature of the conventional power module packaging structure is 89.9 DEG C (the case temperature refers to the surface temperature of the electronic component packaging shell), the highest junction temperature is 94.5 DEG C (the junction temperature refers to the temperature of the PN junction inside the semiconductor chip), the highest case temperature of the power module packaging structure of the application is 88 DEG C, and the highest junction temperature is 92.9 DEG C. Under the same conditions, the design of the utility model makes the case temperature decrease by 1.9 DEG C, and the junction temperature decrease by 1.6 DEG C.

[0091] The above only describes the embodiments of the application and is not used to limit the protection scope of the application. For those skilled in the art, the application can have various changes and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A circuit assembly comprising a DBC substrate (1) and a plurality of SiC MOSFET chips arranged on the DBC substrate (1), which SiC MOSFET chips form a parallel half-bridge circuit by means of bonding wires (2) and copper electrodes arranged on the surface of the DBC substrate (1) and pins arranged on the DBC substrate (1), characterized in that, The plurality of SiC MOSFET chips comprises a plurality of first chips (3) connected in parallel and a plurality of second chips (4) connected in parallel; The drain of each first chip (3) is attached to a first drain copper electrode (6) provided with a first drain pin (5), and each first chip (3) is staggered in the lateral and longitudinal directions to form a stepped arrangement structure; the staggered distance of any two adjacent first chips (3) in the lateral and longitudinal directions is the same, the gate of each first chip (3) is connected to a same first gate pin (7) through a longitudinally extending connecting piece and a laterally extending connecting piece in turn, so that the path length of the gate of each first chip (3) to the first gate pin (7) is equal, and the Kelvin pole of each first chip (3) is connected to a same first Kelvin pin (8) through a longitudinally extending connecting piece and a laterally extending connecting piece in turn, so that the path length of the Kelvin pole of each first chip (3) to the first Kelvin pin (8) is equal; The drain of each second chip (4) is attached to a second drain copper electrode (10) provided with a second drain pin (9), and each second chip (4) is staggered in the lateral and longitudinal directions to form a stepped arrangement structure; the staggered distance of any two adjacent second chips (4) in the lateral and longitudinal directions is the same, the gate of each second chip (4) is connected to a same second gate pin (11) through a longitudinally extending connecting piece and a laterally extending connecting piece in turn, so that the path length of the gate of each second chip (4) to the second gate pin (11) is equal, and the Kelvin pole of each second chip (4) is connected to a same second Kelvin pin (12) through a longitudinally extending connecting piece and a laterally extending connecting piece in turn, so that the path length of the Kelvin pole of each second chip (4) to the second Kelvin pin (12) is equal; The longitudinal direction and the lateral direction are two perpendicular directions on the upper surface of the DBC substrate (1).

2. The circuit assembly of claim 1, wherein, The parallel half-bridge circuit comprises a plurality of first chips (3), a plurality of second chips (4), a source pin (13), the first Kelvin pin (8), the first gate pin (7), the first drain pin (5), the second Kelvin pin (12), the second gate pin (11), and the second drain pin (9). The source and the Kelvin pole of all the first chips (3) are connected to the source pin (13); the drain of all the first chips (3) and the source and the Kelvin pole of all the second chips (4) are connected to the first drain pin (5); and the drain of all the second chips (4) is connected to the second drain pin (9).

3. The circuit assembly of claim 2, wherein, The first chip (3) is arranged on the DBC substrate (1) in the same direction, and the transversely extending connecting member connected with the first chip (3) comprises a first gate copper electrode (14) and a first Kelvin copper electrode (15) arranged on the DBC substrate (1) and extending in the transverse direction, one end of the first gate copper electrode (14) is connected with the first gate pin (7), and one end of the first Kelvin copper electrode (15) is connected with the first Kelvin pin (8); the gate of each first chip (3) is connected with the first gate copper electrode (14) through a longitudinally extending connecting member; and the Kelvin electrode of each first chip (3) is connected with the first Kelvin copper electrode (15) through a longitudinally extending connecting member.

4. The circuit assembly of claim 3, wherein, The connecting member between the Kelvin electrode of at least one first chip (3) and the first Kelvin copper electrode (15) comprises a bonding wire (2) and a transition copper electrode (16) which are connected with each other to form a spanning bonding structure.

5. The circuit assembly of claim 2, wherein, The second chip (4) is arranged on the DBC substrate (1) in the same direction, and the transversely extending connecting member connected with the second chip (4) comprises a second gate copper electrode (17) and a second Kelvin copper electrode (18) arranged on the DBC substrate (1) and extending in the transverse direction, one end of the second gate copper electrode (17) is connected with the second gate pin (11), and one end of the second Kelvin copper electrode (18) is connected with the second Kelvin pin (12); the gate of each second chip (4) is connected with the second gate copper electrode (17) through a longitudinally extending connecting member; and the Kelvin electrode of each second chip (4) is connected with the second Kelvin copper electrode (18) through a longitudinally extending connecting member.

6. The circuit assembly of claim 5, wherein, The connecting member between the Kelvin electrode of at least one second chip (4) and the second Kelvin copper electrode (18) comprises a bonding wire (2) and a transition copper electrode (16) which are connected with each other to form a spanning bonding structure.

7. The circuit assembly of claim 3, wherein, The first gate copper electrode (14) and the first Kelvin copper electrode (15) are arranged on the same side of the longitudinal direction of the first drain copper electrode (6), the other side of the longitudinal direction of the first drain copper electrode (6) is further provided with a first source copper electrode (19), the source pin (13) is arranged on the first source copper electrode (19), and the source and the Kelvin electrode of all the first chips (3) are connected with the first source copper electrode (19) through the bonding wire (2).

8. The circuit assembly of claim 5, wherein, The second gate copper electrode (17) and the second Kelvin copper electrode (18) are arranged on the same side of the longitudinal direction of the second drain copper electrode (10), the other side of the longitudinal direction of the second drain copper electrode (10) is further provided with a second source copper electrode (20), the source and the Kelvin electrode of all the second chips (4) are connected with the second source copper electrode (20) through the bonding wire (2), and the second source copper electrode (20) is connected with the first drain copper electrode (6) through a copper clamp (21).

9. The circuit assembly of claim 1, wherein, The first gate pin (7) and the first Kelvin pin (8) are arranged at one end in the lateral direction of the DBC substrate (1), and the second gate pin (11) and the second Kelvin pin (12) are arranged at the other end in the lateral direction of the DBC substrate (1); the first drain pin (5) is arranged at one end of the first drain copper electrode (6) away from the second drain copper electrode (10), and the second drain pin (9) is arranged at one end of the second drain copper electrode (10) away from the first drain copper electrode (6).

10. A power module package structure, characterized by, The circuit assembly (101) as claimed in any one of claims 1-9 is arranged on the upper side of the metal base plate (100), and a plastic package shell (102) is arranged on the metal base plate (100) and the circuit assembly (101), and the space between the plastic package shell (102) and the circuit assembly (101) is filled with an organic silicone-based gel (103).

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