Circuit for suppressing starting current in segmented manner

Abstract

The utility model relates to the technical field of circuits, in particular to a circuit for suppressing starting current in a segmented manner, which comprises a plurality of circuit units P1, P2, P3,..., Pn, and the plurality of circuit units P1, P2, P3,..., Pn are respectively composed of loads C1,..., Cn, field effect transistors VM1,..., VMn, delay charging resistors R1,..., Rn, delay capacitors Cd1,..., Cdn, grid signal detection resistors Rp11,..., Rpn1, and grid signal detection resistors Rp12,..., Rpn2. According to the utility model, optimization is carried out based on a method of an MOSFET switch tube and a time-delay network circuit (i.e., an MOSFET suppression circuit), the purposes of controllable surge suppression, reliable MOSFET and no influence on the starting of a load circuit are realized aiming at a direct current power supply occasion, and the contradiction that multiple loads are mixed together and cannot be considered at the same time is avoided.

Description

TECHNICAL FIELD

[0001] The utility model relates to a circuit technical field especially relates to a subsection inhibiting starting current's circuit. BACKGROUND

[0002] In the power supply circuit, the switch (refers to the device of controlling the circuit on-off) closes the circuit and produces the inrush current. But in some important application occasions, such as the weapon equipment, high-end instrument and meter, etc. The overlarge inrush current is not allowed to appear, even the amplitude and the rising slope of the inrush current have the requirement, therefore, the traditional inrush current suppression circuit has the following several common methods.

[0003] 1, series negative temperature coefficient thermistor (NTC): the NTC thermistor reduces the resistance value when the switch power supply starts, which can effectively limit the inrush current during starting. After starting, the resistance value of the NTC thermistor is reduced, which reduces the influence on the normal work of the power supply. This method is simple and practical, and the cost is low, but the current limiting effect is greatly affected by the environmental temperature, and the power bearing capacity is limited and cannot be used in the occasion of the excessive input current.

[0004] 2, using power resistance: a power resistance is connected in series in the circuit to limit the inrush current. This method is simple and easy to operate, but it will increase the power consumption of the circuit, and is only suitable for small power occasions.

[0005] 3, using resistance during starting and removing the resistance after starting: a resistance is connected in series during the starting of the power supply, and the resistance is removed immediately after the starting is completed. This method can effectively limit the inrush current. But the devices connected in parallel with the resistance also need to be able to bear the maximum working current in the circuit, and the additional control circuit also needs to be timed, triggered and other functions. Once the control circuit fails, the risk of burning the current limiting resistance is faced.

[0006] 4, using series fixed resistance and thyristor: a fixed resistance and a thyristor are connected in series at the input end, and the inrush current is limited by the triggering characteristics of the thyristor. This method is suitable for occasions that need to accurately control the inrush current, but the heat of the resistance in the circuit and the control of the thyristor are the problems that need to be considered.

[0007] 5, using MOSFET switch tube and delay network circuit: the starting process of the power supply is controlled by the MOSFET switch tube and the delay network circuit, and the current is gradually increased to suppress the inrush current. This method is efficient, but during the starting process, if the MOSFET is in the linear working area, the load current is large, which may cause two problems: a) MOSFET burnout; b) due to the limited power supply capacity, the load starting process restarts.

[0008] 6. PTC (Positive Temperature Coefficient) thermistor: PTC thermistor increases in resistance when temperature rises, which can effectively limit the inrush current. This method is not suitable for application in the occasion where there is a large current in the line.

[0009] 7. Active suppression method: active switch with soft start circuit is used to limit the inrush current. For example, a special inrush suppression circuit module is used to limit the inrush current during start-up. This method does not affect the system efficiency, but requires external circuit and has high overall cost.

[0010] Therefore, we propose a circuit for segmenting and suppressing start-up current. Invention content

[0011] In view of the shortcomings of the prior art, the present application provides a circuit for segmenting and suppressing start-up current to solve the technical problems in the prior art.

[0012] To achieve the above purpose, the present application is realized by the following technical solutions:

[0013] A circuit for segmenting and suppressing start-up current, comprising a plurality of circuit units P1, P2, P3,..., Pn, wherein each of the plurality of circuit units P1, P2, P3,..., Pn is composed of a load C1,..., Cn, a field effect transistor VM1,..., VMn, a delay charging resistor R1,..., Rn, a delay capacitor Cd1,..., Cdn, a gate signal detection resistor Rp11,..., Rpn1 and Rp12,..., Rpn2, a signal comparator N1,..., Nn, and a conduction switch VT1,..., VTn.

[0014] In the circuit unit P1, one end of the resistor R1 is coupled to the power supply VIN, and the other end is coupled to the source of the field effect transistor VM1 through the delay capacitor Cd1. The drain of the field effect transistor VM1 is coupled to the power supply VIN through the delay capacitor C1. The resistor R1 is coupled to the base of the conduction switch VT1 through the signal detection resistors Rp11, Rp12 and the signal comparator N1.

[0015] In the circuit unit P2, one end of the resistor R2 is coupled to the power supply VIN, and the other end is coupled to the delay capacitor Cd2 through the conduction switch VT1. The delay capacitor Cd2 is coupled to the source of the field effect transistor VM2. The gate of the field effect transistor VM2 is coupled to the base of the conduction switch VT2 through the gate signal detection resistors Rp21, Rp22 and the signal comparator N2.

[0016] In the circuit unit Pn, one end of the resistor Rn is coupled to the power supply VIN, and the other end is coupled to the delay capacitor Cdn through the on-off switch VTN-1, the delay capacitor Cdn is coupled at the source of the field effect tube VMn, and the gate of the field effect tube VMn is coupled to the base of the on-off switch VTN-1 through the gate signal detection resistor Rpn1, Rpn2, and the signal comparator Nn.

[0017] As a preferred technical scheme of the utility model, the sources of the field effect tubes VM1... VMn are all grounded.

[0018] As a preferred technical scheme of the utility model, the gate of the field effect tube VMn is coupled to the collector of the triode VTN-1.

[0019] As a preferred technical scheme of the utility model, the emitter of the triode VTN-1 is coupled to the resistor Rn.

[0020] As a preferred technical scheme of the utility model, the signal comparator Nn is coupled between the gate signal detection resistors Rpn1, Rpn2.

[0021] The utility model provides a kind of segmented suppression starting current circuit, with following beneficial effects:

[0022] The present application is optimized based on the method of MOSFET switch tube and delay network circuit (i.e. MOSFET suppression circuit), which realizes controllable surge suppression for DC power supply occasions, MOSFET reliable, does not affect the purpose of load circuit starting, avoids the contradiction that multiple loads are mixed together and cannot be considered. BRIEF DESCRIPTION OF DRAWINGS

[0023] Fig. 1 It is the schematic diagram of the utility model;

[0024] Fig. 2 It is the circuit diagram of the utility model. DETAILED DESCRIPTION

[0025] In order to make the technical problems, technical schemes and beneficial effects to be solved by the utility model more clear and obvious, the utility model is further described in detail below in combination with drawings and examples. It should be understood that the specific examples described herein are only used to explain the utility model, and are not used to limit the utility model.

[0026] Thus, one feature described in the specification is used to illustrate one feature of an embodiment of the application, and not every embodiment of the application necessarily includes that particular feature. Also, it is noted that the specification describes many embodiments of the application. Although each of these particular embodiments describes particular combinations of features, other combinations of features are also possible. Thus, the described combinations are not intended to limit the application. Rather, the scope of the application includes all alternatives, combinations, and permutations of features described or incorporated by reference herein.

[0027] The principles and structure of the present application will be described in detail below with reference to the accompanying drawings and embodiments:

[0028] Reference Figs. 1-2 A circuit for segmenting the starting current, comprising a plurality of circuit units P1, P2, P3,..., Pn, each of the plurality of circuit units P1, P2, P3,..., Pn is composed of a load C1,..., Cn, a field effect transistor VM1,..., VMn, a delay charging resistor R1,..., Rn, a delay capacitor Cd1,..., Cdn, a gate signal detection resistor Rp11,..., Rpn1 and Rp12,..., Rpn2, a signal comparator N1,..., Nn, and a conduction switch VT1,..., VTn.

[0029] In the circuit unit P1, one end of the resistor R1 is coupled to the power supply VIN, and the other end is coupled to the source of the field effect transistor VM1 through the delay capacitor Cd1, the drain of the field effect transistor VM1 is coupled to the power supply VIN through the delay capacitor C1, and the resistor R1 is coupled to the base of the conduction switch VT1 through the signal detection resistors Rp11, Rp12, and the signal comparator N1.

[0030] In the circuit unit P2, one end of the resistor R2 is coupled to the power supply VIN, and the other end is coupled to the delay capacitor Cd2 through the conduction switch VT1, the delay capacitor Cd2 is coupled to the source of the field effect transistor VM2, and the gate of the field effect transistor VM2 is coupled to the base of the conduction switch VT2 through the gate signal detection resistors Rp21, Rp22, and the signal comparator N2.

[0031] In the circuit unit Pn, one end of the resistor Rn is coupled to the power supply VIN, and the other end is coupled to the delay capacitor Cdn through the conduction switch VTN-1, the delay capacitor Cdn is coupled to the source of the field effect transistor VMn, and the gate of the field effect transistor VMn is coupled to the base of the conduction switch VTN-1 through the gate signal detection resistors Rpn1, Rpn2, and the signal comparator Nn.

[0032] The source of the field effect tube VM1...VMn is grounded, the gate of the field effect tube VMn is coupled with the collector of the triode VTN-1, the emitter of the triode VTN-1 is coupled with the resistor Rn, and the signal comparator Nn is coupled between the gate signal detection resistors Rpn1 and Rpn2.

[0033] Specifically, after the power supply VIN is added, VIN charges Cd1 through R1, and the level at VGS1 increases at a predetermined slope during the charging, when the voltage at VGS1 reaches the minimum starting requirement of VM1, VM1 presents a state of changing resistance, assuming that the resistance is Rds. With the increase of VGS1, the resistance Rds decreases until VM1 is fully open, and the resistance reaches the minimum value, which is generally in the order of milliohm, and the surge circuit is fully opened.

[0034] The mechanism of suppressing the surge current is that the current in the circuit is limited by Ohm's law, which is equal to VIN divided by Rds. If R1 increases or Cd1 increases, the voltage slope of VGS1 increases, the time to reach the full opening of VM1 becomes longer, and the limitation of the surge current in the circuit is better. Of course, the disadvantage is that if the circuit suddenly needs to be increased, VM1 cannot provide this current, resulting in the restart of the line, so the design of this circuit needs to optimize the selection of the values of R1 and Cd1 to ensure that the load can be started smoothly.

[0035] Rp11 and Rp12 detect the level of VGS1 at all times, when the level reaches a predetermined value, N1 gives a signal to make VT1 conductive, and the second stage surge circuit starts. Repeat the above process until all loads are working.

[0036] The above only describes the specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A circuit for segmenting the suppression of start-up current comprising a plurality of circuit units P1, P2, P3,... Pn, characterized in that, The plurality of circuit units P1, P2, P3,..., Pn are respectively composed of a load C1,..., Cn, a field effect transistor VM1,..., VMn, a delay charging resistor R1,..., Rn, a delay capacitor Cd1,..., Cdn, a gate signal detection resistor Rp11,..., Rpn1 and Rp12,..., Rpn2, a signal comparator N1,..., Nn, and a conduction switch VT1,..., VTn. In the circuit unit P1, one end of the resistor R1 is coupled to the power supply VIN, and the other end is coupled to the source of the field effect transistor VM1 through the delay capacitor Cd1. The drain of the field effect transistor VM1 is coupled to the power supply VIN through the delay capacitor C1. The resistor R1 is coupled to the base of the conduction switch VT1 through the signal detection resistors Rp11 and Rp12 and the signal comparator N1. In the circuit unit P2, one end of the resistor R2 is coupled to the power supply VIN, and the other end is coupled to the delay capacitor Cd2 through the conduction switch VT1. The delay capacitor Cd2 is coupled to the source of the field effect transistor VM2. The gate of the field effect transistor VM2 is coupled to the base of the conduction switch VT2 through the gate signal detection resistors Rp21 and Rp22 and the signal comparator N2. In the circuit unit Pn, one end of the resistor Rn is coupled to the power supply VIN, and the other end is coupled to the delay capacitor Cdn through the conduction switch VTN-1. The delay capacitor Cdn is coupled to the source of the field effect transistor VMn. The gate of the field effect transistor VMn is coupled to the base of the conduction switch VTN-1 through the gate signal detection resistors Rpn1 and Rpn2 and the signal comparator Nn.

2. A circuit for segmenting the suppression of starting current as defined in claim 1, characterized in that, The sources of the field effect transistors VM1,..., VMn are all grounded.

3. A circuit for segmenting the suppression of starting current as defined in claim 1, wherein, The gate of the field effect transistor VMn is coupled to the collector of the transistor VTN-1.

4. A circuit for segmenting the suppression of starting current as defined in claim 1, wherein, The emitter of the transistor VTN-1 is coupled to the resistor Rn.

5. A circuit for segmenting the suppression of starting current as defined in claim 1, wherein, The signal comparator Nn is coupled between the gate signal detection resistors Rpn1 and Rpn2.

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