Display backboard

Abstract

The utility model discloses a display backboard, which comprises a driving substrate, a plurality of light-emitting structures arranged in an array are bonded on the surface of the driving substrate, each light-emitting structure comprises a first electrode and a sub epitaxial layer which are sequentially stacked on the driving substrate from bottom to top, the sub epitaxial layer is electrically connected with the first electrode, and the sub epitaxial layer is of a step structure; passivation layers cover the side wall of the light-emitting structure and the surface of the driving substrate around the light-emitting structure; the edge area of the table top of the sub epitaxial layer and the surface of the passivation layer are both covered with an ohmic contact metal layer, so that the ohmic contact metal layer is electrically connected with the sub epitaxial layer, and a via hole for exposing the middle area of the table top of the sub epitaxial layer is formed in the ohmic contact metal layer; and a common electrode covers the middle area of the table top of the sub epitaxial layer and the ohmic contact metal layer, so that the common electrode is electrically connected with the sub epitaxial layer. According to the display backboard, the problems that the chip is low in light-emitting brightness and large in light-emitting angle are solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technical field especially relates to a display backplate. BACKGROUND

[0002] At present, the low brightness of Micro LED micro display chip is the main problem of each company, for example, the red light Micro LED micro display chip has the problem of low brightness, and the market mainstream AR glasses usually adopt light waveguide technology, the brightness loss of this kind of technology is large, and the luminous brightness entering the human eye is less than 10%; meanwhile, the N-type ohmic contact metal in the traditional red light chip process is made at the center position of the chip, which seriously affects the light emission of the chip surface, and the chip can only rely on the edge light emission or the side wall light emission, which will cause the light emission angle of the chip to be too large and the display effect to be poor. SUMMARY

[0003] In view of the above-mentioned problems in the prior art, the purpose of the utility model is to provide a display backplate to solve the problems of low chip light emission brightness and large light emission angle.

[0004] The utility model provides a kind of display backplate, including drive substrate, the surface of the drive substrate is bonded with multiple arrayed light emitting structure, the light emitting structure includes first electrode and sub-epitaxial layer sequentially stacked on the drive substrate from bottom to top, the sub-epitaxial layer is electrically connected with the first electrode, and the sub-epitaxial layer is stepped structure;

[0005] The surface of the sidewall of the light emitting structure and the drive substrate around it is covered with passivation layer;The edge region of the mesa of the sub-epitaxial layer and the surface of the passivation layer are covered with ohmic contact metal layer, so that the ohmic contact metal layer is electrically connected with the sub-epitaxial layer and the via hole is formed on the ohmic contact metal layer, which exposes the central region of the mesa of the sub-epitaxial layer;Common electrode is covered on the central region of the mesa of the sub-epitaxial layer and the ohmic contact metal layer, so that the common electrode is electrically connected with the sub-epitaxial layer.

[0006] Optionally, the sub-epitaxial layer includes first semiconductor layer, quantum well layer and second semiconductor layer sequentially stacked from bottom to top, the mesa of the sub-epitaxial layer is the surface of the second semiconductor layer, the sub-epitaxial layer is electrically connected with the first electrode, i.e. the first semiconductor layer is electrically connected with the first electrode, and the common electrode is electrically connected with the sub-epitaxial layer, i.e. the common electrode is electrically connected with the second semiconductor layer.

[0007] Optionally, the via hole is a circular hole.

[0008] Optionally, the common electrode is a common indium tin oxide electrode layer.

[0009] Optionally, the first electrode is a first indium tin oxide electrode layer.

[0010] Optionally, the first semiconductor layer is a P-type semiconductor layer, the first electrode is a P electrode, the common electrode is an N-type semiconductor layer, and the common electrode is a common N electrode; or, the first semiconductor layer is an N-type semiconductor layer, the first electrode is an N electrode, the common electrode is a P-type semiconductor layer, and the common electrode is a common P electrode.

[0011] Optionally, the driving substrate is a CMOS driving substrate.

[0012] Optionally, the first electrode and the driving substrate are bonded by a bonding metal.

[0013] Optionally, the passivation layer comprises at least one of an aluminum oxide passivation layer, a silicon oxide passivation layer, and a silicon nitride passivation layer.

[0014] Optionally, the sub-epitaxial layer is a sub-red light epitaxial layer.

[0015] Optionally, the light emitting structure is a MicroLED or a MiniLED.

[0016] The display backboard of the utility model solves the problems of low chip luminance and large light emitting angle, and improves the light emitting uniformity of the entire two-dimensional array chip by covering the ohmic contact metal layer in the groove around the light emitting structure. The via is made at the edge of the mesa, and the light emitting center of the mesa is not shielded, the light emitting angle is small, and a microlens does not need to be made; meanwhile, the ohmic contact metal layer of the mesa sidewall reflects the light directed to the sidewall, which is beneficial to reducing the absorption of the light by the quantum well layer, and meanwhile, the light beam convergence degree is increased, and the brightness of each chip is improved; the ITO has poor transverse conductivity, while the metal thin film has the best transverse and longitudinal conductivity, each pixel point is connected through the ohmic contact metal layer, the current passing through each pixel point is kept consistent, and the light emitting uniformity is improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A schematic view of an epitaxial wafer bonded to a driving substrate is provided for the utility model embodiment;

[0018] Figure 2 A schematic view after a mesa process of an epitaxial wafer is provided for the utility model embodiment;

[0019] Figure 3 A schematic view after deposition and etching of a passivation layer is provided for the utility model embodiment;

[0020] Figure 4 A schematic view after deposition and etching of an ohmic contact metal layer is provided for the utility model embodiment;

[0021] Figure 5The top view of the display backboard is provided for the embodiment of the utility model.

[0022] Figure 6 The schematic diagram of depositing the common electrode is provided for the embodiment of the utility model.

[0023] Mark explanation: 1-drive substrate; 2-first electrode; 3-sub-epitaxial layer; 31-taiping; 4-passivation layer; 5-ohmic contact metal layer; 51-via; 6-common electrode; 7-bonding metal. DETAILED DESCRIPTION

[0024] In order to facilitate the understanding of the utility model, the utility model will be described more fully below with reference to the relevant drawings. The preferred embodiments of the utility model are shown in the drawings. However, the utility model can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the utility model more thorough and comprehensive.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the utility model belongs. The terms used in the specification of the utility model herein are only for the purpose of describing specific embodiments and are not intended to limit the utility model.

[0026] In the description of the utility model, the terms "first", "second", etc. are used to distinguish different objects, not to describe a specific order, in addition, the terms "up", "down", "in", "out" indicate the orientation or position relationship shown in the drawings, only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, therefore, it cannot be understood as a limitation on the utility model.

[0027] It should be noted that the diagrams provided in the embodiments of the utility model only illustrate the basic concept of the utility model in a schematic manner, and only show the components related to the utility model in the diagrams, not the number, shape and size of the components when actually implemented. The type, number and proportion of each component in actual implementation can be changed at will, and the component layout form may be more complex.

[0028] The specific embodiments of the utility model will be further described below with reference to the drawings.

[0029] Reference Figure 6The utility model discloses a display backboard, including drive substrate 1, the surface bonding of drive substrate 1 has multiple array arrangement's light emitting structure, the light emitting structure includes first electrode 2 and sub epitaxial layer 3 from below to above and stack in drive substrate 1 on, sub epitaxial layer 3 with first electrode 2 electricity is connected, and sub epitaxial layer 3 is the step structure,

[0030] The sidewall of the light emitting structure and the surface of the drive substrate 1 around the light emitting structure are covered with a passivation layer 4; the edge region of the mesa 31 of the sub epitaxial layer 3 and the surface of the passivation layer 4 are covered with an ohmic contact metal layer 5, so that the ohmic contact metal layer 5 is connected with the sub epitaxial layer 3 and a via hole 51 is formed on the ohmic contact metal layer 5 to expose the middle region of the mesa 31 of the sub epitaxial layer 3; and a common electrode 6 is covered on the middle region of the mesa 31 of the sub epitaxial layer 3 and the ohmic contact metal layer 5, so that the common electrode 6 is electrically connected with the sub epitaxial layer 3.

[0031] The display backboard of the utility model solves the problems of low light emitting brightness and large light emitting angle of the chip, and the ohmic contact metal layer 5 is covered on the groove around the light emitting structure, so that the light emitting uniformity of the entire two-dimensional array chip can be improved. The via hole 51 is made in the edge region of the mesa 31, the center region of the mesa 31 is not shielded for light emission, the light emitting angle is small, and a microlens does not need to be made; meanwhile, the ohmic contact metal layer 5 of the sidewall of the mesa 31 reflects the light emitted to the sidewall, which is beneficial to reducing the light absorption of the quantum well layer and increasing the light beam convergence degree, and the brightness of each chip is improved. The groove around the light emitting structure includes the sidewall of the light emitting structure and the surface of the drive substrate 1 around the light emitting structure.

[0032] In the embodiment, the sub epitaxial layer 3 includes a first semiconductor layer, a quantum well layer and a second semiconductor layer which are stacked in sequence from bottom to top, the mesa 31 of the sub epitaxial layer 3 is the surface of the second semiconductor layer, the sub epitaxial layer 3 is electrically connected with the first electrode 2, that is, the first semiconductor layer is electrically connected with the first electrode 2, and the common electrode 6 is electrically connected with the sub epitaxial layer 3, that is, the common electrode 6 is electrically connected with the second semiconductor layer.

[0033] In the embodiment, the first electrode 2 and the drive substrate 1 are bonded by a bonding metal 7.

[0034] In the embodiment, the via hole 51 is a circular hole. In some embodiments, the via hole 51 is an elliptical hole or a square hole or other shapes, which are not limited here.

[0035] In the embodiment, the ohmic contact metal layer 5 can include at least one of an Au ohmic contact layer, an Ni ohmic contact layer, a Ge ohmic contact layer, and a Pd ohmic contact layer. The ohmic contact metal layer 5 on the sidewall of the mesa 31 reflects light incident on the sidewall, which is advantageous to reduce the absorption of light by the quantum well layer, while the light beam convergence degree is increased, and the brightness of each chip is improved.

[0036] In some embodiments, the material of the common electrode 6 and the first electrode 2 both includes one of indium tin oxide and a multi-layer metal film, for example, Ti / Al / Ni / Au, and in other embodiments, the multi-layer metal film can also be other kinds of materials.

[0037] In the embodiment, the common electrode 6 is a common indium tin oxide (ITO) electrode layer. ITO has poor lateral conduction capability, while the lateral and longitudinal conductivity of the metal film is best, and the ohmic contact metal layer 5 is connected to each pixel point, so that the current passing through each pixel point is consistent, and the light emission uniformity is improved.

[0038] In the embodiment, the first electrode 2 is a first indium tin oxide electrode layer.

[0039] In the embodiment, the first semiconductor layer is a P-type semiconductor layer, the first electrode 2 is a P electrode, the common electrode 6 is an N-type semiconductor layer, and the common electrode 6 is a common N electrode.

[0040] Alternatively, the first semiconductor layer is an N-type semiconductor layer, the first electrode 2 is an N electrode, the common electrode 6 is a P-type semiconductor layer, and the common electrode 6 is a common P electrode.

[0041] In the embodiment, the driving substrate 1 can be a circuit board, an array substrate, a glass driving substrate, a flexible driving substrate, a lamp board, a semiconductor driving substrate, or other kinds of driving substrates, which are not specifically limited in the embodiment; the material of the driving substrate 1 can be glass, transparent plastic, acrylic, quartz, sapphire, semiconductor material, etc., which can be selected according to actual conditions and is not specifically limited in the embodiment. Optionally, the driving substrate 1 is a CMOS driving substrate.

[0042] In the embodiment, the passivation layer 4 includes at least one of an aluminum oxide passivation layer, a silicon oxide passivation layer, and a silicon nitride passivation layer.

[0043] In some embodiments, the sub-epitaxial layer 3 includes at least one of a sub-red light epitaxial layer, a sub-green light epitaxial layer, and a sub-blue light epitaxial layer.

[0044] In this embodiment, the sub-epipolar layer 3 is a sub-red light epipolar layer. By adopting the technical solution of this utility model, the problems of low brightness and large emission angle of the red light chip are solved. Optionally, the light-emitting structure can be MicroLED, MiniLED, nano-scale LED, or LED of other sizes. It is not limited here, and can be selected according to the actual situation.

[0045] In this embodiment, the display back panel can be either a direct display or a backlit display, and no limitation is made here.

[0046] As one implementation method, the display back panel can be a TV, VR / AR device, smart wearable device, mobile phone, vehicle display, etc.

[0047] See Figures 1 to 6 The diagram shown is a process flow chart for fabricating the display backplane. The process steps are as follows: Figure 2 First, the epitaxial wafer and the driving substrate 1 are metal-bonded. After bonding, the epitaxial substrate is peeled off. Then, the mesa fabrication process of the epitaxial wafer and the bonding metal etching process are performed to form multiple light-emitting structures. The sub-epiaxial layer 3 is obtained through the mesa fabrication process of the epitaxial wafer; for example... Figure 3 Next, a passivation layer 4 is deposited on the surface and sidewalls of the light-emitting structure. The passivation layer 4 is etched to create an opening in the mesa 31 of the light-emitting structure, and a current injection window is etched out. The mesa 31 of the light-emitting structure is the mesa 31 of the sub-epitaxial layer 3. Figure 4 As shown, an ohmic contact metal layer 5 is fabricated and covers the edge area of ​​the mesa 31 of the light-emitting structure to form a via 51. At the same time, the sidewalls and surrounding trenches of the light-emitting structure are filled with the ohmic contact metal layer 5. Finally, a common electrode 6 is deposited and connected to the driving substrate 1 to realize chip conduction. The driving substrate 1 can drive each light-emitting structure to emit light and display independently.

[0048] It should be understood that the application of this utility model is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A display backplane, characterized by, The driving substrate is surface-bonded with a plurality of light-emitting structures arranged in an array, the light-emitting structure comprises a first electrode and a sub-epitaxial layer stacked in order from bottom to top on the driving substrate, the sub-epitaxial layer is electrically connected with the first electrode, and the sub-epitaxial layer is a stepped structure. The sidewall of the light-emitting structure and the surface of the driving substrate around the sidewall are covered with a passivation layer; the edge region of the mesa of the sub-epitaxial layer and the surface of the passivation layer are covered with an ohmic contact metal layer, so that the ohmic contact metal layer is electrically connected with the sub-epitaxial layer, and a via hole is formed on the ohmic contact metal layer to expose a middle region of the mesa of the sub-epitaxial layer; and a common electrode is covered on the middle region of the mesa of the sub-epitaxial layer and the ohmic contact metal layer, so that the common electrode is electrically connected with the sub-epitaxial layer.

2. The display backplane of claim 1, wherein, The sub-epitaxial layer comprises a first semiconductor layer, a quantum well layer and a second semiconductor layer stacked in order from bottom to top, the mesa of the sub-epitaxial layer is the surface of the second semiconductor layer, the sub-epitaxial layer is electrically connected with the first electrode, i.e. the first semiconductor layer is electrically connected with the first electrode, and the common electrode is electrically connected with the sub-epitaxial layer, i.e. the common electrode is electrically connected with the second semiconductor layer.

3. The display backplane of claim 2, wherein, The first semiconductor layer is a P-type semiconductor layer, the first electrode is a P electrode, the common electrode is an N-type semiconductor layer, and the common electrode is a common N electrode. Or, the first semiconductor layer is an N-type semiconductor layer, the first electrode is an N electrode, the common electrode is a P-type semiconductor layer, and the common electrode is a common P electrode.

4. The display backplane of claim 1 or 2 or 3, wherein, The common electrode is a common indium tin oxide electrode layer.

5. The display backplane of claim 4, wherein, The first electrode is a first indium tin oxide electrode layer.

6. The display backplane of claim 1 or 2 or 3 or 5, wherein, The via hole is a circular hole.

7. The display backplane of claim 1, wherein, The first electrode and the driving substrate are bonded by a bonding metal.

8. The display backplane of claim 7, wherein, The passivation layer comprises at least one of an aluminum oxide passivation layer, a silicon oxide passivation layer and a silicon nitride passivation layer.

9. The display backplane of claim 1 or 2 or 3 or 5 or 7 or 8, wherein, The sub-epitaxial layer is a sub-red light epitaxial layer.

10. The display backplane of claim 1 or 2 or 3 or 5 or 7 or 8, wherein, The light-emitting structure is a MicroLED or a MiniLED.

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