Dielectric layer structure for high-voltage terminal

Abstract

The utility model discloses a dielectric layer structure for a high-voltage terminal, which comprises a Si substrate layer, an oxide layer, a polycrystalline layer, a USG isolation layer, a first metal layer, a first SRO layer, a SiO2 layer and a second metal layer which are sequentially stacked, and the second SRO layer and the PSG layer which are connected with each other are arranged between the first metal layer and the USG isolation layer. According to the dielectric layer structure for the high-voltage terminal, provided by the utility model, the first SRO layer and the second SRO layer are additionally arranged, so that the reliability design requirement can be met while chip tape-out is realized, and the SRO can tolerate thermal expansion and thermal shock in a high-temperature environment and is not easy to deform and crack; and meanwhile, the SRO is very high in electrical insulation performance and dielectric constant and excellent in insulation performance, the electromagnetic interference capability of the high-voltage power device can be improved to a great extent, the wafer stress is relieved, the problem of film cracking is solved, the reliability of a product is improved, and the performance quality advantage of the dielectric layer is obvious.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a dielectric layer structure for high-voltage terminals. Background Technology

[0002] Currently, existing high-voltage power devices require a PSG or SiO2 dielectric layer of 2µm or more to electrically isolate the metal from silicon and interconnect metal layers, and physically isolate impurity sources such as mobile ions, thereby preventing the degradation of the electrical characteristics of high-voltage power devices.

[0003] However, existing high-voltage power devices use PSG or SiO2 dielectric layers larger than 2µm to be fabricated via PECVD. During the fabrication process, cracking and pinholes are prone to occur. During the packaging and wire bonding process, film cracking is also very likely to occur, which cannot meet product requirements and makes it even more difficult to achieve the requirements of high-voltage reliability.

[0004] In view of this, it is necessary to propose further improvements to the current structure. Utility Model Content

[0005] Therefore, the purpose of this utility model is to at least partially address the shortcomings of the prior art, thereby proposing a dielectric layer structure for high-voltage terminals.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] This invention provides a dielectric layer structure for high-voltage terminals, comprising a Si substrate layer, an oxide layer, a polycrystalline layer, a USG isolation layer, a first metal layer, a first SRO layer, a SiO2 layer, and a second metal layer stacked sequentially. The first metal layer and the USG isolation layer are further provided with a second SRO layer and the PSG layer interconnected.

[0008] Furthermore, the thicknesses of the first SRO layer and the second SRO layer are...

[0009] Furthermore, a portion of the first metal layer is connected to the USG isolation layer, and a second SRO layer and the PSG layer are disposed between the other portion and the USG isolation layer. One end of the second SRO layer and the PSG layer are respectively connected to the first metal layer, and one side of the PSG layer is connected to the first metal layer, and the other side is connected to the second SRO layer. The side of the second SRO layer away from the PSG layer is connected to the USG isolation layer.

[0010] Furthermore, a groove is formed in the USG isolation layer, and the polycrystalline layer is disposed in the groove, with one end of the polycrystalline layer connected to the oxide layer.

[0011] Furthermore, a first contact hole window is formed on the USG isolation layer and the oxide layer, and the first metal layer passes through the first contact hole window to connect with the Si substrate layer.

[0012] Furthermore, a second contact hole window is provided on the USG isolation layer, and the first metal layer passes through the second contact hole window to connect with the polycrystalline layer.

[0013] Furthermore, a through-hole window is formed on the SiO2 layer and the first SRO layer, and the second metal layer passes through the through-hole window and connects to the first metal layer.

[0014] Furthermore, the thickness of the SiO2 layer and the PSG layer is 2μm-3μm.

[0015] Furthermore, the first metal layer and the second metal layer are made of adhesive conductive metal.

[0016] This invention provides a dielectric layer structure for high-voltage terminals, comprising a Si substrate layer, an oxide layer, a polycrystalline layer, a USG isolation layer, a first metal layer, a first SRO layer, a SiO2 layer, and a second metal layer stacked sequentially. A second SRO layer and the USG isolation layer are interconnected between the first metal layer and the second SRO layer. By adding the first and second SRO layers, this high-voltage terminal dielectric layer structure can meet reliability design requirements while enabling chip fabrication. SRO can withstand thermal expansion and thermal shock in high-temperature environments, and is not prone to deformation or cracking. Simultaneously, SRO has very high electrical insulation properties and dielectric constant, possessing excellent insulation performance, which can significantly improve the electromagnetic interference capability of high-voltage power devices, alleviate wafer stress, solve film cracking problems, and improve product reliability. Furthermore, the performance and quality advantages of the dielectric layer are significant. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a cross-sectional view of the dielectric layer structure for a high-voltage terminal in an embodiment of this application.

[0019] The reference numerals in the figure are as follows: 1. Si substrate layer; 2. Oxide layer; 3. Polycrystalline layer; 4. USG isolation layer; 5. First metal layer; 6. First SRO layer; 7. SiO2 layer; 8. Second metal layer; 9. Second SRO layer; 10. PSG layer; 11. First contact hole window; 12. Second contact hole window; 13. Through hole window. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] It should be noted that the descriptions involving "first," "second," etc., in this utility model are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0022] Please refer to Figure 1 This utility model provides a dielectric layer structure for high voltage terminals, including a Si substrate layer 1, an oxide layer 2, a polycrystalline layer 3, a USG isolation layer 4, a first metal layer 5, a first SRO layer 6, an SiO2 layer 7, and a second metal layer 8 stacked sequentially. A second SRO layer 9 and a PSG layer 10 are also disposed between the first metal layer 5 and the USG isolation layer 4 and are interconnected.

[0023] Existing high-voltage power devices require a PSG or SiO2 dielectric layer of 2µm or more to electrically isolate the metal from silicon and interconnect metal layers, and physically to isolate mobile ions and other impurity sources, thus preventing the degradation of the electrical characteristics of the high-voltage power devices. However, the existing PSG or SiO2 dielectric layers of 2µm or more in high-voltage power devices are prepared by PECVD, which is prone to cracking and pinholes during the fabrication process. Furthermore, film cracking is also highly likely during wire bonding and packaging, failing to meet product requirements and making it difficult to achieve the high-voltage reliability requirements.

[0024] Therefore, this embodiment provides a dielectric layer structure for high-voltage terminals. By adding a first SRO layer 6 and a second SRO layer 9, it is possible to achieve chip fabrication while simultaneously meeting reliability design requirements. SRO can withstand thermal expansion and thermal shock in high-temperature environments and is not prone to deformation or cracking. Simultaneously, SRO has very high electrical insulation properties and dielectric constant, possessing excellent insulation performance, which can significantly improve the electromagnetic interference capability of high-voltage power devices, thereby compensating for the film cracking phenomenon in traditional processes. The SRO is silicon-rich silicon dioxide, and the first SRO layer 6 and the second SRO layer 9 serve the same function, with both layers having the same thickness.

[0025] Specifically, the Si substrate layer 1 provides the necessary physical support in the dielectric layer structure for high-voltage terminals and is the foundation of the device structure. It withstands various mechanical stresses during the manufacturing and use of the device. In other words, the Si substrate layer 1 not only provides physical support, but also helps to optimize electrical performance, reduce leakage current, support advanced process nodes, improve breakdown voltage, and is compatible with existing CMOS technology.

[0026] The USG (Un-doped Silicate Glass) isolation layer 4 serves as a dielectric material to form an electrical isolation layer between the high-voltage power device and the first metal layer 5. It effectively isolates the metal interconnects from the device, reduces the parasitic capacitance between the first metal layer 5 and the Si substrate layer 1, and also has multiple functions such as preventing contamination, high-temperature stability, insulation performance, chemical stability, and surface planarization.

[0027] The USG isolation layer 4 has a groove, within which the polycrystalline layer 3 is disposed. One end of the polycrystalline layer 3 is connected to the oxide layer 2. The polycrystalline layer 3 acts as a field plate, optimizing the electric field distribution, increasing the breakdown voltage, and improving device performance.

[0028] The first metal layer 5 and the second metal layer 8 are used to transmit electrical signals and connect the various dielectric layers together to ensure the normal operation of the circuit.

[0029] SiO2 layer 7 is the dielectric material in the dielectric layer structure of this high-voltage terminal, providing electrical isolation, preventing current leakage between different dielectric layers, and ensuring the stability and safety of the device.

[0030] The oxide layer 2 has the same function as the SiO2 layer 7, and its specific material is also SiO2.

[0031] In this high-voltage terminal dielectric layer structure, the PSG layer 10 provides electrical isolation, buffering and leveling, absorption of alkaline ions, and surface protection.

[0032] The thickness of the SiO2 layer 7 and the PSG layer 10 is 2μm-3μm, and the specific thickness of the SiO2 layer and the PSG layer 10 in this embodiment is 2μm.

[0033] The second SRO layer 9 is deposited on the USG isolation layer 4 by plasma-enhanced CVD and prepared using silane (SiH4) and N2O in a plasma environment. The preparation process was carried out by adjusting the total RF power (0.5W–1.5W), pressure (1.6 Torr–2.8 Torr), N2 flow rate (1 slm–4 slm), and N2O flow rate (0.5 slm–6.0 slm). The second SRO layer 9 is then prepared, followed by a 2µm PSG layer 10.

[0034] By adjusting the total RF power to 0.5W–1.5W, the pressure to 1.6 Torr–2.8 Torr, the N2 flow rate to 1 slm–4 slm, and the N2O flow rate to 0.5 slm–6.0 slm, the following preparations were first made. First SRO layer 6, then prepare 2um SiO2 layer 7.

[0035] Furthermore, a portion of the first metal layer 5 is connected to the USG isolation layer 4, and the other portion is provided with the second SRO layer 9 and the PSG layer 10 between it and the USG isolation layer 4. One end of the second SRO layer 9 and the PSG layer 10 are respectively connected to the first metal layer 5, and one side of the PSG layer 10 is connected to the first metal layer 5, and the other side is connected to the second SRO layer 9. The side of the second SRO layer 9 away from the PSG layer 10 is connected to the USG isolation layer 4.

[0036] Furthermore, a first contact window 11 is formed on the USG isolation layer 4 and the oxide layer 2, and the first metal layer 5 passes through the first contact window 11 to connect with the Si substrate layer 1. A second contact window 12 is also formed on the USG isolation layer 4, and the first metal layer 5 passes through the second contact window 12 to connect with the polycrystalline layer 3. A through-hole window 13 is also formed on the SiO2 layer 7 and the second SRO layer 9, and the second metal layer 8 passes through the through-hole window 13 to connect with the first metal layer 5.

[0037] In this embodiment, the high-voltage terminal dielectric layer structure is provided with a first contact hole window 11, a second contact hole window 12, and a through hole window 13 as connection channels between the first metal layer 5 and the second metal layer 8, which can realize electrical connection and play an important role in connecting the two metal layers.

[0038] Specifically, the first metal layer 5 can be connected to the Si substrate layer 1 through the first contact hole window 11 and the second contact hole window 12, while the second metal layer 8 can be connected to the first metal layer 5 through the through hole window 13, ensuring the correct flow of current.

[0039] The first contact hole window 11, the second contact hole window 12, and the through hole window 13 are formed by etching. The first metal layer 5 is also filled in the first contact hole window 11 and the second contact hole window 12, thereby connecting with the Si substrate layer 1. The second metal layer 8 is filled in the through hole window 13 disposed in the first SRO layer 6 and the SiO2 layer 7, thereby connecting with the first metal layer 5. The shapes of the first metal layer 5 and the second metal layer 8 are also formed by photolithography and etching.

[0040] Furthermore, the first metal layer 5 and the second metal layer 8 are made of an adhesive conductive metal, specifically Al or Si.

[0041] This invention provides a dielectric layer structure for high-voltage terminals, comprising a Si substrate layer, an oxide layer, a polycrystalline layer, a USG isolation layer, a first metal layer, a first SRO layer, a SiO2 layer, and a second metal layer stacked sequentially. A second SRO layer and the USG isolation layer are interconnected between the first metal layer and the second SRO layer. By adding the second and first SRO layers, this high-voltage terminal dielectric layer structure achieves chip fabrication while meeting reliability design requirements. SRO can withstand thermal expansion and thermal shock in high-temperature environments, and is less prone to deformation and cracking. Simultaneously, SRO has very high electrical insulation properties and dielectric constant, possessing excellent insulation performance, which can significantly improve the electromagnetic interference capability of high-voltage power devices, alleviate wafer stress, solve film cracking problems, and improve product reliability. Furthermore, the dielectric layer exhibits significant performance and quality advantages.

[0042] It should be noted that the various embodiments in this utility model are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0043] It should also be noted that, in the present invention, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in the present invention may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dielectric layer structure for high-voltage terminals, characterized in that, It includes a Si substrate layer, an oxide layer, a polycrystalline layer, a USG isolation layer, a first metal layer, a first SRO layer, a SiO2 layer, and a second metal layer stacked in sequence. A second SRO layer and a PSG layer are also disposed between the first metal layer and the USG isolation layer and are interconnected.

2. The dielectric layer structure for high-voltage terminals according to claim 1, characterized in that, The thicknesses of the first SRO layer and the second SRO layer are:

3. The dielectric layer structure for high-voltage terminals according to claim 1, characterized in that, A portion of the first metal layer is connected to the USG isolation layer, and a second SRO layer and the PSG layer are disposed between the other portion and the USG isolation layer. One end of the second SRO layer and the PSG layer are respectively connected to the first metal layer, and one side of the PSG layer is connected to the first metal layer, and the other side is connected to the second SRO layer. The side of the second SRO layer away from the PSG layer is connected to the USG isolation layer.

4. The dielectric layer structure for high-voltage terminals according to claim 1, characterized in that, A groove is formed in the USG isolation layer, and the polycrystalline layer is disposed in the groove. One end of the polycrystalline layer is connected to the oxide layer.

5. The dielectric layer structure for high-voltage terminals according to claim 4, characterized in that, A first contact hole window is formed on the USG isolation layer and the oxide layer, and the first metal layer passes through the first contact hole window to connect with the Si substrate layer.

6. The dielectric layer structure for high-voltage terminals according to claim 5, characterized in that, The USG isolation layer also has a second contact hole window, through which the first metal layer passes and connects to the polycrystalline layer.

7. The dielectric layer structure for high-voltage terminals according to claim 1, characterized in that, A through-hole window is also formed on the SiO2 layer and the first SRO layer, and the second metal layer passes through the through-hole window and is connected to the first metal layer.

8. The dielectric layer structure for high-voltage terminals according to claim 1, characterized in that, The thickness of the SiO2 layer and the PSG layer is 2μm-3μm.

9. The dielectric layer structure for high-voltage terminals according to claim 1, characterized in that, The first metal layer and the second metal layer are made of adhesive conductive metal.

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