Multi-chip packaging structure and electronic equipment

Abstract

The utility model relates to the technical field of electronic packaging, in particular to a multi-chip packaging structure and electronic equipment, and aims to reduce the size of the multi-chip packaging structure. The multi-chip packaging structure comprises a first chip, a second chip, a third chip and a plurality of conductive columns. The second chip is located on one side of the first chip and is bound with the first chip. And a groove is formed in one side, far away from the first chip, of the second chip. The groove is recessed along a direction from the second chip to the first chip. At least one part of the third chip is located in the groove. Each conductive column penetrates through the second chip from the bottom wall of the groove. The third chip is electrically connected with the first chip through the plurality of conductive columns. The multi-chip packaging structure is used for chip packaging.

Description

Technical Field

[0001] This disclosure relates to the field of electronic packaging technology, and in particular to a multi-chip packaging structure and electronic device. Background Technology

[0002] With the development of electronic technology, the functions of electronic devices are becoming increasingly diverse and comprehensive, leading to a growing demand for the evolution and iteration of high-end chips. Chip integration is continuously increasing, and multi-chip integration and packaging are becoming trends. As the number of vertically stacked chips increases, the size of multi-chip package structures is becoming larger, which may result in a lower limit on the thickness of electronic devices or cause localized protrusions in the electronic devices. Utility Model Content

[0003] The embodiments of this disclosure provide a multi-chip package structure and an electronic device, which aim to reduce the size of the multi-chip package structure, alleviate the problem of local area protrusion in the electronic device, and thereby realize the miniaturization design of the electronic device.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] Some embodiments of this disclosure provide a multi-chip package structure, which includes a first chip, a second chip, a third chip, and a plurality of conductive posts. The second chip is located on one side of the first chip and is bonded to the first chip. A groove is provided on the side of the second chip away from the first chip. The groove is recessed along the direction from the second chip to the first chip. At least a portion of the third chip is located within the groove. Each conductive post penetrates the second chip from the bottom wall of the groove. The third chip is electrically connected to the first chip through the plurality of conductive posts.

[0006] The multi-chip package structure provided in the embodiments of this disclosure, by setting a second chip to one side of the first chip, having a groove on the side of the second chip away from the first chip, and having at least a portion of the third chip located within the groove, with the groove recessed along the direction from the second chip to the first chip, results in a smaller overall size in the chip thickness direction occupied by the third chip and the second chip, thus reducing the size of the resulting multi-chip package structure and alleviating the problem of protruding local areas in electronic devices. Furthermore, multiple conductive pillars are provided to penetrate the second chip from the bottom wall of the groove, enabling connection between the first and third chips. This simplifies the connection method between the first and third chips, reduces the connection spacing, avoids the connection of the first and third chips occupying additional space, further reducing the size of the multi-chip package structure and facilitating the miniaturization design of electronic devices.

[0007] In some embodiments, the angle between the bottom wall of the groove and the side wall of the groove is greater than or equal to 90°.

[0008] In some embodiments, the number of the third chips is multiple; the number of the grooves is multiple, and at least one third chip is disposed in one groove.

[0009] In some embodiments, a third chip is disposed in a groove, and the orthographic projection shape of the groove onto the first chip is the same as the orthographic projection shape of the third chip onto the first chip.

[0010] In some embodiments, a plurality of third chips are disposed in a groove, and the orthographic projection shape of the groove onto the first chip is the same as the outer boundary shape formed by the orthographic projections of the plurality of third chips onto the first chip.

[0011] In some embodiments, the distance between the surface of the third chip away from the first chip and the first chip is greater than or equal to the distance between the surface of the second chip away from the first chip and the first chip.

[0012] In some embodiments, the multi-chip package structure further includes a package portion; the package portion is located between the third chip and the sidewall of the recess.

[0013] In some embodiments, the third chip includes a wiring layer located on the surface of the third chip away from the first chip.

[0014] In some embodiments, the first chip includes a pixel chip; the second chip includes a logic chip; and the third chip includes an application-specific integrated circuit (ASIC).

[0015] Some embodiments of this disclosure also provide an electronic device, including a circuit board and a multi-chip package structure as described in the above embodiments; the circuit board is connected to the multi-chip package structure.

[0016] The beneficial effects that the electronic devices provided by some embodiments of this disclosure can achieve are the same as the beneficial effects that the multi-chip packaging structures provided in some of the above embodiments can achieve, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be considered as schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of this disclosure.

[0018] Figure 1This is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0019] Figure 2 This is a structural diagram of a multi-chip package structure according to some embodiments of the present disclosure;

[0020] Figure 3 This is a structural diagram of another multi-chip package structure according to some embodiments of this disclosure;

[0021] Figure 4 This is a structural diagram of yet another multi-chip packaging structure according to some embodiments of the present disclosure;

[0022] Figure 5 This is a structural diagram of yet another multi-chip packaging structure according to some embodiments of the present disclosure;

[0023] Figure 6 This is a structural diagram of another multi-chip package structure according to some embodiments of the present disclosure. Detailed Implementation

[0024] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0025] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0026] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0027] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0028] As used herein, “approximately” includes the values ​​stated and the average value within an acceptable range of deviation from the given values, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0029] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0030] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0031] This disclosure provides an electronic device. This electronic device can be a camera, mobile phone, tablet computer, desktop computer, laptop computer, handheld computer, laptop computer, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, smart wearable device (e.g., smartwatch), in-vehicle device, smart home device, and / or smart city device, etc., that requires image acquisition or storage computation. This disclosure does not impose any special limitations on the specific type of this electronic device.

[0032] like Figure 1 As shown, the above-mentioned electronic device 1000 includes a multi-chip package structure 100 and a circuit board 200.

[0033] For example, the multi-chip package structure 100 is connected to the circuit board 200 and receives control signals provided by the circuit board 200, enabling the electronic device 1000 to perform display, storage and other functions.

[0034] In one implementation, multiple chips are stacked sequentially along their thickness direction and then packaged to form a multi-chip package structure. This multi-chip package structure has a large dimension in the thickness direction, resulting in a large overall size and occupying a significant amount of space in electronic devices, which is detrimental to the miniaturization design of electronic devices.

[0035] Based on this, embodiments of this disclosure provide a multi-chip packaging structure 100, such as... Figure 2 As shown, it includes: multiple chips and multiple conductive pillars 40. The multiple chips include a first chip 10, a second chip 20, and a third chip 30.

[0036] The second chip 20 is located on one side of the first chip 10, for example, on one side of the first chip 10 along its thickness direction. The second chip 20 is bonded to the first chip 10 to achieve electrical connection between the two chips, facilitating signal transmission between them.

[0037] A groove 21 is provided on the side of the second chip 20 away from the first chip 10. The groove 21 is recessed along the direction from the second chip 20 to the first chip 10. The groove 21 has a certain depth in the thickness direction of the second chip 20. For example, if the thickness direction of the chip and the thickness direction of the second chip 20 are both in the third direction Z, the depth of the groove 21 is less than the thickness of the second chip 20 (see reference). Figure 2 ).

[0038] At least a portion of the third chip 30 is located within the recess 21. For example, as... Figure 2 As shown, the third chip 30 is located within the groove 21, and the third chip 30 does not protrude from the second chip 20. For example, as... Figure 3 As shown, a portion of the third chip 30 is located within the groove 21, and along the direction from the first chip 10 to the third chip 30, a portion of the third chip 30 protrudes relative to the second chip 20. Therefore, the overall dimension of the third chip 30 and the second chip 20 in the chip thickness direction is smaller than the sum of the thicknesses of the third chip 30 and the second chip 20. The overall dimension of the first chip 10, the second chip 20, and the third chip 30 in the chip thickness direction is also smaller than the sum of the thicknesses of the first chip 10, the second chip 20, and the third chip 30, resulting in a smaller overall dimension of the multi-chip package structure 100 in the chip thickness direction.

[0039] The aforementioned plurality of conductive posts 40 penetrate the second chip 20 from the bottom wall of the groove 21 to the surface of the second chip 20 near the first chip 10. One end of the conductive post 40 is electrically connected to the first chip 10, and the other end is electrically connected to the third chip 30. The third chip 30 is electrically connected to the first chip 10 through the plurality of conductive posts 40, thereby facilitating signal transmission between the third chip 30 and the first chip 10. In addition, the second chip 20 can also be connected to the first chip 10 through the conductive posts 40 to realize signal transmission between the second chip 20 and the first chip 10.

[0040] For example, the second chip 20 has multiple through-silicon vias (TSVs), and conductive material fills the TSVs to form the aforementioned conductive pillars 40. The conductive material can be a metal or the like.

[0041] The connection between the first chip 10 and the third chip 30 is achieved by using conductive posts 40, which can make the spacing between the first chip 10 and the third chip 30 smaller, avoid the connection between the first chip 10 and the third chip 30 occupying a large space, and help reduce the size of the multi-chip package structure 100 in the chip thickness direction.

[0042] The multi-chip package structure 100 provided in the embodiments of this disclosure, by setting the second chip 20 to one side of the first chip 10, and providing a groove 21 on the side of the second chip 20 away from the first chip 10, with at least a portion of the third chip 30 located within the groove 21, and the groove 21 being recessed along the direction from the second chip 20 to the first chip 10, makes the overall size of the third chip 30 and the second chip 20 smaller in the chip thickness direction, resulting in a smaller size of the multi-chip package structure 100 and alleviating the problem of protruding local areas in electronic devices. Furthermore, multiple conductive posts 40 are provided to penetrate the second chip 20 from the bottom wall of the groove 21, realizing the connection between the first chip 10 and the third chip 30. This simplifies the connection method between the first chip 10 and the third chip 30, and the connection spacing is small, avoiding the connection of the first chip and the third chip occupying additional space, further reducing the size of the multi-chip package structure 100, which is beneficial for achieving miniaturized design of electronic devices.

[0043] In some embodiments, such as Figure 4 As shown, there are multiple third chips 30. There are multiple grooves 21, and at least one third chip 30 is disposed in each groove 21.

[0044] For example, multiple grooves 21 are configured one-to-one with multiple third chips 30, and one third chip 30 is disposed in one groove 21. In this way, the size of a single groove 21 can be relatively small, avoiding affecting the internal structure of the second chip 20, and also reducing the damage of the groove 21 to the rigidity of the second chip 20, ensuring that the second chip 20 has sufficient mechanical strength.

[0045] For example, a groove 21 contains multiple third chips 30, which are arranged at intervals.

[0046] For example, the depths of the multiple recesses 21 may not be equal. For instance, the depth of the recess 21 may be adapted to the thickness of the corresponding third chip 30. If the thickness of the third chip 30 is greater, the depth of the recess 21 can be set to be greater. If the thickness of the third chip 30 is smaller, the depth of the recess 21 can be set to be smaller. This results in a smaller protrusion of the third chip 30 relative to the second chip 20, and consequently, a smaller overall size for the multi-chip package structure 100 and the electronic device 1000.

[0047] The aforementioned multi-chip package structure 100 can be a system-on-a-chip (SoC) or a system on a chip.

[0048] The first chip 10, the second chip 20, and the third chip 30 mentioned above can be chips of the same type or chips of different types. The types of chips in the multi-chip package structure can be set according to the specific application scenarios of the electronic device.

[0049] In some examples, in the multi-chip package structure 100 described above, the first chip 10 includes a pixel wafer, the second chip 20 includes a logic wafer, and the third chip 30 includes an application-specific integrated circuit (ASIC).

[0050] For example, logic chips and multiple application-specific integrated circuits can be integrated on the pixel chip to form functional modules in electronic devices. This makes the electronic devices smaller in the thickness direction, alleviates the problem of protruding functional modules in electronic devices, and helps to achieve a thinner and lighter design of electronic devices.

[0051] For example, the aforementioned electronic device can be a mobile phone. The third chip 30 may include a camera chip. A logic chip and multiple camera chips can be integrated on the pixel chip to form a camera module in the mobile phone, which alleviates the problem of the camera module protruding in the mobile phone, and helps to reduce the size of the mobile phone, thus realizing the design of a thinner and smaller mobile phone.

[0052] For example, the third chip 30 may include a microlens chip.

[0053] The structure of the third chip 30 can be varied and can be configured according to actual needs. The embodiments disclosed herein do not limit this.

[0054] In some examples, such as Figure 2 As shown, the third chip 30 includes a wiring layer 31, which is located on the surface of the third chip 30 away from the first chip 10.

[0055] The wiring layer 31 includes multiple wires. These wires are used to enable the interaction between the third chip 30 and other chips, such as the first chip 10.

[0056] This reduces the space occupied by the third chip 30, which helps to reduce the size of the multi-chip package structure 100. Furthermore, it avoids the need to place wires on the surface of the third chip 30 away from the first chip 10 for connection, reducing the packaging process difficulty of the third chip 30 and shortening the packaging time.

[0057] In some embodiments, the plane containing the bottom wall of the groove 21 is parallel or substantially parallel to the plane containing the first chip 10.

[0058] For example, such as Figure 2 As shown, the included angle α between the bottom wall of groove 21 and the side wall of groove 21 is greater than or equal to 90°.

[0059] For example, the included angle α between the bottom wall of the groove 21 and the side wall of the groove 21 can be 90°, 120°, 150° or 160°.

[0060] For example, the angle α between the bottom wall of the groove 21 and the side wall of the groove 21 is 90°, and the cross-sectional shape of the groove 21 is rectangular or square.

[0061] For example, the angle α between the bottom wall and the side wall of the groove 21 is 120°, and the cross-sectional shape of the groove 21 is an inverted trapezoid, with the upper base of the inverted trapezoid being larger than the lower base.

[0062] By adopting the above-mentioned arrangement, the opening of the groove 21 is relatively large, which makes it easier to place at least a portion of the third chip 30 in the groove 21, thereby reducing the fabrication difficulty of the multi-chip package structure 100.

[0063] For example, the size of the groove 21 in the first direction X is larger than the size of the third chip 30 in the first direction X.

[0064] For example, the dimension of the groove 21 in the second direction Y is greater than the dimension of the third chip 30 in the second direction Y.

[0065] This facilitates the placement of at least a portion of the third chip 30 within the groove 21, preventing damage such as scratches from affecting its functionality and thereby improving the yield and reliability of the multi-chip package structure.

[0066] In some embodiments, such as Figure 2 and Figure 3 As shown, the distance L1 between the surface of the third chip 30 away from the first chip 10 and the first chip 10 is greater than or equal to the distance L2 between the surface of the second chip 20 away from the first chip 10 and the first chip 10.

[0067] Therefore, the surface of the third chip 30 can be flush with the surface of the second chip 20 on the side away from the first chip 10, or the size of the third chip 30 protruding from the surface of the second chip 20 on the side away from the first chip 10 can be small, reducing the probability of the third chip 30 being damaged by scratches, avoiding damage to the function of the third chip 30, which is conducive to improving the yield and stability of electronic devices and alleviating the problem of local protrusion in electronic devices.

[0068] In some embodiments, such as Figure 2 and Figure 4 As shown, the multi-chip package structure 100 further includes a package portion 50. The package portion 50 is located between the third chip 30 and the sidewall of the recess 21.

[0069] Therefore, the third chip 30 can be fixed in the groove 21 by using the packaging part 50, which helps to improve the structural stability of the multi-chip packaging structure 100.

[0070] For example, the material of the encapsulation part 50 may include an adhesive, or the material of the encapsulation part 50 may include a polymer.

[0071] For example, the surface of the package portion 50 away from the bottom wall of the recess 21 is approximately flush with the surface of the second chip 20 away from the bottom wall of the recess 21. This allows for a relatively flat surface to be achieved in the multi-chip package structure 100.

[0072] The relationship between the orthographic projection of the aforementioned groove 21 on the second chip and the orthographic projection of the third chip 30 on the second chip can be set according to actual needs. The embodiments disclosed herein do not specify the shape.

[0073] For example, such as Figure 4 As shown, the orthographic projection of the third chip 30 onto the second chip is located within the orthographic projection range of the groove 21 onto the second chip.

[0074] In some embodiments, a third chip 30 is disposed in a groove 21, and the orthographic projection shape of the groove 21 on the first chip 10 is different from the orthographic projection shape of the third chip 30 on the first chip 10.

[0075] For example, the orthographic projection shape of the groove 21 on the first chip 10 can be a quadrilateral, and the orthographic projection shape of the third chip 30 on the first chip 10 can be a circle.

[0076] For example, the orthographic projection shape of the groove 21 on the first chip 10 can be a circle, and the orthographic projection shape of the third chip 30 on the first chip 10 can be a quadrilateral.

[0077] In other embodiments, such as Figure 5 As shown, a third chip 30 is disposed in a groove 21. The orthographic projection shape of the groove 21 on the first chip 10 is the same as the orthographic projection shape of the third chip 30 on the first chip 10.

[0078] For example, the orthographic projection shape of the groove 21 on the first chip 10 can be a quadrilateral, and the orthographic projection shape of the third chip 30 on the first chip 10 can also be a quadrilateral.

[0079] This allows for a more uniform spacing between the outer contour of the third chip 30 and the sidewall of the recess 21, resulting in a more uniform package around the third chip 30 and thus improving the structural stability of the multi-chip package structure 100. It also allows for a relatively small area of ​​the orthographic projection of a single recess 21 onto the first chip, reducing the impact of the recess 21 on other structures in the second chip 20 and preventing any disruption to the functionality of the second chip 20.

[0080] In some examples, the center of the orthographic projection of the third chip 30 onto the first chip 10 coincides with or substantially coincides with the center of the orthographic projection of the groove 21 onto the first chip 10.

[0081] In some other embodiments, such as Figure 6 As shown, a plurality of third chips 30 are disposed in a groove 21. The orthographic projection shape of the groove 21 on the first chip 10 is the same as the outer boundary shape formed by the orthographic projection of the plurality of third chips 30 on the first chip 10.

[0082] For example, the orthographic projection of the groove 21 onto the first chip 10 is a quadrilateral, and the outer boundary shape formed by the orthographic projections of the multiple third chips 30 onto the first chip 10 is also a quadrilateral.

[0083] This allows for a more uniform spacing between the outer contours of the multiple third chips 30 and the sidewalls of the grooves 21, resulting in a more uniform packaging portion 50 around the multiple third chips 30, thereby improving the structural stability of the multi-chip packaging structure 100. It also reduces the number of grooves 21, which helps shorten the groove fabrication time and the fabrication cycle of the multi-chip packaging structure 100.

[0084] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A multi-chip packaging structure, characterized in that, include: First chip; The second chip is located on one side of the first chip and is bound to the first chip; The second chip has a groove on the side away from the first chip; the groove is recessed along the direction from the second chip to the first chip; The third chip, at least a portion of which is located within the groove; Multiple conductive pillars penetrate the second chip from the bottom wall of the groove, and the third chip is electrically connected to the first chip through the multiple conductive pillars.

2. The multi-chip packaging structure according to claim 1, characterized in that, The angle between the bottom wall of the groove and the side wall of the groove is greater than or equal to 90°.

3. The multi-chip packaging structure according to claim 1, characterized in that, The number of the third chips is multiple; the number of the grooves is multiple, and at least one of the third chips is disposed in each groove.

4. The multi-chip packaging structure according to claim 3, characterized in that, A third chip is disposed in a groove, and the orthographic projection shape of the groove onto the first chip is the same as the orthographic projection shape of the third chip onto the first chip.

5. The multi-chip packaging structure according to claim 3, characterized in that, A plurality of the third chips are disposed in a groove, and the orthographic projection shape of the groove onto the first chip is the same as the outer boundary shape formed by the orthographic projections of the plurality of third chips onto the first chip.

6. The multi-chip packaging structure according to claim 1, characterized in that, The distance between the surface of the third chip away from the first chip and the first chip is greater than or equal to the distance between the surface of the second chip away from the first chip and the first chip.

7. The multi-chip packaging structure according to claim 1, characterized in that, The multi-chip packaging structure further includes: a packaging section; The packaging portion is located between the third chip and the sidewall of the groove.

8. The multi-chip packaging structure according to claim 1, characterized in that, The third chip includes a wiring layer located on the surface of the third chip away from the first chip.

9. The multi-chip packaging structure according to any one of claims 1 to 8, characterized in that, The first chip includes a pixel chip; the second chip includes a logic chip; and the third chip includes an application-specific integrated circuit (ASIC).

10. An electronic device, characterized in that, include: Circuit board, and multi-chip package structure as described in any one of claims 1 to 9; The circuit board is connected to the multi-chip package structure.

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