Electronic package and substrate structure thereof
By reducing the area of the metal sheet covering the die-placement region in the substrate structure of the semiconductor package, the problem of electrical connection failure caused by warpage is solved, and higher electrical connection reliability and production yield are achieved.
Patent Information
- Application Number
- CN202423101715.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-12-09
- Filing Date
- 2024-12-16
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2034-12-16
AI Technical Summary
In existing semiconductor packages, the metal sheet on the packaging substrate warps, causing the solder bumps to separate from the substrate, resulting in electrical connection failure and affecting product yield.
The substrate structure is designed so that the metal sheet does not extend into the crystal placement area or an opening is provided at the junction of the crystal placement area and the functional area to reduce the metal area on the substrate surface, disperse stress, and avoid warping.
This effectively prevents conductive bumps from separating from the substrate, improves electrical connection reliability, and increases production yield.
Smart Images
Figure CN223651406U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor packaging technology, and more particularly to an electronic package and its substrate structure that can improve reliability. Background Technology
[0002] With the development of the electronics industry, today's electronic products are trending towards thinner, smaller, and more versatile designs, and semiconductor packaging technology has also developed different packaging forms accordingly. To meet the requirements of high integration and miniaturization of semiconductor devices, in addition to traditional wire bonding semiconductor packaging technology, the industry mainly uses flip chip technology to increase the wiring density of semiconductor devices.
[0003] Please see Figure 1A and Figure 1B This is a cross-sectional schematic diagram and a partial top view of an existing flip-chip semiconductor package 1. Figure 1A As shown, a semiconductor chip 11 is first bonded to an electrical contact pad 104 of a packaging substrate 10 via multiple solder bumps 13, and then the solder bumps 13 are reflowed. Next, an undercoat 14 is formed between the semiconductor chip 11 and the packaging substrate 10 to cover the solder bumps 13.
[0004] Additionally, at least one passive component 15, such as a capacitor, is typically disposed on the packaging substrate 10. This passive component 15 is located on a single metal sheet 100 of the packaging substrate 10 and electrically connected to multiple solder bumps 13 of the semiconductor chip 11 (or similar components) via multiple conductive traces 101 connecting the metal sheet 100. Figure 1B The multiple electrical contact pads 104 shown.
[0005] However, in existing semiconductor packages 1, the metal sheet 100 of the packaging substrate 10 is a large-area metal structure, causing the metal sheet 100 to overlap the vertical projection area P of the semiconductor chip 11. Therefore, the area of metal material distributed on the packaging substrate 10 below the semiconductor chip 11 is excessive. Consequently, during temperature cycling or stress changes, such as during reflow oven tests or drop tests, the packaging substrate 10 is prone to uneven stress distribution due to differences in the coefficient of thermal expansion (CTE) across different surface areas, leading to warpage. This warpage (e.g.) Figure 1AThe chip warping direction F1 and the substrate warping direction F0 shown are opposite, which can easily cause the multiple solder bumps 13 to separate from the packaging substrate 10, or even cause the solder bumps 13 to break, resulting in the failure of the electrical connection between the semiconductor chip 11 and the packaging substrate 10 (such as an open circuit), which in turn leads to product scrap and a drop in product yield.
[0006] Therefore, overcoming the shortcomings of the existing technologies has become an urgent issue to be addressed. Utility Model Content
[0007] In view of the various deficiencies of the prior art, this application provides a substrate structure, including: a substrate body, the surface of which is defined with adjacent placement areas and functional areas; and a wiring layer, including a plurality of conductive traces disposed in the placement areas and a metal sheet disposed in the functional areas and electrically connected to the plurality of conductive traces, wherein the metal sheet does not extend into the placement areas, or the metal sheet has an opening located at the junction of the placement areas and the functional areas.
[0008] In the aforementioned substrate structure, all of the plurality of conductive traces have the same linewidth. Alternatively, at least two of the plurality of conductive traces have different linewidths.
[0009] In the aforementioned substrate structure, the distance between the edge of the crystal placement area and the metal sheet is at least 100 micrometers.
[0010] In the aforementioned substrate structure, the metal sheet having an opening located at the junction of the crystal placement area and the functional area extends into the crystal placement area.
[0011] In the aforementioned substrate structure, the wiring layer also has a plurality of electrical contact pads located within the die-placement region and electrically connected to each of the conductive traces. For example, the opening may or may not correspond to the position of the electrical contact pad.
[0012] In the aforementioned substrate structure, the opening may or may not correspond to the position of the conductive trace.
[0013] This application also provides an electronic package, including: a substrate structure as described above; electronic components disposed on the die-placement area and electrically connected to the plurality of conductive traces; and passive components disposed on the functional area and electrically connected to the metal sheet.
[0014] In the aforementioned electronic package, the distance between the edge of the vertical projection area of the electronic component and the metal sheet is at least 100 micrometers.
[0015] As can be seen from the above, the electronic package and its substrate structure of this application mainly reduce the area of the wiring layer in the die-placement area by means that the metal sheet does not extend into the die-placement area or the metal sheet has at least one opening, thereby reducing the metal area on the surface of the substrate body. Therefore, the electronic package can effectively disperse the stress of the substrate structure and avoid the warping of the substrate structure. Thus, compared with the prior art, this application can avoid the problem of the conductive bumps peeling off, which helps to improve the reliability of the electrical connection between the electronic component and the substrate structure, thereby improving the production yield. Attached Figure Description
[0016] Figure 1A This is a cross-sectional schematic diagram of an existing semiconductor package.
[0017] Figure 1B This is a partial top view of an existing semiconductor package.
[0018] Figure 2A This is a cross-sectional schematic diagram of the electronic package of this application.
[0019] Figure 2B This is a partial top view of the electronic package of this application.
[0020] Figure 3A , Figure 3B and Figure 3C This is a top view schematic diagram of another embodiment of the electronic package of this application.
[0021] Explanation of reference numerals in the attached figures
[0022] 1 Semiconductor package
[0023] 10 Packaging substrate
[0024] 100, 200, 300 metal sheets
[0025] 101, 201, 301 Conductive traces
[0026] 104, 204 electrical contact pads
[0027] 11 Semiconductor chips
[0028] 13 Solder bumps
[0029] 14,24 base rubber
[0030] 15, 25, 85 Passive components
[0031] 2. Substrate Structure
[0032] 2a Wiring Layer
[0033] 20 substrate body
[0034] 202 Dielectric Layer
[0035] 203 Line Layer
[0036] 21 Electronic Components
[0037] 21a Working surface
[0038] 21b Non-operating surface
[0039] 23 Conductive bumps
[0040] 3 Electronic Packages
[0041] 302, 303 openings
[0042] 80 Another metal sheet
[0043] A Crystal Placement Area
[0044] B Function Area
[0045] D, P vertical projection areas
[0046] F0 substrate warping direction
[0047] F1 Chip Warping Direction
[0048] R1, R2 line width
[0049] t represents distance. Detailed Implementation
[0050] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0051] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "below," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0052] Figure 2A This is a cross-sectional schematic diagram of the electronic package 3 of this application, and Figure 2BThis is a partial top view of the substrate structure 2 of this application. Figure 2A and Figure 2B As shown, the substrate structure 2 includes a substrate body 20 and a wiring layer 2a formed on the substrate body 20.
[0053] The substrate body 20 has an adjacent crystal placement region A and a functional region B defined on its surface.
[0054] In this embodiment, the substrate body 20 is a packaged substrate with a core layer or a coreless packaged substrate, which includes a dielectric layer 202 and a circuit layer 203 bonded to the dielectric layer 202 and electrically connected to the wiring layer 2a. For example, the circuit layer 203 and the wiring layer 2a are formed by a redistribution layer (RDL) fabrication method, wherein the material forming the circuit layer 203 and the wiring layer 2a is copper, and the material forming the dielectric layer 202 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0055] The wiring layer 2a includes a plurality of conductive traces 201 and a metal sheet 200 connecting the plurality of conductive traces 201.
[0056] In this embodiment, the metal sheet 200 is located on the functional area B and outside the crystal placement area A, and the conductive trace 201 spans the crystal placement area A and the functional area B.
[0057] Furthermore, the linewidth R1 of each conductive trace 201 is the same. Or, as... Figure 3A As shown, at least two of the multiple conductive traces 201 and 301 have different line widths R1 and R2.
[0058] Furthermore, the wiring layer 2a also has a plurality of electrical contact pads 204 located in the crystal placement area A and electrically connected to each of the conductive traces 201, so that one end of the conductive trace 201 is connected to the metal sheet 200 and the other end is connected to the electrical contact pad 204.
[0059] In addition, the substrate body 20 also has another metal sheet 80 formed on the functional area B, which is spaced apart from the metal sheet 200.
[0060] The electronic package 3 has at least one electronic component 21 disposed on the die placement area A of the substrate body 20, and at least one passive component (in this embodiment, multiple passive components 25, 85 are shown) disposed on the functional area B of the substrate body 20, so that the electronic component 21 is electrically connected to the passive component 25 through the wiring layer 2a.
[0061] The electronic component 21 is an active component such as a semiconductor chip.
[0062] In this embodiment, the electronic component 21 has opposing active surfaces 21a and non-active surfaces 21b, and the active surface 21a has multiple electrode pads. The electronic component 21 is electrically connected to the circuit layer 203 and the multiple electrical contact pads 204 via multiple conductive bumps 23 containing solder material using a flip-chip method, and then the conductive bumps 23 are covered with a primer 24. In other embodiments, the electronic component 21 can also be electrically connected to the circuit layer 203 and the multiple electrical contact pads 204 via multiple bonding wires (not shown); or, the electronic component 21 can directly contact the circuit layer 203 and the multiple electrical contact pads 204. It should be understood that there are many ways to electrically connect the electronic component 21 to the circuit layer 203 and the multiple electrical contact pads 204, and it is not limited to the methods described above.
[0063] Furthermore, the distance t between the edge of the crystal placement area A (or the vertical projection area D of the electronic component 21) and the metal sheet 200 is at least 100 micrometers (µm), such as 120 micrometers.
[0064] The passive components 25 and 85 are, for example, resistors, capacitors or inductors, which are disposed on the metal sheet 200 and the other metal sheet 80 and electrically connected to the metal sheet 200 and the other metal sheet 80.
[0065] Therefore, the electronic package 3 of this application reduces the area of the metal sheet 200 by designing the wiring layer 2a of the substrate structure 2 (e.g., not extending into the die placement area A), thereby reducing the metal area on the surface of the substrate body 20 (especially the amount of copper area corresponding to the electronic component 21 below it). This prevents the metal sheet 200 from overlapping in the vertical projection area D (or the die placement area A) of the electronic component 21. Therefore, compared with the prior art, the electronic package 3 can effectively disperse the stress of the substrate structure 2 when the conductive bump 23 is re-soldered during temperature cycling or stress changes, so as to avoid stress concentration in the wiring layer 2a and thus avoid excessive warping of the substrate structure 2.
[0066] Furthermore, the substrate structure 2 of this application can avoid the problem that the multiple conductive bumps 23 and the substrate structure 2 (or the electronic component 21) will separate due to warping (or even that the conductive bumps 23 will break due to stress concentration). Therefore, the electronic package 3 of this application is beneficial to improving the reliability of the electrical connection between the electronic component 21 and the substrate structure 2, thereby increasing the production yield.
[0067] Furthermore, the method of reducing the area of the metal sheet 200 to reduce the metal area on the surface of the substrate body 20 (especially the amount of copper area corresponding to the area below the electronic component 21) is not limited to the above. Figure 3B As shown, even if the metal sheet 300 spans the crystal placement area A and the functional area B, the area of the metal sheet 200 can still be reduced by forming at least one opening 302, 303 on the metal sheet 300, wherein the opening 302 corresponds to the position of the conductive trace 201 (or the electrical contact pad 204); or, as Figure 3C The opening 303 shown does not correspond to the position of the conductive trace 201 (or the electrical contact pad 204); preferably, the opening 302, 303 is located at the junction of the crystal placement area A and the functional area B (or at the edge of the vertical projection area D of the electronic component 21).
[0068] In summary, the electronic package and its substrate structure of this application reduce the area of the wiring layer in the die-placement area, thereby reducing the metal area on the surface of the substrate body. This allows the electronic package to effectively disperse the stress of the substrate structure and prevent warping of the substrate structure. Therefore, this application can avoid the problem of the conductive bumps peeling off, which helps to improve the reliability of the electrical connection between the electronic component and the substrate structure, and thus improve the production yield.
[0069] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. A substrate structure, characterized in that, include: The substrate body has adjacent crystal placement areas and functional areas defined on its surface; as well as The wiring layer includes a plurality of conductive traces disposed in the crystal placement area and a metal sheet disposed in the functional area and electrically connected to the plurality of conductive traces, wherein the metal sheet does not extend into the crystal placement area, or the metal sheet has an opening located at the junction of the crystal placement area and the functional area.
2. The substrate structure as described in claim 1, characterized in that, All of these conductive traces have the same line width.
3. The substrate structure as described in claim 1, characterized in that, At least two of the multiple conductive traces have different line widths.
4. The substrate structure as described in claim 1, characterized in that, The distance between the edge of the crystal placement area and the metal sheet is at least 100 micrometers.
5. The substrate structure as described in claim 1, characterized in that, The metal sheet, having an opening located at the junction of the crystal placement area and the functional area, extends into the crystal placement area.
6. The substrate structure as described in claim 5, characterized in that, The wiring layer also has multiple electrical contact pads located within the crystal placement area and electrically connected to each of the conductive traces.
7. The substrate structure as described in claim 6, characterized in that, The opening corresponds to the position of the electrical contact pad.
8. The substrate structure as described in claim 6, characterized in that, The opening is not in the correct position for the electrical contact pad.
9. The substrate structure as described in claim 1, characterized in that, The opening corresponds to the location of the conductive trace.
10. The substrate structure as described in claim 1, characterized in that, The opening is not in the correct position for the conductive trace.
11. An electronic package, characterized in that, include: The substrate structure as described in any one of claims 1 to 10; Electronic components are disposed on the crystal placement area and electrically connected to the plurality of conductive traces; as well as A passive component is disposed on the functional area and electrically connected to the metal sheet.
12. The electronic package as claimed in claim 11, characterized in that, The distance between the edge of the vertical projection area of the electronic component and the metal sheet is at least 100 micrometers.