Circuit board
By designing a uniform layout of input and output interfaces on the circuit board and connecting each conductive area through unblocked vias, the heat dissipation problem of high-power components is solved, achieving uniform heat dissipation of the circuit board and protection of the switching circuit.
Patent Information
- Application Number
- CN202422970032.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-03
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2034-12-03
AI Technical Summary
In modern electronic products, the heat generated by high-power components is difficult to dissipate effectively, causing the circuit temperature to rise and potentially damaging the electronic components. This is especially true on the power circuit boards of electric vehicles, where the heat from short-circuit currents accumulates more severely.
Design a circuit board layout in which the input and output interfaces are located at opposite ends of the circuit board, the current path lengths of multiple switching circuits are equal, and the conductive areas are connected by unplugged vias to ensure uniform current distribution and increase the area of the conductive areas to improve heat dissipation.
This achieves uniform heat distribution on the circuit board, avoids overheating damage to the switching circuit, and improves the heat dissipation capacity of the power supply circuit board.
Smart Images
Figure CN223652412U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a circuit board, and more particularly to a circuit board provided with multiple switching circuits. Background Technology
[0002] Modern electronic products often use high-power electronic components. As these components become increasingly smaller, the heat they generate becomes more difficult to dissipate, causing circuit temperatures to rise rapidly. If this heat is not dissipated in time, the electronic components may be damaged due to overheating. For example, in electric vehicle applications, the battery current supplied by the battery module is distributed through multiple switching circuits on the power supply circuit board before being supplied to the vehicle. Furthermore, when the short-circuit protection of the power supply circuit board is triggered, the short-circuit current is also distributed and discharged through multiple switching circuits. In this situation, battery current or short-circuit current will generate and accumulate heat at multiple switching circuits.
[0003] Therefore, designing the layout of power supply circuit boards and multiple switching circuits on the power supply circuit board to improve the heat dissipation capacity of the power supply circuit board has become one of the goals that the industry is striving for. Utility Model Content
[0004] Therefore, the main objective of this invention is to provide a circuit board whose layout can achieve the effects of uniform current and temperature.
[0005] To achieve the above objectives, embodiments of this utility model provide a circuit board having a plurality of switching circuits arranged along a first direction, including:
[0006] The first surface layer includes:
[0007] First input conductive region; and
[0008] A first output conductive region, wherein the first input conductive region and the first output conductive region are distributed along a second direction perpendicular to the first direction;
[0009] The input interface and the multiple input terminals of the multiple switching circuits are disposed on the first input conductive area;
[0010] The output interface and the multiple output terminals of the multiple switching circuits are disposed on the first output conductive area;
[0011] The input interface is located at the first end of the first input conductive region relative to the first direction, and the output interface is located at the second end of the first output conductive region relative to the first direction.
[0012] The lengths of the multiple current paths formed by the input interface along multiple switching circuits to the output interface are substantially equal.
[0013] Preferably, the area of the first input conductive region is substantially equal to the area of the first output conductive region.
[0014] Preferably, the circuit board further includes:
[0015] The second surface layer comprises:
[0016] The second input conductive region is located in the projection area of the first input conductive region onto the second surface layer; and
[0017] The second output conductive region is located in the projection area of the first output conductive region onto the second surface layer;
[0018] Multiple input vias are used to electrically connect the first input conductive region and the second input conductive region; and
[0019] Multiple output vias are used to electrically connect the first output conductive region and the second output conductive region, wherein the multiple input vias and the multiple output vias are unplugged electroplated vias.
[0020] Preferably, the first surface layer further includes a first relay conductive region, and one of the plurality of switching circuits includes a first switch and a second switch, and the other of the plurality of switching circuits includes a third switch and a fourth switch.
[0021] The input interface, the input terminals of the first switch and the third switch are disposed on the first input conductive area, and the output terminals of the first switch and the third switch are disposed on the first relay conductive area; the input terminals of the second switch and the fourth switch are disposed on the first relay conductive area, and the output terminals of the second switch, the fourth switch and the output interface are disposed on the first output conductive area.
[0022] More preferably, the circuit board further includes:
[0023] The second surface layer comprises:
[0024] The second input conductive region is located in the projection area of the first input conductive region onto the second surface layer;
[0025] The second relay conductive region is located in the projection area of the first relay conductive region onto the second surface layer; and
[0026] The second output conductive region is located in the projection area of the first output conductive region onto the second surface layer;
[0027] Multiple input vias are used to electrically connect the first input conductive region and the second input conductive region; and
[0028] Multiple output vias are used to electrically connect the first output conductive area and the second output conductive area;
[0029] Among them, the plurality of input through holes and the plurality of output through holes are electroplated through holes that are not plugged.
[0030] Preferably, both the first surface layer and the second surface layer are bare copper.
[0031] Preferably, each switch in the plurality of switching circuits is formed by at least one of a metal-oxide-semiconductor field-effect transistor, a bipolar transistor, or a shunt resistor.
[0032] Preferably, the current flowing into the input interface is substantially evenly distributed into the multiple current paths and flows out through the output interface.
[0033] Compared with the prior art, the layout of multiple switching circuits, input interfaces and output interfaces in this utility model ensures that the heat on the power circuit board is evenly distributed and does not accumulate in some switching circuits or on the switches. As a result, the power circuit board of this utility model has better heat dissipation capacity than the prior art, and the switching circuits on the power circuit board will not be damaged due to overheating. Attached Figure Description
[0034] Figure 1 This is a schematic diagram of a power circuit board according to an embodiment of the present invention.
[0035] Figure 2 This is a top view of the first surface layer of an embodiment of the present invention.
[0036] Figure 3 This is a bottom view of the second surface layer according to an embodiment of the present invention.
[0037] Figure 4 This is a top view of the first surface layer in another embodiment of the present invention.
[0038] Figure 5 This is a bottom view of the second surface layer in another embodiment of the present invention.
[0039] Figure 6 This is a schematic diagram of the current path and current path impedance in an embodiment of this utility model.
[0040] Figure 7 This is a schematic diagram of the current path and current path impedance in the prior art. Detailed Implementation
[0041] To provide a better understanding of the purpose, structure, features, and functions of this utility model, detailed descriptions are provided below with reference to specific embodiments.
[0042] Certain terms are used in the specification and claims to refer to specific elements. It will be understood by those skilled in the art that manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements by differences in name, but rather by differences in function. The term "comprising" throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to".
[0043] The ordinal numbers used in the instruction manual, such as "first," "second," and "third," are used to modify components. They do not imply or represent any previous ordinal number of the component, nor do they represent the order of one component with another component, or the order of manufacturing methods. The use of these ordinal numbers is only to make it clear that a component with a certain name can be distinguished from another component with the same name.
[0044] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a power circuit board 1 according to an embodiment of the present invention. The power circuit board 1 includes a first surface layer UP and a second surface layer DN. A power circuit 10 is disposed on the first surface UP. In electric vehicle applications, the battery current provided by the battery module passes through the power circuit 10 and is then supplied to the electric vehicle for operation. Alternatively, when short-circuit protection is triggered, the short-circuit current is discharged through the power circuit 10. Furthermore, the surface copper foil of the conductive areas on the first surface layer UP and the second surface layer DN can be bare copper. Bare copper in direct contact with air can improve the heat dissipation capacity of the power circuit board 1. An ink layer is applied between the first surface layer UP and the second surface layer DN to separate them. The solder pads on the first surface layer UP and the second surface layer DN can be outlined by ink to define the soldering area and serve as a solder resist, and / or outlined by silkscreen printing; the present invention is not limited thereto.
[0045] Please refer to Figure 2 , Figure 2 This is a top view of the first surface layer UP according to an embodiment of the present invention. Figure 2As shown, multiple switching circuits 101, 102, and 103 are disposed on a first surface layer UP along a first direction D1. The first surface layer UP includes a first input conductive region UP1 and a first output conductive region UP2, and the first input conductive region UP1 and the first output conductive region UP2 are distributed along a second direction D2 perpendicular to the first direction D1. The power supply circuit 10 includes multiple switching circuits 101, 102, and 103, an input interface IN, and an output interface OUT. The input interface IN and multiple input terminals of the multiple switching circuits 101, 102, and 103 are disposed on the first input conductive region UP1, and the output interface OUT and multiple output terminals of the multiple switching circuits 101, 102, and 103 are disposed on the first output conductive region UP2. Preferably, the heat dissipation pads of the multiple switching circuits 101, 102, and 103 are selectively thermally connected to either the first input conductive region UP1 or the first output conductive region UP2, and the thermal connection can be achieved, for example, by soldering or filling with thermally conductive adhesive. Furthermore, the input interface IN is located at the first end of the first input conductive region UP1 relative to the first direction D1, and the output interface OUT is located at the second end of the first output conductive region UP2 relative to the first direction D1. In other words, the input interface IN and the output interface OUT are respectively located at opposite ends of the first surface layer UP in the first direction D1, as shown below. Figure 2 As shown, the input interface IN is closer to the input terminal of the left-hand switch circuit 101 and farther from the input terminal of the right-hand switch circuit 103, while the output interface OUT is closer to the output terminal of the right-hand switch circuit 103 and farther from the output terminal of the left-hand switch circuit 101. Therefore, the length of the current path from the input interface IN through the multiple switch circuits 101, 102, and 103 to the output interface OUT is substantially equal. It should be noted that the length of the current path is proportional to the current path impedance; therefore, the current path impedance through the multiple switch circuits 101, 102, and 103 is also substantially equal. In this case, the battery current or short-circuit current can be evenly distributed from the input interface IN through the multiple switch circuits 101, 102, and 103 to the output interface OUT; in other words, the current flowing through each switch circuit is substantially equal. It should be noted that the substantially equal current flowing through each switch circuit means that the heat generated by each switch circuit is also substantially equal. In short, through the layout of multiple switching circuits 101, 102, 103, input interface IN and output interface OUT in this utility model, the heat on the power circuit board 1 will be evenly distributed and will not accumulate in some switching circuits. In this way, the switching circuit of this utility model will not be damaged due to overheating.
[0046] It should be noted that, in order to enhance the heat dissipation capacity of the power circuit board 1, the area of the first input conductive region UP1 and the area of the first output conductive region UP2 are increased to increase the contact area with air. Furthermore, the area of the first input conductive region UP1 is substantially equal to the area of the first output conductive region UP2, ensuring consistent impedance across all current paths. As a result, the heat accumulated on the power circuit board 1 is evenly distributed and dissipated uniformly.
[0047] On the other hand, please refer to Figure 3 , Figure 3 This is a bottom view of the second surface layer DN according to an embodiment of the present invention. The second surface layer DN includes a second input conductive region DN1 and a second output conductive region DN2. The second input conductive region DN1 is located in the projection area of the first input conductive region UP1 onto the second surface layer DN, and the second output conductive region DN2 is located in the projection area of the first output conductive region UP2 onto the second surface layer DN. In other words, the area of the second input conductive region DN1 is substantially equal to the area of the second output conductive region DN2. It should be noted that the power circuit board 1 also includes multiple input through holes and multiple output through holes, which can be unplugged plated through holes (PTH) to improve the heat dissipation capacity of the power circuit board 1. The multiple input through holes are used to electrically connect the first input conductive region UP1 and the second input conductive region DN1, and the multiple output through holes are used to electrically connect the first output conductive region UP2 and the second output conductive region DN2. In this way, the heat accumulated on the first surface UP of the power circuit board 1 can be conducted to the second surface DN through the multiple input through holes and the multiple output through holes. Furthermore, the second surface layer DN of this invention is also bare copper. In other words, the second input conductive area DN1 and the second output conductive area DN2 can directly contact the air and dissipate heat.
[0048] Please refer to Figure 4 , Figure 4This is a top view of the first surface layer of the power circuit board 2 according to another embodiment of the present invention. The power circuit board 2 is derived from the power circuit board 1, therefore identical components are represented by the same symbols. The difference between the power circuit board 2 and the power circuit board 1 is that the switching circuit consists of multiple switches SW1, SW2, SW3, and SW4, and the first surface layer UP also includes a first relay conductive area UP3. It should be noted that the multiple switches SW1, SW2, SW3, and SW4 can be resistive components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar transistors (BJTs), relays, or shunt resistors, but are not limited thereto. In this embodiment, such as... Figure 4 As shown, the input interface IN and the input terminal of the first switch SW1 are located on the first input conductive area UP1, and the output terminal of the first switch SW1 is located on the first relay conductive area UP3. The input terminal of the second switch SW2 is located on the first relay conductive area UP3, and the output terminal of the second switch SW2 is located on the first output conductive area UP2. The input terminal of the third switch SW3 is located on the first input conductive area UP1, and the output terminal of the third switch SW3 is located on the first relay conductive area UP3. The input terminal of the output interface OUT and the input terminal of the fourth switch SW4 are located on the first relay conductive area UP3, and the output terminal of the fourth switch SW4 is located on the first output conductive area UP2. Preferably, as follows... Figure 4 As shown, the multiple switches SW1, SW2, SW3, and SW4 are thermally connected to the first input conductive region UP1, the first relay conductive region UP3, or the first output conductive region UP2, respectively, similar to the previous embodiment, and will not be described again. Specifically, the input interface IN is located at the first end of the first input conductive region UP1 relative to the first direction D1, and the output interface OUT is located at the second end of the first output conductive region UP2 relative to the first direction D1. Figure 4As shown, the input interface IN is closer to the input terminal of the first switch SW1 on the left and farther from the input terminal of the third switch SW3 on the right, while the output interface OUT is closer to the output terminal of the fourth switch SW4 on the right and farther from the output terminal of the second switch SW2 on the left. Furthermore, to clearly illustrate the layout of the various areas and components on the first surface layer UP, this invention divides the first surface layer UP into four quadrants: I, II, III, and IV. Specifically, the input interface IN and the first switch SW1 are located in the second quadrant II, the second switch SW2 is located in the third quadrant III, the third switch SW3 is located in the first quadrant I, and the output interface OUT and the fourth switch SW4 are located in the fourth quadrant IV. In this way, the lengths of the current path from the input interface IN along switches SW1 and SW2 to the output interface OUT and the current path from the input interface IN along switches SW3 and SW4 to the output interface OUT are substantially equal. Therefore, the impedances of the current paths through switches SW1 and SW2 and switches SW3 and SW4 are also substantially equal. In this configuration, the battery current or short-circuit current can be evenly distributed from the input interface IN through switches SW1, SW2, SW3, and SW4 to the output interface OUT. In other words, the current flowing through switches SW1, SW2, SW3, and SW4 is substantially equal. In short, through the arrangement of multiple switches SW1, SW2, SW3, SW4, the input interface IN, and the output interface OUT in this invention, the heat on the power circuit board 2 is evenly distributed and does not accumulate on some switches. Therefore, the switches of this invention will not be damaged due to overheating.
[0049] It should be noted that, in order to enhance the heat dissipation capacity of the power circuit board 1, the area of the first input conductive region UP1, the area of the first output conductive region UP2, and the area of the first relay conductive region UP3 are increased to increase the area in contact with air. Furthermore, the area of the first input conductive region UP1 is substantially equal to the areas of the first output conductive region UP2 and the first relay conductive region UP3, respectively, ensuring consistent impedance across current paths. In this way, the heat accumulated on the power circuit board 1 is evenly distributed and dissipated uniformly.
[0050] Please refer to Figure 5 , Figure 5This is a bottom view of the second surface layer DN according to another embodiment of the present invention. The second surface layer DN includes a second input conductive region DN1, a second relay conductive region DN3, and a second output conductive region DN2. The second input conductive region DN1 is located in the projection area of the first input conductive region UP1 onto the second surface layer DN; the second output conductive region DN2 is located in the projection area of the first output conductive region UP2 onto the second surface layer DN; and the second relay conductive region DN3 is located in the projection area of the first relay conductive region UP3 onto the second surface layer DN. In other words, the area of the second input conductive region DN1 is substantially equal to the area of the first input conductive region UP1, the area of the second output conductive region DN2 is substantially equal to the area of the first output conductive region UP2, and the area of the second relay conductive region DN3 is substantially equal to the area of the first relay conductive region UP3. Furthermore, the surface copper foil of the second surface layer DN of the present invention is also bare copper. In other words, the exposed copper on the surfaces of the second input conductive region DN1, the second output conductive region DN2, and the second relay conductive region DN3 can dissipate heat by directly contacting the air with the surface copper foil.
[0051] In one embodiment, please refer to Figure 6 , Figure 6 This is a schematic diagram of the current path and current path impedance according to an embodiment of the present invention. Figure 6 As shown, the current path impedance corresponding to current path A is 10R (1R+5R+4R); the current path impedance corresponding to current path B is 10R (2R+5R+3R); the current path impedance corresponding to current path C is 10R (3R+5R+2R); and the current path impedance corresponding to current path D is 10R (4R+5R+1R). In other words, the four current paths in this embodiment of the invention have the same length, and their corresponding current path impedances are also substantially equal. Furthermore, please refer to... Figure 7 , Figure 7 This is a schematic diagram of the current path and current path impedance in existing technology. (Example) Figure 7 As shown, the current path impedance corresponding to current path E is 9R (2R+5R+2R); the current path impedance corresponding to current path F is 7R (1R+5R+1R); the current path impedance corresponding to current path G is 7R (1R+5R+1R); and the current path impedance corresponding to current path H is 9R (2R+5R+2R). In other words, the four current paths in the prior art have different lengths and different current path impedances. Therefore, the switching circuits on current paths F and G in the prior art are prone to damage due to the large current flow and the generation of more heat.
[0052] In summary, through the layout of multiple switching circuits, input interface IN, and output interface OUT in this utility model, the heat on the power supply circuit board is evenly distributed and will not accumulate in some switching circuits or on the switches. As a result, compared with the prior art, the power supply circuit board of this utility model has better heat dissipation capabilities, and the switching circuits set on the power supply circuit board will not be damaged due to overheating.
[0053] This utility model has been described by the above-described embodiments; however, these embodiments are merely examples for implementing this utility model. It must be noted that the disclosed embodiments do not limit the scope of this utility model. Conversely, any modifications and refinements made without departing from the spirit and scope of this utility model are within the scope of patent protection of this utility model.
Claims
1. A circuit board, characterized in that, The circuit board has multiple switching circuits arranged along the first direction, including: The first surface layer includes: First input conductive region; and A first output conductive region, wherein the first input conductive region and the first output conductive region are distributed along a second direction perpendicular to the first direction; The input interface and the multiple input terminals of the multiple switching circuits are disposed on the first input conductive area; The output interface and the multiple output terminals of the multiple switching circuits are disposed on the first output conductive area; The input interface is located at the first end of the first input conductive region relative to the first direction, and the output interface is located at the second end of the first output conductive region relative to the first direction. The lengths of the multiple current paths formed by the input interface along multiple switching circuits to the output interface are substantially equal.
2. The circuit board as described in claim 1, characterized in that, The area of the first input conductive region is substantially equal to the area of the first output conductive region.
3. The circuit board as described in claim 1, characterized in that, The circuit board also includes: The second surface layer comprises: The second input conductive region is located in the projection area of the first input conductive region onto the second surface layer; and The second output conductive region is located in the projection area of the first output conductive region onto the second surface layer; Multiple input vias are used to electrically connect the first input conductive area and the second input conductive area; as well as Multiple output vias are used to electrically connect the first output conductive region and the second output conductive region, wherein the multiple input vias and the multiple output vias are unplugged electroplated vias.
4. The circuit board as described in claim 1, characterized in that, The first surface layer also includes a first relay conductive region, and one of the plurality of switching circuits includes a first switch and a second switch, and the other of the plurality of switching circuits includes a third switch and a fourth switch. The input interface, the input terminals of the first switch and the third switch are disposed on the first input conductive area, and the output terminals of the first switch and the third switch are disposed on the first relay conductive area; the input terminals of the second switch and the fourth switch are disposed on the first relay conductive area, and the output terminals of the second switch, the fourth switch and the output interface are disposed on the first output conductive area.
5. The circuit board as described in claim 4, characterized in that, The circuit board also includes: The second surface layer comprises: The second input conductive region is located in the projection area of the first input conductive region onto the second surface layer; The second relay conductive region is located in the projection area of the first relay conductive region onto the second surface layer; as well as The second output conductive region is located in the projection area of the first output conductive region onto the second surface layer; Multiple input vias are used to electrically connect the first input conductive area and the second input conductive area; as well as Multiple output vias are used to electrically connect the first output conductive area and the second output conductive area; Among them, the plurality of input through holes and the plurality of output through holes are electroplated through holes that are not plugged.
6. The circuit board as described in claim 3, characterized in that, Both the first and second surface layers are bare copper.
7. The circuit board as described in claim 1, characterized in that, Each switch in the plurality of switching circuits is formed by at least one of a metal-oxide-semiconductor field-effect transistor, a bipolar transistor, or a shunt resistor.
8. The circuit board as described in claim 1, characterized in that, The current flowing into the input interface is essentially evenly distributed into the multiple current paths and flows out through the output interface.