Current expanding circuit for LDO (Low Dropout Regulator) chip

Abstract

The utility model discloses a current expanding circuit for an LDO (Low Dropout Regulator) chip, which relates to the technical field of power supply chips and comprises an input circuit, a current expanding circuit, an LDO circuit and an output circuit, the current expanding circuit is connected with the output end of the input circuit and is used for providing a current expanding branch; the LDO circuit is connected with the current expanding circuit and is used for providing a main current path; the input end of the output circuit is connected with the common output end of the current expanding circuit and the LDO circuit, and the output circuit outputs voltage to a backward stage. According to the current expanding circuit for the LDO chip, the LDO chip does not need to be replaced under a certain condition through the circuit, meanwhile, the current of a voltage stabilizer can be increased, and the over-current requirement of the circuit is met.

Description

TECHNICAL FIELD

[0001] The utility model relates to power supply chip technical field, specifically speaking, it is a kind of for the current expansion circuit of LDO chip. BACKGROUND

[0002] LDO is Low Dropout Regulator, it is a kind of low dropout linear regulator, with extremely low self-noise and higher power supply rejection ratio, is the most commonly used power supply chip in integrated circuit design.

[0003] But LDO chip as linear power supply, in voltage conversion process, can be equivalent to series resistance, with Rds indicates;Voltage difference △U=Uin-Uout, with Vdropout indicates, in circuit work time for fixed value;Series circuit current is Iout, by load decision;Then LDO power consumption:W=Vdropout*Iout.It can be seen from this, the greater the current in circuit, the greater LDO power consumption, the more serious heat generation;And due to material restriction, our common LDO package, small size, limited heat dissipation, so LDO current capacity (Imax) cannot be infinite, common LDO package power consumption see Figure 1 Exceeding the rated current of LDO chip, will lead to LDO chip overheating, burn LDO chip. INVENTION CONTENTS

[0004] The utility model aims at providing a kind of current expansion circuit for LDO chip, for solving the problem that the overcurrent capacity of conventional LDO chip in prior art is limited, exceeding the rated current of LDO chip, will lead to LDO chip overheating, burn LDO chip.

[0005] The utility model solves the above-mentioned problems by the following technical solutions:

[0006] A kind of current expansion circuit for LDO chip, including input circuit, current expansion circuit, LDO circuit and output circuit, wherein:

[0007] Input circuit, for providing power supply;

[0008] Current expansion circuit, the output end of the input circuit is connected, for providing current expansion branch;

[0009] LDO circuit, with the current expansion circuit is connected, for providing main current path;

[0010] Output circuit, its input end is connected with the common output end of current expansion circuit, LDO circuit, and it is towards the output voltage of back stage.

[0011] Furthermore, the current-amplifying circuit includes a current-limiting resistor Rx and a transistor Q1. The first end of the current-limiting resistor Rx and the emitter of the transistor Q1 are connected to the output terminal of the input circuit. The second end of the current-limiting resistor Rx is connected to the base of the transistor Q1 and is connected to the input terminal of the LDO circuit. The collector of the transistor Q1 serves as the output terminal of the current-amplifying circuit and is connected to the output terminal of the LDO circuit and the input terminal of the output circuit.

[0012] Furthermore, the LDO circuit includes an LDO chip, a feedback resistor R1, and a feedback resistor R2. The voltage input terminal of the LDO chip is connected to the second terminal of the current-limiting resistor Rx. The voltage output terminal of the LDO chip is connected to the collector of the transistor Q1 and the first terminal of the feedback resistor R1. The second terminal of the feedback resistor R1 is connected to the first terminal of the feedback resistor R2 and the reference terminal of the LDO chip. The second terminal of the resistor R2 is grounded.

[0013] Furthermore, the output circuit includes an output voltage terminal, capacitor C3 and capacitor C4. The output voltage terminal, the first terminal of capacitor C3 and the first terminal of capacitor C4 are connected to the collector of transistor Q1, and the second terminal of capacitor C3 and the second terminal of capacitor C4 are grounded.

[0014] Furthermore, the transistor Q1 is a PNP transistor.

[0015] Furthermore, the input circuit includes an input power supply, a capacitor C1, and a capacitor C2. The first terminal of the input power supply, the first terminal of capacitor C1, and the first terminal of capacitor C2 are connected to the first terminal of the current-limiting resistor Rx, and the second terminal of capacitor C1 and the second terminal of capacitor C2 are grounded.

[0016] Compared with the prior art, this utility model has the following advantages and beneficial effects:

[0017] (1) This utility model provides a current amplification circuit for LDO chips. This circuit can increase the voltage regulator current and meet the circuit overcurrent requirements without replacing the LDO chip under certain conditions.

[0018] (2) This utility model utilizes a transistor current amplification circuit to increase the overcurrent capability of the LDO circuit; especially in small-volume, low-current LDOs, it can significantly improve the circuit load capacity at low cost.

[0019] (3) This utility model utilizes a transistor current amplification circuit to reduce the current of the LDO circuit, thereby reducing the heat generation of the LDO chip. Attached Figure Description

[0020] Figure 1 Power consumption diagram of common LDO packages in existing technologies;

[0021] Figure 2 This is the circuit schematic diagram of this utility model;

[0022] Figure 3 The equivalent circuit diagram of the internal structure of an LDO circuit;

[0023] Figure 4 This is a simulation diagram of the system current distribution of this utility model;

[0024] Among them, 1-input circuit; 2-current amplification circuit; 3-LDO circuit; 4-output circuit; U1-LDO chip; U2-comparison amplifier. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the embodiments, but the implementation of the present invention is not limited thereto.

[0026] Example:

[0027] A current amplification circuit for an LDO chip includes an input circuit 1, a current amplification circuit 2, an LDO circuit 3, and an output circuit 4, wherein:

[0028] Input circuit 1 is used to provide power;

[0029] The current amplification circuit 2 is connected to the output terminal of the input circuit 1 and is used to provide a current amplification branch.

[0030] LDO circuit 3 is connected to the current amplification circuit 2 and is used to provide the main current path;

[0031] Output circuit 4 has its input terminal connected to the common output terminal of current amplification circuit 2 and LDO circuit 3, and outputs voltage to the next stage.

[0032] Example 2:

[0033] Based on Example 1, combined with Appendix Figure 2 As shown, the current amplification circuit 2 includes a current-limiting resistor Rx and a transistor Q1. The first end of the current-limiting resistor Rx and the emitter of the transistor Q1 are connected to the output terminal of the input circuit 1. The second end of the current-limiting resistor Rx is connected to the base of the transistor Q1 and is connected to the input terminal of the LDO circuit 3. The collector of the transistor Q1 serves as the output terminal of the current amplification circuit 2 and is connected to the output terminal of the LDO circuit 3 and the input terminal of the output circuit 4.

[0034] Furthermore, combined Figure 2 and Figure 3As shown, the LDO circuit 3 includes an LDO chip U1, a feedback resistor R1, and a feedback resistor R2. The voltage input terminal of the LDO chip U1 is connected to the second terminal of the current limiting resistor Rx. The voltage output terminal of the LDO chip U1 is connected to the collector of the transistor Q1 and the first terminal of the feedback resistor R1. The second terminal of the feedback resistor R1 is connected to the first terminal of the feedback resistor R2 and the reference terminal of the LDO chip U1. The second terminal of the resistor R2 is grounded.

[0035] Furthermore, the output circuit 4 includes an output voltage terminal, a capacitor C3, and a capacitor C4. The output voltage terminal, the first terminal of capacitor C3, and the first terminal of capacitor C4 are connected to the collector of transistor Q1, and the second terminal of capacitor C3 and the second terminal of capacitor C4 are grounded.

[0036] Furthermore, the transistor Q1 is a PNP transistor.

[0037] Furthermore, the input circuit 1 includes an input power supply, a capacitor C1, and a capacitor C2. The first end of the input power supply, the first end of the capacitor C1, and the first end of the capacitor C2 are connected to the first end of the current-limiting resistor Rx, and the second end of the capacitor C1 and the second end of the capacitor C2 are grounded.

[0038] like Figure 3 As shown in the LDO datasheet, Vout = 1.25 × (1 + R2 / R1). The LDO can regulate the output voltage because it compares the output voltage FB with the internal reference voltage Vref using a comparator amplifier U2. The difference between the two is amplified by the comparator amplifier U2 to regulate an internal series regulating transistor VT (commonly a P-channel MOSFET, or PMOS). The PMOS operates in the amplification region, and the output of the comparator amplifier U2 controls the internal resistance of the PMOS, thus controlling the stability of the output voltage.

[0039] The current amplification circuit of this invention uses a PNP transistor Q1 with appropriate power connected in parallel to the input and output terminals of the LDO chip U1; a current-limiting resistor Rx is connected in series between the base and emitter of the transistor Q1; the voltage difference across the current-limiting resistor Rx is ΔVeb = Ue - Ub = Ir * Rx; when ΔVeb < 0.7V, the transistor Q1 operates in the cutoff region, and Ir = Ildo; when ΔVeb ≥ 0.7V, the transistor Q1 operates from the cutoff region into the amplification region and saturation region; when the current-limiting resistor Rx is fixed according to requirements, ΔVeb changes with the current Ir.

[0040] The working principle of the circuit of this utility model is as follows:

[0041] When the output load current is small, ΔVeb=Ir*Rx=Ildo*Rx<0.7V, transistor Q1 operates in the cutoff region and does not conduct. At this time, the current amplification circuit 2 does not work, and all the load current will be provided through the LDO circuit 3, Iout=Ildo.

[0042] When the output load current increases, ΔVeb=Ir*Rx=(Ibe+Ildo)*Rx>Ildo*Rx>0.7V, transistor Q1 starts to conduct from the cutoff region into the amplification region. Ice forms a current-amplifying branch, and all the load current will be provided by LDO circuit 3 and current-amplifying circuit 2 together, Iout=Ildo+Ice.

[0043] When the output load current continues to increase while the output voltage remains constant, and ΔVeb=Ir*Rx=(Ibe+Ildo)*Rx>Ildo*Rx>0.7V, transistor Q1 moves from the amplification region closer to the saturation region. The internal resistance between the emitter and collector of transistor Q1 decreases. At this time, the increased load current is mainly provided by the current-amplifying circuit Ice. As the load current continues to increase, the transistor moves infinitely closer to the saturation region, and the internal resistance decreases, but it cannot enter the saturation region. Because the transistor's ΔVce changes, that is, the ΔVsd of the PMOS transistor inside the LDO decreases (the two are connected in parallel), causing Uout to rise. The operational amplifier inside the LDO will adjust the PMOS gate voltage, increasing the PMOS internal resistance and reducing the LDO branch current. After the Rx current decreases, Q1 will enter the cutoff state, and the output voltage will also decrease accordingly. Through the above adjustments, the loop dynamic balance is achieved, ensuring the stability of the output voltage.

[0044] Component Selection: When the maximum overcurrent capability of the LDO chip U1 in the circuit is 200mA, we take 140mA as the overcurrent balance point. Calculations show Rx = 0.7V / 0.14A ≈ 5Ω; that is, when the current is below 140mA, ΔVeb is less than 0.7V, the transistor operates in the cutoff region, and the load current is provided by the LDO; when the current is greater than 140mA, ΔVeb is greater than 0.7V, the transistor operates in the saturation region, the current amplification circuit 2 begins to intervene, and the LDO circuit 3 and the current amplification circuit 2 jointly provide the load current. The system current distribution simulation is as follows: Figure 4 As shown. By adjusting the value of the current-limiting resistor Rx, the current-amplifying balance point of the circuit can be adjusted.

[0045] Although the present invention has been described herein with reference to illustrative embodiments, the above embodiments are merely preferred embodiments of the present invention, and the implementation of the present invention is not limited to the above embodiments. It should be understood that those skilled in the art can design many other modifications and implementations, which will fall within the scope and spirit of the principles disclosed in this application.

Claims

1. A current amplification circuit for an LDO chip, characterized in that, It includes input circuitry, current amplification circuitry, LDO circuitry, and output circuitry, wherein: Input circuitry, used to provide power; A current-amplifying circuit, connected to the output terminal of the input circuit, is used to provide a current-amplifying branch; An LDO circuit, connected to the current amplification circuit, is used to provide the main current path; The output circuit has its input terminal connected to the common output terminal of the current amplification circuit and the LDO circuit, and outputs voltage to the subsequent stage.

2. The current amplification circuit for an LDO chip according to claim 1, characterized in that, The current-amplifying circuit includes a current-limiting resistor Rx and a transistor Q1. The first end of the current-limiting resistor Rx and the emitter of the transistor Q1 are connected to the output terminal of the input circuit. The second end of the current-limiting resistor Rx is connected to the base of the transistor Q1 and is connected to the input terminal of the LDO circuit. The collector of the transistor Q1 serves as the output terminal of the current-amplifying circuit and is connected to the output terminal of the LDO circuit and the input terminal of the output circuit.

3. The current amplification circuit for an LDO chip according to claim 2, characterized in that, The LDO circuit includes an LDO chip, a feedback resistor R1, and a feedback resistor R2. The voltage input terminal of the LDO chip is connected to the second terminal of the current-limiting resistor Rx. The voltage output terminal of the LDO chip is connected to the collector of the transistor Q1 and the first terminal of the feedback resistor R1. The second terminal of the feedback resistor R1 is connected to the first terminal of the feedback resistor R2 and the reference terminal of the LDO chip. The second terminal of the resistor R2 is grounded.

4. The current amplification circuit for an LDO chip according to claim 2, characterized in that, The output circuit includes an output voltage terminal, capacitor C3 and capacitor C4. The output voltage terminal, the first end of capacitor C3 and the first end of capacitor C4 are connected to the collector of transistor Q1, and the second end of capacitor C3 and the second end of capacitor C4 are grounded.

5. A current amplification circuit for an LDO chip according to claim 2, characterized in that, The transistor Q1 is a PNP transistor.

6. A current amplification circuit for an LDO chip according to claim 2, characterized in that, The input circuit includes an input power supply, capacitor C1 and capacitor C2. The first end of the input power supply, capacitor C1 and capacitor C2 are connected to the first end of the current limiting resistor Rx, and the second end of capacitor C1 and capacitor C2 are grounded.

Images