Substrate structure
By setting an insulating block within the die-placement area of the substrate structure to cover part of the circuit layer, the delamination problem caused by poor adhesion between the adhesive and the circuit layer is solved, the adhesive flow rate is increased and air bubbles are avoided, thereby improving the reliability of the packaging substrate.
Patent Information
- Application Number
- CN202422552700.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-16
- Filing Date
- 2024-10-22
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2034-10-22
AI Technical Summary
In existing flip-chip packaging structures, poor adhesion between the adhesive and the circuit layer leads to delamination problems, and large openings can cause the adhesive to flow more slowly and generate bubbles.
Multiple insulating blocks are set in the die-placement area of the substrate structure to cover part of the circuit layer, reducing the contact area between the primer and copper. The delamination problem is improved by the spacing between the insulating blocks and the circuit layer, and the primer flow rate is increased to avoid the generation of bubbles.
It effectively reduces delamination, increases the flow rate of the base adhesive, avoids the generation of bubbles, and improves the reliability and production efficiency of the encapsulation substrate.
Smart Images
Figure CN223665457U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a substrate structure, and more particularly to a substrate structure that can reduce delamination problems. Background Technology
[0002] With the development of the electronics industry, today's electronic products are trending towards thinner, smaller, and more versatile designs, and semiconductor packaging technology has also developed different packaging forms accordingly. To meet the requirements of high integration and miniaturization of semiconductor devices, the industry mostly adopts flip-chip packaging structures.
[0003] Figure 1A and Figure 1B These are a cross-sectional view and a partial top view of the existing flip-chip package 1. Figure 1A As shown, a packaging substrate 10 has a circuit layer 100 made of copper wires, an insulating protective layer 101, and an opening 102 for exposing the circuit layer 100. A die placement region D is defined on the packaging substrate 10. A semiconductor chip 11 is bonded to the circuit layer 100 in the die placement region D of the packaging substrate 10 via multiple solder bumps 12. Then, an adhesive base 13 is formed between the semiconductor chip 11 and the packaging substrate 10 to cover the multiple solder bumps 12. However, due to the large contact area, the adhesive base 13 and the circuit layer 100 in the die placement region D have poor adhesion, which easily leads to delamination problems, and the adhesive base 13 is also easily separated from the packaging substrate 10. In addition, the large area of the single opening 102 can slow down the flow rate of the adhesive base 13, which can easily cause the formation of air pockets.
[0004] Therefore, overcoming the various problems of the existing technologies has become an urgent issue for the industry. Utility Model Content
[0005] This utility model provides a substrate structure, including: a substrate body, on one surface of which a circuit layer is disposed and a crystal placement region is defined on the surface; and a plurality of insulating blocks formed on the surface of the substrate body and located within the crystal placement region to cover part of the circuit layer.
[0006] As described above, in the substrate structure, any two adjacent insulating blocks are spaced apart.
[0007] As described above, the substrate structure has a spacing greater than 70 μm.
[0008] As described above, the circuit layer includes a plurality of electrical contact pads within the die-placement area for mounting an electronic component, and there is a spacing between any of the plurality of insulating blocks and any of the plurality of electrical contact pads.
[0009] As with the aforementioned substrate structure, the spacing is greater than 20 μm.
[0010] As described above in the substrate structure, the plurality of insulating blocks are circular in shape.
[0011] As described above, the circular substrate structure has a diameter greater than 100 μm.
[0012] The substrate structure described above also includes an insulating protective layer, wherein the insulating protective layer is disposed on the surface of the substrate body and has at least one opening corresponding to the crystal region and exposing a portion of the circuit layer.
[0013] As described above in the substrate structure, the plurality of insulating blocks are disposed in the opening within the crystal placement area and are spaced apart from the insulating protective layer.
[0014] As described above in the substrate structure, a portion of the opening is located within the crystal placement area, while the remainder is located outside the crystal placement area.
[0015] In summary, the substrate structure of this utility model, by setting multiple insulating blocks in the crystal placement area on the surface of the substrate body, can cover part of the circuit layer by these multiple insulating blocks, thereby effectively reducing the exposed copper ratio and reducing the contact area between the primer and the copper, thus improving the delamination problem, and effectively increasing the primer flow rate to avoid the problem of bubble generation. Attached Figure Description
[0016] Figure 1A and Figure 1B These are a cross-sectional view and a partial top view of an existing flip-chip packaging structure.
[0017] Figure 2 This is a top view schematic diagram of the substrate structure of this utility model.
[0018] Figure 3 This is a partially enlarged schematic diagram of the substrate structure of this utility model.
[0019] Explanation of reference numerals in the attached figures
[0020] 1 Flip Chip Package
[0021] 10-pack substrate
[0022] 100 line layers
[0023] 101 Insulation Protection Layer
[0024] 102 opening
[0025] 11 Semiconductor Chips
[0026] 12 solder bumps
[0027] 13 base rubber
[0028] 2. Substrate Structure
[0029] 20 substrate body
[0030] 200 surface
[0031] 201 Line Layer
[0032] 201a Electrical Contact Pad
[0033] 201b conductive trace
[0034] 21 Insulation Blocks
[0035] 22 Insulation protective layer
[0036] 220 opening
[0037] D crystal placement area
[0038] D1,D2 interval distance
[0039] D is the diameter. Detailed Implementation
[0040] The following specific embodiments illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification.
[0041] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the implementation conditions of this utility model. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this utility model, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above" and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of implementation of this utility model. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this utility model.
[0042] Figure 2 This is a top view of the substrate structure 2 of this utility model. Figure 2 As shown, the substrate structure 2 is, for example, a packaging substrate for carrying a semiconductor chip, which includes a substrate body 20 and a plurality of insulating blocks 21.
[0043] The substrate body 20 is, for example, a substrate with a core layer or a coreless substrate. The substrate body 20 has a circuit layer 201 disposed on its surface 200 and a crystal placement region D defined on the surface 200.
[0044] In this embodiment, the substrate body 20 includes at least one insulating layer and at least one wiring layer (not shown) formed on the insulating layer. The wiring layer may be, for example, a fan-out redistribution layer (RDL), with the outermost wiring layer serving as the circuit layer 201. The circuit layer 201 includes a plurality of electrical contact pads 201a and a plurality of conductive traces 201b connecting the electrical contact pads 201a. A die-placement region D is used to mount electronic components, such as semiconductor chips or passive components, thereon. For example, electronic components are mounted on the electrical contact pads 201a via conductive bumps to form an electronic package.
[0045] Furthermore, the material forming each wiring layer is copper, and each insulating layer is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0046] An insulating protective layer 22 is formed on the surface 200 of the substrate body 20. The insulating protective layer 22 has at least one opening 220. In this embodiment, the opening 220 corresponds to the die placement area D and exposes a portion of the circuit layer 201. A portion of the opening 220 is located within the die placement area D, while the remainder is located outside the die placement area D. The opening 220 located outside the die placement area D allows the underfill to flow effectively between the electronic components and the substrate body 20.
[0047] Furthermore, the material of the insulating protective layer 22 can be, for example, a solder resist material such as green paint or ink.
[0048] Multiple insulating blocks 21 are disposed on the surface 200 of the substrate body 20 and located in the crystal placement area D within the opening 220 to cover part of the circuit layer 201. Furthermore, the multiple insulating blocks 21 are spaced apart from each other and from the insulating protective layer 22.
[0049] Furthermore, the material of the insulating block 21 can be, for example, a solder resist material such as green paint or ink, and the material of the insulating block 21 can be the same as the material of the insulating protective layer 22. Moreover, the material of the insulating block 21 can also be different from that of the insulating protective layer 22, and this utility model is not limited thereto.
[0050] like Figure 3As shown, any two adjacent insulating blocks 21 have a spacing distance D1 between them, which is greater than 70 μm, for example, it can be 80 μm, but this invention is not limited to this. The spacing distance D1 between any two adjacent insulating blocks 21 can avoid the problem of air bubbles being generated when the primer flows in the opening 220.
[0051] Furthermore, there is also a gap D2 between any insulating block 21 and the electrical contact pad 201a. This gap D2 is greater than 20 μm, for example, it can be 30 μm, but the present invention is not limited thereto. This gap D2 can effectively improve the workability of the substrate.
[0052] Furthermore, the insulating block 21 is circular with a diameter d greater than 100 μm, for example, it can be 125 μm, preferably 110 μm, but the present invention is not limited thereto.
[0053] In summary, the substrate structure of this utility model, by setting multiple insulating blocks in the crystal placement area on the surface of the substrate body, can cover part of the circuit layer through these multiple insulating blocks, thereby effectively reducing the exposed copper (circuit layer) ratio and reducing the contact area between the primer and copper, thus improving the delamination problem, and effectively increasing the primer flow rate to avoid the problem of bubble generation.
[0054] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this utility model. Therefore, the scope of protection of this utility model should be as set forth in the claims.
Claims
1. A substrate structure, characterized in that, include: A circuit layer is disposed on one surface of the substrate body, and a crystal placement area is defined on the surface thereon. as well as Multiple insulating blocks are formed on the surface of the substrate body and located within the crystal placement area to cover part of the circuit layer. The multiple insulating blocks are circular in shape and have a diameter greater than 100 μm.
2. The substrate structure as described in claim 1, characterized in that, There is a gap between any two adjacent insulating blocks.
3. The substrate structure as described in claim 2, characterized in that, The interval is greater than 70 μm.
4. The substrate structure as described in claim 1, characterized in that, The circuit layer includes multiple electrical contact pads within the crystal placement area for mounting an electronic component, and there is a spacing between any of the multiple insulating blocks and any of the multiple electrical contact pads.
5. The substrate structure as described in claim 4, characterized in that, The interval is greater than 20 μm.
6. The substrate structure as described in claim 1, characterized in that, The substrate structure also includes an insulating protective layer, wherein the insulating protective layer is disposed on the surface of the substrate body and has at least one opening corresponding to the crystal region and exposing a portion of the circuit layer.
7. The substrate structure as described in claim 6, characterized in that, The plurality of insulating blocks are disposed in the opening within the crystal placement area and are spaced apart from the insulating protective layer.
8. The substrate structure as described in claim 6, characterized in that, A portion of the opening is located within the crystal placement area, while the remainder is located outside the crystal placement area.