Logic circuit for increasing common-mode transient immunity of edge modulation and demodulation digital isolator

Abstract

The utility model discloses a logic circuit for increasing common-mode transient immunity of a digital isolator for edge modulation and demodulation. The logic circuit comprises a transmitting end TX and a receiving end RX, the receiving end RX comprises a latch; a fully differential amplifier; an envelope comparator; the forward common-mode voltage change rate detection circuit is a transistor MP1, the transistor MP1 is connected with the output end of the latch, and the transistor MP1 is switched on or switched off by an output voltage signal of the latch; the negative common-mode voltage change rate detection circuit is a transistor MN5, the transistor MN5 is connected with the output end of the latch, and the transistor MN5 is switched on or switched off by an output voltage signal of the latch; and the logic circuit is used for comparing an output signal of the output end of the envelope comparator, an output signal of the positive common-mode voltage change rate detection circuit and an output signal of the negative common-mode voltage change rate detection circuit, and outputting a logic processing result.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of edge modulation demodulation digital isolator, and particularly relates to a logic circuit for increasing the common-mode transient immunity of an edge modulation demodulation digital isolator. BACKGROUND

[0002] In actual application, the voltage difference between the two grounds in the capacitor isolation digital isolator is transiently changed. If the transient change rate of the voltage difference between the two grounds exceeds a certain limit value, the normal transmission of the digital signal will be damaged. The limit value is the common-mode transient immunity of the digital isolator, and the common-mode transient immunity is an important performance parameter of the digital isolator product.

[0003] The common-mode transient immunity indicates the inhibition ability of the isolation circuit to the high-speed transient signal passing through the isolation layer and damaging the output state, and also reflects the sensitivity of the isolation circuit to the fast transient signal interference. A higher common-mode transient immunity index means that the isolation circuit or the isolation device can ensure that the output (OUT) does not have an error when the common-mode voltage impact isolation barrier at a higher rising or falling rate. CONTENT OF THE UTILITY MODEL

[0004] In order to overcome the defects of the prior art, the application provides a logic circuit for increasing the common-mode transient immunity of an edge modulation demodulation digital isolator, which can improve the common-mode transient immunity of the logic circuit.

[0005] The utility model provides a kind of logic circuit for increasing the common-mode transient immunity of edge modulation demodulation digital isolator, and the logic circuit includes transmitting end TX and receiving end RX, and the transmitting end TX is connected between the receiving end RX, and the transmitting end TX sends voltage signal to the receiving end RX;

[0006] Wherein, including in the receiving end RX:

[0007] Latches, the latches are locked to the voltage signal received by the receiving end RX;

[0008] Full differential amplifier, the input end of the full differential amplifier is connected with the output end of the latches, and the full differential amplifier amplifies the voltage signal locked by the latches;

[0009] Envelope comparator, the input end of the envelope comparator is connected with the output end of the full differential amplifier, and the envelope comparator compares the output voltage of the full differential amplifier and outputs corresponding high-level signal or low-level signal;

[0010] A positive common-mode voltage rate of change detection circuit, which is a transistor MP1, is connected to the output end of the latch, and is turned on or turned off by the output voltage signal of the latch;

[0011] A negative common-mode voltage rate of change detection circuit, which is a transistor MN5, is connected to the output end of the latch, and is turned on or turned off by the output voltage signal of the latch;

[0012] A logic circuit, whose input end is connected to the output end of the envelope comparator, the positive common-mode voltage rate of change detection circuit and the negative common-mode voltage rate of change detection circuit, compares the output signals of the output end of the envelope comparator, the positive common-mode voltage rate of change detection circuit and the negative common-mode voltage rate of change detection circuit, and outputs a logic processing result.

[0013] According to the logic circuit for increasing the common-mode transient immunity of the edge-modulation-demodulation digital isolator provided in the application, the transistor MP1 is a PMOS transistor, and the transistor MN5 is an NMOS transistor.

[0014] According to the logic circuit for increasing the common-mode transient immunity of the edge-modulation-demodulation digital isolator provided in the application, the input voltage VDD1 of the transmitting end TX and the ground end GND1 are not the same as the input voltage VDD2 of the receiving end RX and the ground end GND2.

[0015] According to the logic circuit for increasing the common-mode transient immunity of the edge-modulation-demodulation digital isolator provided in the application, a first high-voltage-resistant capacitor C1 and a second high-voltage-resistant capacitor C2 are further connected between the transmitting end TX and the receiving end RX.

[0016] In the application, one end of the first high-voltage-resistant capacitor C1 is connected to the first output end of the transmitting end TX, and the other end of the first high-voltage-resistant capacitor C1 is connected to the first input end of the receiving end RX; one end of the second high-voltage-resistant capacitor C2 is connected to the second output end of the transmitting end TX, and the other end of the second high-voltage-resistant capacitor C2 is connected to the second input end of the receiving end RX.

[0017] According to the logic circuit for increasing the common-mode transient immunity of the edge-modulation-demodulation digital isolator provided in the application, the latch is composed of a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4.

[0018] The gate of the transistor MN1 is connected to the second input end of the receiving end RX, the source of the transistor MN1 is connected to the ground end GND2 of the receiving end RX, and the drain of the transistor MN1 is connected to one end of the fourth resistor R4 and one end of the first resistor R1.

[0019] The gate of the transistor MN2 is connected to the first input end of the receiving end RX, the source of the transistor MN2 is connected to the ground end GND2 of the receiving end RX, and the drain of the transistor MN2 is connected to one end of the third resistor R3 and one end of the second resistor R2.

[0020] The other end of the first resistor R1 is connected to the other end of the second resistor R2, and the connection node of the first resistor R1 and the second resistor R2 is also connected to the input voltage VDD2 of the receiving end RX. The other end of the third resistor R3 is connected to the gate of the transistor MN1, and the other end of the fourth resistor R4 is connected to the gate of the transistor MN2.

[0021] The output signal of the connection node of the drain of the transistor MN1 and the first resistor R1 is INN_AMP, and the output signal of the connection node of the drain of the transistor MN2 and the second resistor R2 is INP_AMP.

[0022] The gate of the transistor MN3 is connected to the output signal INP_AMP, the source of the transistor MN3 is connected to the ground end GND2 of the receiving end RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN4.

[0023] The gate of the transistor MN4 is connected to the output signal INN_AMP, the source of the transistor MN4 is connected to the ground end GND2 of the receiving end RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN3.

[0024] According to the logic circuit for increasing the common mode transient immunity of the edge modulation demodulation digital isolator provided in the application, the transistor MN1, the transistor MN2, the transistor MN3, and the transistor MN4 are all NMOS transistors.

[0025] According to the logic circuit for increasing the common mode transient immunity of the edge modulation demodulation digital isolator provided in the application, the first input end of the full differential amplifier is connected to the output signal INP_AMP, and the second input end of the full differential amplifier is connected to the output signal INN_AMP.

[0026] According to the logic circuit for increasing the common mode transient immunity of the edge modulation demodulation digital isolator provided in the application, the first input end of the envelope comparator is connected with the first output end of the full differential amplifier, and the second input end of the envelope comparator is connected with the second output end of the full differential amplifier.

[0027] According to the logic circuit for increasing the common mode transient immunity of the edge modulation demodulation digital isolator provided in the application, the gate of the transistor MP1 is connected with the output signal INN AMP, the source of the transistor MP1 is connected with the electric node at the connection position of the first resistor R1 and the second resistor R2, and the drain of the transistor MP1 is connected with the ground end GND2 of the receiving end RX.

[0028] The gate of the transistor MN5 is connected with the output signal INP AMP, the source of the transistor MN5 is connected with the ground end GND2 of the receiving end RX, and the drain of the transistor MP1 is connected with the electric node at the connection position of the first resistor R1 and the second resistor R2.

[0029] According to the logic circuit for increasing the common mode transient immunity of the edge modulation demodulation digital isolator provided in the application, the first input end of the logic circuit is connected with the source of the transistor MP1, the second input end of the logic circuit is connected with the output end of the envelope comparator, the third input end of the logic circuit is connected with the source of the transistor MN5, and the output signal of the logic circuit is VOUT.

[0030] The application provides a logic circuit for increasing the common mode transient immunity of an edge modulation demodulation digital isolator, a positive common mode voltage rate of change detection circuit and a negative common mode voltage rate of change detection circuit are added, when the rate of change of the common mode voltage or the common mode current in the logic circuit exceeds the set threshold value, the positive common mode voltage rate of change detection circuit or the negative common mode voltage rate of change detection circuit is turned on, so that the common mode current is discharged, the influence on the input signal of the amplifier of the receiving end RX is reduced, or the influence on the transmitting end TX is reduced, so that the normal signal transmission is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0031] The technical solutions and other beneficial effects of the present application will become apparent from the following detailed description of specific embodiments of the present application, taken in conjunction with the accompanying drawings.

[0032] Figure 1 The structural schematic diagram of the logic circuit for increasing the common mode transient immunity of the edge-modulation digital isolator is provided in the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be apparently and completely described below with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present application.

[0034] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0035] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to the same reference numerals and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides various specific examples of processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0036] The present application will be further described in conjunction with the accompanying drawings and specific embodiments.

[0037] Figure 1The structural diagram of the logic circuit for increasing the common mode transient immunity of the digital isolator with edge modulation demodulation provided in the application.

[0038] As shown in the figure, the logic circuit provided in the application mainly comprises a transmitting end TX and a receiving end RX, the transmitting end TX is connected with the receiving end RX, and the transmitting end TX sends a voltage signal to the receiving end RX. Figure 1

[0039] Among them, the receiving end RX comprises:

[0040] a latch, which latches the voltage signal received by the receiving end RX;

[0041] a full differential amplifier AMP, the input end of which is connected with the output end of the latch, and the full differential amplifier AMP amplifies the voltage signal latched by the latch;

[0042] an envelope comparator COMP, the input end of which is connected with the output end of the full differential amplifier AMP, and the envelope comparator COMP compares the output voltage of the full differential amplifier AMP and outputs a corresponding high-level signal or low-level signal;

[0043] a positive common mode voltage rate of change detection circuit, which is a transistor MP1, the output end of the latch is connected with the transistor MP1, and the transistor MP1 is turned on or turned off by the output voltage signal of the latch;

[0044] a negative common mode voltage rate of change detection circuit, which is a transistor MN5, the output end of the latch is connected with the transistor MN5, and the transistor MN5 is turned on or turned off by the output voltage signal of the latch;

[0045] a logic circuit, the input end of which is connected with the output end of the envelope comparator COMP, the positive common mode voltage rate of change detection circuit and the negative common mode voltage rate of change detection circuit, and the logic circuit compares the output signals of the output end of the envelope comparator COMP, the positive common mode voltage rate of change detection circuit and the negative common mode voltage rate of change detection circuit, and outputs a logic processing result (VOUT).

[0046] ​The input voltage VDD1 of the transmitting end TX and the ground end GND1 and the input voltage VDD2 of the receiving end RX and the ground end GND2 are not the same. That is, the transmitting end TX belongs to the VDD1-GND1 voltage domain, and the receiving end RX belongs to the VDD2-GND2 voltage domain.

[0047] When a higher common-mode voltage rate of change or a common-mode current rate of change occurs in the logic circuit, the voltage of the ground end GND1 of the transmitting end TX suddenly rises relative to the voltage of the ground end GND2 of the receiving end RX, that is, a positive common-mode voltage rate of change is generated; or the voltage of the ground end GND1 of the transmitting end TX suddenly falls relative to the voltage of the ground end GND2 of the receiving end RX, that is, a negative common-mode voltage rate of change is generated; because the response speed of the positive common-mode voltage rate of change detection circuit and the negative common-mode voltage rate of change detection circuit is much higher than the response speed of the modulation and demodulation main path, the output signal of the positive common-mode voltage rate of change detection circuit or the negative common-mode voltage rate of change detection circuit acts first, thereby preventing the output of the logic circuit from changing and maintaining the output (VOUT) of the logic circuit unchanged.

[0048] In the present example, the transistor MP1 in the positive common-mode voltage rate of change detection circuit is a PMOS transistor, and the transistor MN5 in the negative common-mode voltage rate of change detection circuit is an NMOS transistor.

[0049] As shown in Figure 1 The first high-voltage-resistant capacitor C1 and the second high-voltage-resistant capacitor C2 are further connected between the transmitting end TX and the receiving end RX; one end of the first high-voltage-resistant capacitor C1 is connected to the first output end of the transmitting end TX, and the other end of the first high-voltage-resistant capacitor C1 is connected to the first input end of the receiving end RX; one end of the second high-voltage-resistant capacitor C2 is connected to the second output end of the transmitting end TX, and the other end of the second high-voltage-resistant capacitor C2 is connected to the second input end of the receiving end RX. The voltage difference between the ground end GND1 of the transmitting end TX and the ground end GND2 of the receiving end RX is mainly applied to the first high-voltage-resistant capacitor C1 and the second high-voltage-resistant capacitor C2.

[0050] The latch is composed of a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0051] The gate of the transistor MN1 is connected to the second input terminal of the receiving end RX, i.e. to the second high-voltage-resistant capacitor C2, the source of the transistor MN1 is connected to the ground terminal GND2 of the receiving end RX, and the drain of the transistor MN1 is connected to one end of the fourth resistor R4 and one end of the first resistor R1.

[0052] The gate of the transistor MN2 is connected to the first input terminal of the receiving end RX, i.e. to the first high-voltage-resistant capacitor C1, the source of the transistor MN2 is connected to the ground terminal GND2 of the receiving end RX, and the drain of the transistor MN2 is connected to one end of the third resistor R3 and one end of the second resistor R2.

[0053] The other end of the first resistor R1 is connected to the other end of the second resistor R2, and the node at which the first resistor R1 and the second resistor R2 are connected is also connected to the input voltage VDD2 of the receiving end RX. The other end of the third resistor R3 is connected to the gate of the transistor MN1, and the other end of the fourth resistor R4 is connected to the gate of the transistor MN2.

[0054] The output signal of the node at which the drain of the transistor MN1 and the first resistor R1 are connected is INN_AMP, and the output signal of the node at which the drain of the transistor MN2 and the second resistor R2 are connected is INP_AMP.

[0055] The gate of the transistor MN3 is connected to the output signal INP_AMP, the source of the transistor MN3 is connected to the ground terminal GND2 of the receiving end RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN4.

[0056] The gate of the transistor MN4 is connected to the output signal INN_AMP, the source of the transistor MN4 is connected to the ground terminal GND2 of the receiving end RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN3.

[0057] In this embodiment, the transistor MN1, the transistor MN2, the transistor MN3 and the transistor MN4 are all NMOS transistors.

[0058] In this embodiment, the transistor MN1, the transistor MN2, the transistor MN3 and the transistor MN4 are all NMOS transistors.

[0059] The first input end INP of the full differential amplifier AMP is connected with the output signal INP AMP, and the second input end INN of the full differential amplifier AMP is connected with the output signal INN AMP.

[0060] The first input end INP of the envelope comparator COMP is connected with the first output end OUT1 of the full differential amplifier AMP, and the second input end INN of the envelope comparator COMP is connected with the second output end OUT2 of the full differential amplifier AMP.

[0061] In the positive common-mode voltage rate of change detection circuit, the gate of the transistor MP1 is connected with the output signal INN AMP, the source of the transistor MP1 is connected with the electric node at the connection position of the first resistor R1 and the second resistor R2, and the drain of the transistor MP1 is connected with the ground end GND2 of the receiving end RX.

[0062] In the negative common-mode voltage rate of change detection circuit, the gate of the transistor MN5 is connected with the output signal INP AMP, the source of the transistor MN5 is connected with the ground end GND2 of the receiving end RX, and the drain of the transistor MP1 is connected with the electric node at the connection position of the first resistor R1 and the second resistor R2.

[0063] Wherein, the current flowing through the source of the transistor MP1 constitutes a current source I3, and the current flowing through the source of the transistor MN5 constitutes a current source I4; the current source I3 and the transistor MP1 jointly constitute the positive common-mode voltage rate of change detection circuit, and the current source I4 and the transistor MN5 jointly constitute the negative common-mode voltage rate of change detection circuit.

[0064] The first input end A1 of the logic circuit is connected with the source of the transistor MP1, the second input end A2 of the logic circuit is connected with the output end COMP OUT of the envelope comparator COMP, and the third input end A3 of the logic circuit is connected with the source of the transistor MN5; and the output signal of the logic circuit is VOUT.

[0065] The working principle of the logic circuit provided in the embodiment is as follows:

[0066] When there is no high common-mode voltage rate of change or common-mode current rate of change in the circuit, the transistor MP1 is in the off state, and the positive common-mode voltage rate of change detection circuit, which is composed of the current source I3 and the transistor MP1, outputs a high level, and does not affect the normal modem function of the logic circuit. The transistor MN5 is in the off state, and the negative common-mode voltage rate of change detection circuit, which is composed of the current source I4 and the transistor MN5, outputs a low level, and does not affect the normal modem function of the logic circuit.

[0067] When the voltage of the ground GND1 of the transmitting end TX suddenly rises relative to the voltage of the ground GND2 of the receiving end RX, that is, a positive common-mode voltage change occurs, the common-mode current flows through the first high-voltage-resistant capacitor C1 and the second high-voltage-resistant capacitor C2, and is filled into the receiving end RX from the transmitting end TX, so that the voltages of the output signal INP AMP and the output signal INN AMP simultaneously rise. When the common-mode rate of change exceeds the preset value, the transistor MP1 is turned on, the output of the current source I3 and the transistor MP1 changes from the original high level to the low level, thereby preventing the output change of the logic circuit caused by the output change of the main path of the full differential amplifier AMP and the envelope comparator COMP, so that the output (VOUT) of the logic circuit is maintained unchanged.

[0068] When there is no positive common-mode voltage change or the positive common-mode voltage change is small and does not exceed the preset value, the transistor MP1 is in the off state, and the positive common-mode voltage rate of change detection circuit does not affect the normal modem function of the logic circuit.

[0069] During the positive common-mode voltage change, the negative common-mode voltage rate of change detection circuit composed of the current source I4 and the transistor MN5 is in the off state, and the negative common-mode voltage rate of change detection circuit does not affect the normal modem function of the logic circuit.

[0070] When the voltage of the ground GND1 of the transmitting end TX suddenly decreases relative to the voltage of the ground GND2 of the receiving end RX, i.e. a negative common-mode voltage change occurs, the common-mode current flows from the receiving end RX to the transmitting end TX through the first high-voltage-resistant capacitor C1 and the second high-voltage-resistant capacitor C2, and the voltages of the output signal INP AMP and the output signal INN AMP decrease simultaneously. When the common-mode change rate exceeds a preset value, the transistor MN5 is turned on, the output of the current source I4 and the transistor MN5 changes from the original low level to high level, thereby preventing the output change of the logic circuit caused by the output change of the main path of the full differential amplifier AMP and the envelope comparator COMP, so that the output (VOUT) of the logic circuit is maintained unchanged.

[0071] When there is no negative common-mode voltage change or the negative common-mode voltage change is small and does not exceed the preset value, the transistor MN5 is in an off state, and the negative common-mode voltage change rate detection circuit does not affect the normal modulation and demodulation function of the logic circuit.

[0072] During the negative common-mode voltage change, the positive common-mode voltage change rate detection circuit composed of the current source I3 and the transistor MP1 is in an off state, and the positive common-mode voltage change rate detection circuit does not affect the normal modulation and demodulation function of the logic circuit.

[0073] The application provides a logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation, which increases a set of positive common-mode voltage change rate detection circuits and negative common-mode voltage change rate detection circuits. When the change rate of the common-mode voltage or common-mode current in the logic circuit exceeds a set threshold, the positive common-mode voltage change rate detection circuit or the negative common-mode voltage change rate detection circuit is turned on, thereby discharging the common-mode current, reducing the influence on the input signal of the amplifier of the receiving end RX or the influence on the de-driver of the transmitting end TX, so as to ensure normal signal transmission. Moreover, since the response speed of the positive common-mode voltage change rate detection circuit and the negative common-mode voltage change rate detection circuit is much higher than that of the modulation and demodulation path, during the change of the common-mode voltage or common-mode current in the circuit, the output signal of the positive common-mode voltage change rate detection circuit or the negative common-mode voltage change rate detection circuit acts first, thereby preventing the output of the logic circuit from changing and maintaining the output (VOUT) of the logic circuit unchanged, effectively improving the common-mode transient immunity of the digital isolator.

[0074] Although the preferred embodiments of the present application have been described, those skilled in the art who obtain the basic inventive concept can make further changes and modifications to the embodiments. Therefore, the appended claims are intended to cover the preferred embodiments and all changes and modifications falling within the scope of the present application. Finally, it should be noted that in this document, relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the recited element.

[0075] The logic circuit for increasing the common mode transient immunity of the digital isolator with edge modulation demodulation is described in detail above. The principles and implementation of the present application are described using specific examples. The above description of the embodiments is intended to help understand the technical solutions of the present application and its core idea. Those skilled in the art should understand that the technical solutions described in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and such modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation, characterized in that, The logic circuit includes a transmitter TX and a receiver RX, the transmitter TX and the receiver RX are connected, and the transmitter TX sends a voltage signal to the receiver RX. The receiving end RX includes: A latch, wherein the latch latches the voltage signal received by the receiving end RX; A fully differential amplifier, the input of which is connected to the output of the latch, amplifies the voltage signal latched by the latch. An envelope comparator is provided, the input of which is connected to the output of the fully differential amplifier. The envelope comparator compares the output voltage of the fully differential amplifier and outputs a corresponding high-level signal or low-level signal. A forward common-mode voltage change rate detection circuit, wherein the forward common-mode voltage change rate detection circuit is a transistor MP1, the transistor MP1 is connected to the output terminal of the latch, and the transistor MP1 is turned on or off by the output voltage signal of the latch; A negative common-mode voltage change rate detection circuit, wherein the negative common-mode voltage change rate detection circuit is a transistor MN5, the transistor MN5 is connected to the output terminal of the latch, and the transistor MN5 is turned on or off by the output voltage signal of the latch; A logic circuit is provided, the input of which is connected to the output of the envelope comparator, the positive common-mode voltage change rate detection circuit, and the negative common-mode voltage change rate detection circuit. The logic circuit compares the output signal of the envelope comparator, the output signal of the positive common-mode voltage change rate detection circuit, and the output signal of the negative common-mode voltage change rate detection circuit, and outputs the logic processing result.

2. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation as described in claim 1, characterized in that, The transistor MP1 is a PMOS transistor, and the transistor MN5 is an NMOS transistor.

3. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation as described in claim 1, characterized in that, The input voltage VDD1 of the transmitting end TX is different from the ground terminal GND1, and the input voltage VDD2 of the receiving end RX is different from the ground terminal GND2.

4. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation as described in claim 1, characterized in that, A first high-voltage capacitor C1 and a second high-voltage capacitor C2 are also connected between the transmitter TX and the receiver RX. Wherein, one end of the first high-voltage capacitor C1 is connected to the first output terminal of the transmitter TX, and the other end of the first high-voltage capacitor C1 is connected to the first input terminal of the receiver RX; one end of the second high-voltage capacitor C2 is connected to the second output terminal of the transmitter TX, and the other end of the second high-voltage capacitor C2 is connected to the second input terminal of the receiver RX.

5. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation according to claim 4, characterized in that, The latch consists of transistors MN1, MN2, MN3, and MN4, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The gate of transistor MN1 is connected to the second input terminal of the receiver RX, the source of transistor MN1 is connected to the ground terminal GND2 of the receiver RX, and the drain of transistor MN1 is connected to one end of the fourth resistor R4 and one end of the first resistor R1. The gate of transistor MN2 is connected to the first input terminal of receiver RX, the source of transistor MN2 is connected to the ground terminal GND2 of receiver RX, and the drain of transistor MN2 is connected to one end of the third resistor R3 and one end of the second resistor R2. The other end of the first resistor R1 is connected to the other end of the second resistor R2. The electrical node at the connection between the first resistor R1 and the second resistor R2 is also connected to the input voltage VDD2 of the receiving terminal RX. The other end of the third resistor R3 is connected to the gate of the transistor MN1. The other end of the fourth resistor R4 is connected to the gate of the transistor MN2. The output signal of the connection node between the drain of transistor MN1 and the first resistor R1 is INN_AMP, and the output signal of the connection node between the drain of transistor MN2 and the second resistor R2 is INP_AMP. The gate of transistor MN3 is connected to the output signal INP_AMP, the source of transistor MN3 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of transistor MN3 is connected to the gate of transistor MN4. The gate of transistor MN4 is connected to the output signal INN_AMP, the source of transistor MN4 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of transistor MN3 is connected to the gate of transistor MN3.

6. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation according to claim 5, characterized in that, The transistors MN1, MN2, MN3 and MN4 are all NMOS transistors.

7. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation as described in claim 5, characterized in that, The first input terminal of the fully differential amplifier is connected to the output signal INP_AMP, and the second input terminal of the fully differential amplifier is connected to the output signal INN_AMP.

8. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation according to claim 7, characterized in that, The first input terminal of the envelope comparator is connected to the first output terminal of the fully differential amplifier, and the second input terminal of the envelope comparator is connected to the second output terminal of the fully differential amplifier.

9. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation according to claim 8, characterized in that, The gate of transistor MP1 is connected to the output signal INN_AMP, the source of transistor MP1 is connected to the electrical node at the connection of the first resistor R1 and the second resistor R2, and the drain of transistor MP1 is connected to the ground terminal GND2 of the receiving terminal RX. The gate of transistor MN5 is connected to the output signal INP_AMP, the source of transistor MN5 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of transistor MP1 is connected to the electrical node at the connection of the first resistor R1 and the second resistor R2.

10. The logic circuit for increasing the common-mode transient immunity of a digital isolator with edge modulation and demodulation according to claim 9, characterized in that, The first input terminal of the logic circuit is connected to the source of the transistor MP1, the second input terminal of the logic circuit is connected to the output terminal of the envelope comparator, and the third input terminal of the logic circuit is connected to the source of the transistor MN5. The output signal of the logic circuit is VOUT.

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