Wafer structure and power device
By designing vertically arranged trenches on the back of the wafer and filling them with material, the wafer warpage problem caused by deep trench process was solved, improving the yield and performance of the device.
Patent Information
- Application Number
- CN202423205178.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2034-12-25
AI Technical Summary
In the fabrication of shielded gate power devices, insulated gate bipolar transistors, and superjunction power devices, deep trench processes cause wafer warping, affecting photolithography accuracy and causing breakage.
The method involves designing a first and second trench arranged vertically on the back of the wafer, and filling the trenches with silicon dioxide or metal materials to form a stable foundation, thereby solving the wafer warping problem.
This improved the product yield and performance of the device, reduced internal resistance, and enhanced wafer stability.
Smart Images
Figure CN223666686U_ABST
Abstract
Description
Technical Field
[0012] , ,
[0001] This application relates to the technical field of power semiconductor devices, and particularly to a wafer structure and a power device. Background Art
[0002] In the fabrication processes of devices such as shield gate power devices, insulated gate bipolar transistors, and super junction power devices, deep trench processes are used. During the manufacturing process of the above devices with deep trench processes, due to the effect of the deep trenches, the wafer will be severely warped. The existence of warping will change the shape of the wafer, resulting in poor lithography accuracy during lithography, and the lithography machine cannot achieve good adsorption of the wafer during the lithography operation, so lithography cannot be performed; at the same time, the existence of warping will cause the wafer to generate large internal stresses, making it easy for the wafer to break during the transfer process or the dicing process. Therefore, how to solve the wafer warping caused by the preparation of the deep trench structure on the front side of the wafer has become an urgent problem to be solved. Summary of the Utility Model
[0003] This application provides a wafer structure and a power device, which can solve the problem of wafer warping caused by the preparation of the deep trench structure on the front side of the wafer.
[0004] To achieve the above object, this application adopts the following technical solutions:
[0005] In the first aspect of the embodiments of this application, a wafer structure is provided, and the wafer structure includes:
[0006] A substrate, the substrate includes opposite first and second surfaces;
[0007] The first surface includes a plurality of channels, the second surface includes a plurality of trenches, and the trenches include a first filler;
[0008] The trenches include first trenches and second trenches, and the opening cross-section of the first trenches is perpendicular to the opening cross-section of the second trenches;
[0009] The sum of the areas of the opening cross-sections of the first trenches is equal to the sum of the areas of the opening cross-sections of the second trenches, and the first trenches and the second trenches have the same depth.
[0010] As a possible implementation, the opening cross-section of the first trenches and the opening cross-section of the second trenches are orthogonally arranged.
[0011] As a possible implementation, the opening cross-section of the first trenches and the opening cross-section of the second trenches are arranged in a "pin" shape or an "E" shape.
[0012] As a possible implementation, the channels include an oxide layer.
[0013] As a possible implementation, the oxide layer is silicon dioxide, and the first filler is silicon dioxide or a metal material.
[0014] As a possible implementation, the depth of the trench is 2 - 5 μm.
[0015] As a possible implementation, the opening width of the trench is 0.5 - 1 μm.
[0016] In a second aspect of the embodiments of the present application, a power device is provided, and the power device includes the wafer structure in the first aspect of the embodiments of the present application.
[0017] As a possible implementation, the power device further includes: a gate region and a source region, and the gate region and the source region are formed on the first surface of the wafer structure.
[0018] As a possible implementation, the power device further includes: a drain, and the drain is formed on the second surface of the wafer structure.
[0019] The beneficial effects brought by the technical solutions provided in the embodiments of the present application at least include:
[0020] The embodiments of the present application provide a wafer structure, which includes: a substrate, the substrate includes opposite first and second surfaces. Among them, the first surface includes a plurality of channels, the second surface includes a plurality of trenches, the trenches include a first filler, the trenches include a first trench and a second trench, the opening cross-section of the first trench is perpendicular to the opening cross-section of the second trench, the sum of the areas of the opening cross-sections of the first trench is equal to the sum of the areas of the opening cross-sections of the second trench, and the depths of the first trench and the second trench are the same. The wafer structure provided in the embodiments of the present application can form a stable foundation by opening the first trench and the second trench with the same opening cross-section area on the back of the wafer and filling the trenches, thereby solving the problem of wafer warping caused by preparing a deep trench structure on the front of the wafer. Further, the product yield and product performance of the device can be improved. Description of the Drawings
[0021] Figure 1 It is a schematic diagram of the orthogonal arrangement of the opening cross-section of the first trench and the opening cross-section of the second trench provided in the embodiments of the present application;
[0022] Figure 2 It is a schematic diagram of the "pin" - shaped arrangement of the opening cross-section of the first trench and the opening cross-section of the second trench provided in the embodiments of the present application;
[0023] Figure 3This is a schematic diagram showing that the opening cross-sections of the first trench and the second trench are arranged in an "E" shape, according to an embodiment of this application. Detailed Implementation
[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0025] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0026] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.
[0027] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0028] This application provides a wafer structure comprising: a substrate, the substrate including opposing first and second surfaces;
[0029] The first surface includes a plurality of channels, and the second surface includes a plurality of grooves, wherein the grooves include a first filler.
[0030] The trench includes a first trench and a second trench, wherein the opening cross-section of the first trench is perpendicular to the opening cross-section of the second trench;
[0031] The sum of the areas of the opening cross-sections of the first trenches is equal to the sum of the areas of the opening cross-sections of the second trenches, and the first trenches and the second trenches have the same depth.
[0032] Among them, the substrate serves as the carrier of the power device and mainly plays a supporting role. The material of the substrate can be a silicon substrate, a germanium substrate, a germanium-silicon substrate, etc. In this embodiment, the material of the substrate is preferably a silicon substrate, and silicon is the most common, inexpensive, and stable semiconductor material.
[0033] The depth of the trenches can be 2 - 5 μm, and the opening width of the trenches is 0.5 - 1 μm.
[0034] It can be understood that the channel and the trench are only used to distinguish the corresponding positional relationship, and the preparation methods of the channel and the trench can be the same, and both can be obtained by etching the substrate.
[0035] The substrate has opposite first and second surfaces. Among them, the first surface can be understood as the front side of the substrate, and the second surface can be understood as the back side of the substrate. The first surface includes multiple channels, and the gate region and the source region of the power device are formed on the first surface. The drain of the power device is formed on the second surface of the substrate.
[0036] Optionally, the present application provides a schematic diagram of the arrangement of the first trenches and the second trenches on the second surface of a substrate. As Figure 1 shown, the opening cross-sections of the first trenches and the opening cross-sections of the second trenches are arranged orthogonally.
[0037] In the specific preparation process, multiple first trenches and multiple second trenches can be etched according to the orthogonal arrangement. The sum of the areas of the opening cross-sections of the multiple first trenches formed by this orthogonal arrangement is equal to the sum of the areas of the opening cross-sections of the multiple second trenches.
[0038] Optionally, the present application also provides a schematic diagram of the arrangement of the first trenches and the second trenches on the second surface of the substrate. As Figure 2 shown, a schematic diagram of the "pin" - shaped arrangement of the opening cross-sections of the first trenches and the opening cross-sections of the second trenches, as Figure 3 shown, the opening cross-sections of the first trenches and the opening cross-sections of the second trenches are arranged in an "E" - shaped pattern.
[0039] Whether it is the orthogonal arrangement, the "pin" - shaped arrangement, or the "E" - shaped arrangement, it only needs that the sum of the areas of the opening cross-sections of the multiple first trenches is equal to the sum of the areas of the opening cross-sections of the multiple second trenches, and by filling in the trenches, a stable foundation can be formed, thereby solving the problem of wafer warping caused by the preparation of deep trench structures on the front side of the wafer. Further, the product yield and product performance of the device can be improved.
[0040] Optionally, the trench in the first surface of the substrate includes an oxide layer, and the trench in the second surface of the substrate includes a first filler, wherein if the oxide layer is silicon dioxide, the first filler is silicon dioxide or a metallic material.
[0041] It is understood that the channel filling in the first surface of the substrate with silicon dioxide is generally used for the fabrication of power devices. Of course, depending on the performance of different power devices, the channel in the first surface of the substrate may not include a filler, or may be a first filler other than silicon dioxide. This application does not specifically limit this.
[0042] The trenches in the second surface of the substrate include a first filler, which may be silicon dioxide or a metal.
[0043] It should be noted that filling the trenches on the second surface of the substrate with silicon dioxide or metal is primarily to counteract the stress exerted on the substrate by the trenches on the first surface, as well as the stress exerted on the substrate by the oxide layer formed in the trenches. Simultaneously, it can form a stable back-side foundation structure, thereby solving the wafer warpage problem caused by deep trench structures fabricated on the front side of the wafer. Furthermore, if the trenches on the second surface are filled with metal, the drain of the power device is formed on the filled metal, allowing the drain of the power device to connect with the filled metal. This increases the contact area of the power device, thereby reducing its internal resistance.
[0044] This application provides a wafer structure comprising a substrate, the substrate including a first surface and a second surface opposite to each other, wherein the first surface includes a plurality of channels, and the second surface includes a plurality of trenches, the trenches including a first filler, the trenches including a first trench and a second trench, the opening cross-section of the first trench being perpendicular to the opening cross-section of the second trench, the sum of the areas of the opening cross-sections of the first trench being equal to the sum of the areas of the opening cross-sections of the second trench, and the first trench and the second trench having the same depth. The wafer structure provided in this application, by using first and second trenches with the same opening cross-sectional area on the back side of the wafer and filling the trenches, can form a stable foundation, thereby solving the problem of wafer warpage caused by deep trench structures fabricated on the front side of the wafer. Furthermore, it can improve the product yield and product performance of the device.
[0045] In addition, this application embodiment also provides a power device, which includes the wafer structure provided in this application embodiment.
[0046] The power device further includes a gate region and a source region, the gate region and the source region being formed on a first surface of the substrate in the wafer structure.
[0047] The power device further includes a drain electrode formed on the second surface of the substrate in the wafer structure.
[0048] Specifically, a conductive layer can be formed on the second surface of the substrate in the wafer structure, and this conductive layer serves as the drain of the power device. The first filler in the trench is connected to the conductive layer.
[0049] It should be noted that the method for forming the gate region and the source region on the first surface of the substrate, as well as the fabrication of other structures on the first surface of the substrate, can be determined according to the different power devices to be fabricated, and the embodiments of this application do not impose specific limitations on this.
[0050] The power device provided in this application embodiment forms a gate region and a source region on the first surface of the substrate in the wafer structure provided in this application embodiment, and forms a drain on the second surface of the substrate in the wafer structure. The power device prepared in this way solves the problem of wafer warping caused by the preparation of a deep trench structure on the front side of the wafer, thereby improving the product yield and product performance of the device.
[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
[0052] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the foregoing claims, any of the claimed embodiments can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.
Claims
1. A wafer structure, characterized in that, The wafer structure includes: A substrate, the substrate including opposite first and second surfaces; The first surface includes a plurality of channels, the second surface includes a plurality of grooves, and the grooves include a first filler; The grooves include a first groove and a second groove, and the opening cross-section of the first groove is perpendicular to the opening cross-section of the second groove; The sum of the areas of the opening cross-sections of the first grooves is equal to the sum of the areas of the opening cross-sections of the second grooves, and the first grooves and the second grooves have the same depth.
2. The wafer structure according to claim 1, characterized in that, The opening cross-sections of the first grooves and the opening cross-sections of the second grooves are orthogonally arranged.
3. The wafer structure according to claim 1, characterized in that, The opening cross-sections of the first grooves and the opening cross-sections of the second grooves are arranged in a "pin" shape or an "E" shape.
4. The wafer structure according to claim 1, characterized in that, The channels include an oxide layer.
5. The wafer structure according to claim 4, characterized in that, The oxide layer is silicon dioxide, and the first filler is silicon dioxide or a metal material.
6. The wafer structure according to claim 1, characterized in that, The depth of the grooves is 2 to 5 μm.
7. The wafer structure according to claim 1, characterized in that, The opening width of the grooves is 0.5 to 1 μm.
8. A power device, characterized in that, The power device includes the wafer structure according to any one of claims 1 to 7.
9. The power device according to claim 8, characterized in that, The power device further includes: a gate region and a source region, the gate region and the source region being formed on the first surface of the substrate in the wafer structure.
10. The power device according to claim 8, characterized in that, The power device further includes: a drain, the drain being formed on the second surface of the substrate in the wafer structure.