Packaging structure of GaN chip
By using a dual DBC heat dissipation structure and copper pillar connection, the problems of easy cracking of bonding wires and poor thermal conductivity in GaN chip packaging are solved, achieving smaller size, thinner weight and more efficient heat dissipation.
Patent Information
- Application Number
- CN202423183393.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-23
AI Technical Summary
Traditional GaN chip packaging structures suffer from problems such as easy cracking or detachment of bonding wire solder joints, long heat conduction paths, and poor heat conduction under high temperature and heat conditions, making it difficult to simultaneously meet the requirements of miniaturization and excellent heat dissipation performance.
It adopts a dual DBC heat dissipation structure, which replaces the traditional wire bonding by connecting the protrusion and the copper layer groove. Combined with the connection of the copper pillar and the frame pin, it forms a stable electrical connection and heat conduction path. The silver sintering process is used to improve reliability and heat dissipation performance.
It effectively avoids cracks and detachment of bonding wire solder joints, shortens the heat conduction path, improves the reliability and heat dissipation capacity of chip packaging, and achieves a smaller and thinner packaging structure.
Smart Images
Figure CN223680103U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a semiconductor packaging technical field, concretely relates to a packaging structure of GaN chip. BACKGROUND
[0002] With the continuous development of semiconductor technology, the third generation semiconductor chip gallium nitride (GaN) chip has been widely used in the electronic field due to its excellent performance, and the GaN chip is developing towards high voltage and high power in order to be applied in more extensive fields, but the problem of high temperature and high heat production is also more serious. Therefore, the GaN chip faces many challenges in the packaging process, especially the simultaneous satisfaction of packaging miniaturization and excellent heat dissipation performance. Although the volume thermal conductivity is not obviously lower than that of silicon, the higher current density is limited in a small area around the heterojunction. Although the traditional silicon packaging can be used for packaging wide band gap (WBG) devices, for the GaN structure of lateral design, most of the cooling advantages have been lost. From the perspective of thermal management, this makes the problem more challenging, and higher current density requires more stringent packaging solutions. The traditional packaging structure adopts the way of wire bonding, which has the problems of crack or falling off of the bonding wire welding point, and also has the disadvantages of long heat conduction path and poor heat conduction capacity. SUMMARY
[0003] The utility model aims at overcoming the shortcomings and deficiencies of prior art, and provides a packaging structure of GaN chip.
[0004] The utility model adopts the technical scheme as follows: a packaging structure of GaN chip, including GaN chip, the upper and lower end surfaces of GaN chip are connected with first DBC heat dissipation structure and second DBC heat dissipation structure respectively, the second DBC heat dissipation structure includes the first ceramic layer in the middle layer, the first copper layer is connected to the upper end of first ceramic layer, the second copper layer is connected to the lower end of first ceramic layer,
[0005] The lower end surface of GaN chip is provided with a plurality of connecting convex parts, the first copper layer includes a plurality of copper leads, the copper lead has a contact point matching end and a pin connecting end forming electrical connection with the frame pin, and the contact point matching end has a copper layer groove abutting with the connecting convex part.
[0006] Preferably, the first ceramic layer and the second copper layer are axially penetrated by a first through hole at the position corresponding to the pin connecting end, a copper column is arranged in the first through hole and connected with the pin connecting end, and the bottom of the copper column is connected with the frame pin.
[0007] Preferably, the frame pin includes a first pin in the shape of a right angle bend and a second copper heat dissipation sheet in the shape of a sheet.
[0008] Preferably, the second copper heat sink is located at the corresponding position of the GaN chip and has an area greater than that of the GaN chip.
[0009] Preferably, the connecting protrusions are in the shape of bumps or capsules, and the copper layer grooves are adapted to the shape of the corresponding connecting protrusions.
[0010] Preferably, the housing has a mounting cavity, and the GaN chip, the first DBC heat dissipation structure and the second DBC heat dissipation structure are located in the mounting cavity.
[0011] The bottom of the housing has a lower first through hole in communication with the mounting cavity and adapted to the shape of the copper column, and the lower end of the copper column is connected to the frame pin through the lower first through hole.
[0012] Preferably, the top of the housing is connected with a first copper heat sink.
[0013] Preferably, the copper leads are not in contact with each other to form a first insulation partition, and the first through hole includes a first hole part on the second copper layer, and the size of the first hole part is greater than that of the copper column and does not contact the copper column to form a second insulation partition.
[0014] Preferably, the longer side of the first copper layer and the horizontal boundary of the second copper layer are 0.05mm-0.1mm away from the horizontal boundary of the first ceramic layer.
[0015] Preferably, the thickness of the first copper layer and the second copper layer is 0.0mm-0.0mm, and the thickness of the first ceramic layer is 0.2mm-0.3mm.
[0016] The beneficial effects of the utility model are as follows: the connection mode of the double DBC heat dissipation structure replaces the traditional wire bonding connection mode, the connection protrusions and the copper layer grooves are matched between the lower end surface of the GaN chip and the first copper layer, cracks or falling of the wire bonding welding points are avoided, the shortcomings of long heat conduction path and poor heat conduction capacity are avoided, the reliability of the chip packaging is improved, the heat conduction path of the chip is greatly shortened, the thermal resistance of the chip is reduced, the chip packaging size is smaller and thinner, and thus the heat dissipation capacity is more excellent. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or the prior art description, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings obtained according to these drawings without creative labor still belong to the scope of the utility model.
[0018] Figure 1 It is a three-dimensional structure diagram of the embodiment of the utility model.
[0019] Figure 2 is a bottom view structural diagram of the embodiment of the present application;
[0020] Figure 3 is Figure 2 is a section view at A-A;
[0021] Figure 4 is Figure 2 is a section view at B-B;
[0022] Figure 5 is a matching diagram of the GaN chip and the second DBC heat dissipation structure;
[0023] Figure 6 is a partial exploded view of the GaN chip and the second DBC heat dissipation structure;
[0024] Figure 7 is Figure 4 is a structure enlarged view at C;
[0025] Figure 8 is a top view structural diagram of the first copper layer;
[0026] Figure 9 is a bottom view structural diagram of the GaN chip;
[0027] In the figure, 1, GaN chip; 3, copper column; 5, shell; 7, glue layer; 11, connecting convex part; 21, first ceramic layer; 22, first copper layer; 23, second copper layer; 41, first pin; 42, second copper heat dissipation fin; 51, mounting cavity; 52, first copper heat dissipation fin; 61, second ceramic layer; 62, third copper layer; 64, fourth copper layer; 221, copper lead; 231, first hole part; 2211, copper layer groove; 2212, pin connecting end. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings.
[0029] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same name but different entities or different parameters, and it can be seen that "first" and "second" are only for the convenience of description, and should not be understood as a limitation of the embodiments of the present application, and the subsequent embodiments will not be described one by one.
[0030] The directional and positional terms used in this utility model, such as "up," "down," "front," "back," "left," "right," "inner," "outer," "top," "bottom," and "side," are merely for reference to the accompanying drawings. Therefore, the directional and positional terms used are for the purpose of explaining and understanding this utility model, and not for limiting the scope of protection of this utility model.
[0031] like Figures 1 to 9 As shown in the figure, a GaN chip packaging structure is provided in an embodiment of the present invention. The GaN chip 1 has a first DBC heat dissipation structure and a second DBC heat dissipation structure connected to its upper and lower surfaces, respectively. The second DBC heat dissipation structure includes a first ceramic layer 21 located in the middle layer, a first copper-clad layer 22 connected to the upper end of the first ceramic layer 21, and a second copper-clad layer 23 connected to the lower end of the first ceramic layer 21.
[0032] The lower end face of the GaN chip 1 is provided with a plurality of connection protrusions 11, and the first copper cladding layer 22 includes a plurality of copper leads 221. The copper leads 221 have contact mating ends and pin connection ends 2212 that form an electrical connection with the frame pins. The contact mating ends have copper layer grooves 2211 that abut against the connection protrusions 11.
[0033] This design replaces the traditional wire bonding connection method with a dual DBC heat dissipation structure. The lower end face of the GaN chip and the first copper layer are connected by a connecting protrusion and a copper layer groove, which avoids the disadvantages of wire bonding points such as cracks or detachment, long heat conduction paths and poor heat conduction capacity. At the same time, it improves the reliability of chip packaging, greatly shortens the heat conduction path of the chip, reduces the thermal resistance of the chip, and makes the chip package smaller and thinner, thereby achieving better heat dissipation capabilities.
[0034] In this embodiment, the contact mating method between the connecting protrusion and the copper layer groove is silver sintering process; each copper layer groove and its copper lead trace of the first copper layer and the connecting protrusion on the GaN chip need to be insulated and separated. There is no specific limitation on the insulation separation and its traces. It needs to be specifically set according to the location of the connection points of the source, gate and drain of the GaN chip in the specific design.
[0035] The first ceramic layer 21 and the second copper-clad layer 23 have a first through hole axially passing through them at the position corresponding to the pin connection end 2212. A copper pillar 3 is inserted in the first through hole to form a connection with the pin connection end 2212. The bottom of the copper pillar 3 is connected to the frame pin.
[0036] In the embodiment, the connecting convex part of the GaN chip can be connected to the copper layer groove of the first copper layer through silver sintering process to form a welding point, and the first copper layer is connected to nine pin connection ends through lead wires. First through holes are formed through the first ceramic layer and the second copper layer at the nine pin connection ends, and copper columns are placed in the first through holes. The frame pins are connected to the pin connection ends through the copper columns.
[0037] The frame pin includes a first pin 41 in a right-angle bending shape and a second copper heat dissipation sheet 42 in a sheet shape.
[0038] Through the arrangement, the middle sheet-shaped frame pin is used as a heat dissipation sheet according to the spatial arrangement, and the heat dissipation performance is further improved. In the embodiment, the bending height of the first pin is specifically 0.2-0.3 mm.
[0039] The second copper heat dissipation sheet 42 is located at a corresponding position of the GaN chip 1 and has an area greater than that of the GaN chip 1.
[0040] The connecting convex part 11 is in a bump shape or a capsule shape, and the copper layer groove 2211 is matched in shape with the corresponding connecting convex part 11.
[0041] Through the arrangement, the cooperation of the GaN chip and the first copper layer is more stable, and the heat dissipation is more reliable. The capsule shape refers to a spherical groove at both ends connected through a columnar groove.
[0042] Further comprising a shell 5, the shell 5 has a mounting cavity 51, the GaN chip 1, the first DBC heat dissipation structure, and the second DBC heat dissipation structure are located in the mounting cavity 51,
[0043] The bottom of the shell 5 has a lower first through hole in communication with the mounting cavity 51 and matched in shape with the copper column 3, and the lower end of the copper column 3 penetrates through the lower first through hole and is connected and matched with the frame pin.
[0044] In the embodiment, the shell is specifically a plastic package shell, and the shell includes the first DBC heat dissipation structure, the second DBC heat dissipation structure, and the GaN chip. The frame pin is located outside the plastic package shell.
[0045] The plastic package shell is made of thermosetting material, and the material is not specifically limited. The filling molding process is used to complete the last step of chip packaging, that is, chip plastic packaging.
[0046] The top of the shell 5 is connected with a first copper heat dissipation sheet 52.
[0047] In the embodiment, the first copper heat dissipation sheet is connected to the top of the shell through a glue layer.
[0048] The first insulating division is formed by the non-contact between the copper leads 221, and the first through hole comprises a first hole part 231 on the second copper layer 23, the size of the first hole part 231 is greater than that of the copper column 3 and the first hole part 231 is not in contact with the copper column 3 to form a second insulating division.
[0049] The longer side of the first copper layer 22 and the horizontal boundary of the second copper layer 23 are 0.05mm-0.1mm away from the horizontal boundary of the first ceramic layer 21.
[0050] In the embodiment, the thickness of the first ceramic layer is 0.2mm-0.3mm, the thickness of the first copper layer and the second copper layer is 0.05mm-0.10mm, the area of the first ceramic layer is greater than that of the first copper layer and the second copper layer, and the combination of the first ceramic layer and the first copper layer and the second copper layer is not limited by a specific process.
[0051] The thickness of the first copper layer 22 and the second copper layer 23 is 0.05mm-0.10mm, and the thickness of the first ceramic layer 21 is 0.2mm-0.3mm.
[0052] The first DBC heat dissipation structure comprises a second ceramic layer 61 on the intermediate layer, a third copper layer 62 connected to the upper end of the second ceramic layer 61, and a fourth copper layer 63 connected to the lower end of the second ceramic layer 61, the upper end of the GaN chip 1 is connected with the fourth copper layer 63 through a glue layer 7, the thickness of the glue layer 7 is 0.02mm-0.05mm, the glue layer 7 is a thermosetting material, and the material is not specifically limited, and the bonding process of the glue layer is not specifically limited, and the material or process is selected according to the actual situation.
[0053] The above only discloses the preferred embodiment of the utility model, and of course cannot limit the scope of the utility model, therefore, the equivalent changes made according to the utility model claim still belong to the scope covered by the utility model.
Claims
1. A packaging structure of a GaN chip, comprising a GaN chip (1), characterized in that: The upper and lower end faces of the GaN chip (1) are respectively connected with a first DBC heat dissipation structure and a second DBC heat dissipation structure, the second DBC heat dissipation structure comprises a first ceramic layer (21) located in the middle layer, a first copper clad layer (22) connected to the upper end of the first ceramic layer (21), and a second copper clad layer (23) connected to the lower end of the first ceramic layer (21), The lower end face of the GaN chip (1) is provided with a plurality of connecting protrusions (11), and the first copper clad layer (22) comprises a plurality of copper leads (221), the copper lead (221) has a contact matching end and a pin connecting end (2212) forming an electrical connection with the frame pin, and the contact matching end has a copper layer groove (2211) abuttingly matched with the connecting protrusion (11).
2. The packaging structure of a GaN chip according to claim 1, wherein: The first ceramic layer (21) and the second copper clad layer (23) are axially penetrated by a first through hole corresponding to the position of the pin connecting end (2212), and a copper column (3) is arranged in the first through hole and connected with the pin connecting end (2212), and the bottom of the copper column (3) is connected with the frame pin.
3. The packaging structure of a GaN chip according to claim 2, wherein: The frame pin comprises a first pin (41) in a right angle bending shape and a second copper heat dissipation sheet (42) in a sheet shape.
4. The packaging structure of a GaN chip according to claim 3, wherein: The second copper heat dissipation sheet (42) is located at the corresponding position of the GaN chip (1) and has an area greater than that of the GaN chip (1).
5. The packaging structure of a GaN chip according to claim 1, wherein: The connecting protrusion (11) is in a bump shape or a capsule shape, and the copper layer groove (2211) is matched with the corresponding connecting protrusion (11) in shape.
6. The packaging structure of a GaN chip according to any one of claims 2-5, characterized in that: Further comprising a shell (5) having a mounting cavity (51), the GaN chip (1), the first DBC heat dissipation structure, and the second DBC heat dissipation structure are located in the mounting cavity (51), The bottom of the shell (5) has a lower first through hole communicating with the mounting cavity (51) and matched with the copper column (3) in shape, and the lower end of the copper column (3) passes through the lower first through hole and is connected with the frame pin.
7. The packaging structure of a GaN chip according to claim 6, wherein: The top of the shell (5) is connected with a first copper heat dissipation sheet (52).
8. The packaging structure of a GaN chip according to any one of claims 2-4, wherein: Each copper lead (221) is not in contact with each other to form a first insulation division, and the first through hole comprises a first hole portion (231) located on the second copper clad layer (23), and the size of the first hole portion (231) is greater than that of the copper column (3) and does not contact with the copper column (3) to form a second insulation division.
9. The packaging structure of a GaN chip according to any one of claims 1-5, wherein: The longer side of the first copper clad layer (22) and the horizontal boundary of the second copper clad layer (23) are 0.05mm-0.1mm away from the horizontal boundary of the first ceramic layer (21).
10. The packaging structure of a GaN chip according to any one of claims 1-5, wherein: The thickness of the first copper clad layer (22) and the second copper clad layer (23) is 0.05mm-0.10mm, and the thickness of the first ceramic layer (21) is 0.2mm-0.3mm.