Digital isolation dual-voltage output inverter
By using a digitally isolated dual-voltage output inverter, and utilizing primary and secondary regulation boards, current detection circuits, and voltage circuits, the problem of unstable output voltage in traditional H-bridge inverters has been solved, achieving stable voltage output.
Patent Information
- Application Number
- CN202422849206.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-11-21
AI Technical Summary
The H-bridge inverter output voltage of traditional inverters cannot meet the stable voltage requirements.
The inverter adopts a digitally isolated dual-voltage output inverter. Through the first and second stage adjustment boards, current detection circuit and voltage circuit, the PWM signal output of the two circuit branches is realized to control the first and second stage inverter circuits respectively, and output two or one 120V AC power.
It achieves stable voltage output, capable of simultaneously outputting two 120V AC power sources or one 240V AC power source to meet voltage requirements.
Smart Images
Figure CN223680983U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to the technical field of inverters, in particular to a digital isolated dual-voltage output inverter. BACKGROUND
[0002] An inverter refers to an inverse converter of a rectifier, which is a kind of power electronic converter for converting direct current into alternating current through the opening and closing of a semiconductor power switching device. The existing inverters on the market generally obtain alternating current from a permanent magnet generator, rectify the alternating current through a rectifier circuit to output direct current, and then output the required alternating voltage through an H-bridge inverter. In addition, voltage, current, speed and other detection circuits, protection and control of the inverter are added to form a stable inverter system. The H-bridge inverter output voltage of the traditional inverter cannot meet the stable voltage requirement. Therefore, it is necessary to propose a digital isolated dual-voltage output inverter in view of the defect that the H-bridge inverter output voltage of the traditional inverter cannot meet the stable voltage requirement. CONTENT OF THE INVENTION
[0003] Therefore, it is necessary to propose a digital isolated dual-voltage output inverter in view of the defect that the H-bridge inverter output voltage of the traditional inverter cannot meet the stable voltage requirement.
[0004] The application relates to a digital isolated dual-voltage output inverter, which comprises:
[0005] A first regulating board comprises a first level response board, a first current detection circuit and a first voltage circuit, the first level response board is electrically connected with the first current detection circuit, and the first level response board is electrically connected with the first voltage circuit;
[0006] A second regulating board comprises a second level response board, a second current detection circuit and a second voltage circuit, the second level response board is electrically connected with the second current detection circuit, the second level response board is electrically connected with the second voltage circuit, and the first level response board is electrically connected with the second level response board;
[0007] A first inverter circuit is electrically connected with the first level response board;
[0008] A second inverter circuit is electrically connected with the second level response board.
[0009] Further, the circuit structure of the first inverter circuit is the same as that of the second inverter circuit.
[0010] Further, the first inverter circuit comprises a first PWM chip and a first P-type MOS tube.
[0011] The signal input end of the first PWM chip is electrically connected with the first signal output end of the first level response board.
[0012] The signal output end of the first PWM chip is electrically connected with the gate of the first P-type MOS tube.
[0013] The drain of the first P-type MOS tube is electrically connected with the first input power supply of the digital isolation double-voltage output inverter.
[0014] The source of the first P-type MOS tube is defined as the first output end of the first inverter circuit.
[0015] Further, the first inverter circuit further comprises a second PWM chip and a second P-type MOS tube.
[0016] The signal input end of the second PWM chip is electrically connected with the second signal output end of the first level response board.
[0017] The signal output end of the second PWM chip is electrically connected with the gate of the second P-type MOS tube.
[0018] The drain of the second P-type MOS tube is electrically connected with the source of the first P-type MOS tube.
[0019] The source of the second P-type MOS tube is grounded.
[0020] Further, the first inverter circuit further comprises a first feedback capacitor and a second feedback capacitor.
[0021] The first feedback capacitor is electrically connected between the connection link between the first input power supply end of the second PWM chip and the second input power supply end of the second PWM chip.
[0022] The second feedback capacitor is electrically connected between the connection link between the first feedback capacitor and the second input power supply end of the second PWM chip.
[0023] The connection node between the first feedback capacitor and the second feedback capacitor is grounded.
[0024] Further, the first inverter circuit further comprises a third PWM chip and a third P-type MOS tube.
[0025] The signal input end of the third PWM chip is electrically connected with the third signal output end of the first level response board.
[0026] The signal output end of the third PWM chip is electrically connected with the gate of the third P-type MOS tube.
[0027] The drain of the third P-type MOS tube is electrically connected with a second input power supply of a digital isolation double-voltage output inverter.
[0028] The source of the third P-type MOS tube is defined as a second output end of the primary inverter circuit.
[0029] Further, the primary inverter circuit further comprises a fourth PWM chip and a fourth P-type MOS tube.
[0030] The signal input end of the fourth PWM chip is electrically connected with a fourth signal output end of the primary level response board.
[0031] The signal output end of the fourth PWM chip is electrically connected with the gate of the fourth P-type MOS tube.
[0032] The drain of the fourth P-type MOS tube is electrically connected with the source of the third P-type MOS tube.
[0033] The source of the fourth P-type MOS tube is grounded.
[0034] The first output end of the primary inverter circuit is defined as being connected with a load of the digital isolation double-voltage output inverter between the first output end and the second output end of the primary inverter circuit.
[0035] Further, the circuit structure of the primary voltage circuit is the same as that of the secondary voltage circuit.
[0036] The present application relates to a digital isolation double-voltage output inverter, which realizes PWM signal output of one circuit branch through a primary level response board, a primary current detection circuit and a primary voltage circuit. PWM signal output of another circuit branch is realized through a secondary level response board, a secondary current detection circuit and a secondary voltage circuit. The primary inverter circuit realizes voltage AC output of one input power supply according to the PWM signal of the primary level response board. The secondary inverter circuit realizes voltage AC output of another input power supply according to the PWM signal of the secondary level response board. The primary level response board receives electrical signals of the primary current detection circuit and the primary voltage circuit, and the secondary level response board receives electrical signals of the secondary current detection circuit and the secondary voltage circuit. The primary level response board sends 4-way PWM wave signals to the primary inverter circuit to output 120V AC. The primary level response board sends 4-way PWM wave signals to the secondary inverter circuit to output another 120V AC. BRIEF DESCRIPTION OF DRAWINGS
[0037] Figure 1 A structural connection schematic diagram of a digital isolation double-voltage output inverter is provided for an embodiment of the present application.
[0038] Figure 2This is a schematic diagram of the structure and connection of the first-stage level response board and the first-stage inverter circuit of a digital isolated dual-voltage output inverter provided in an embodiment of this application.
[0039] Figure label:
[0040] 100 - First-level adjustment board; 110 - First-level level response board; 120 - First-level current detection circuit;
[0041] 130 - Primary voltage circuit; 200 - Secondary adjustment board; 210 - Secondary level response board;
[0042] 220 - Second-stage current detection circuit; 230 - Second-stage voltage circuit; 300 - First-stage inverter circuit;
[0043] 310 - First PWM chip; 320 - First P-type MOSFET; 330 - Second PWM chip;
[0044] 340 - Second P-type MOSFET; 350 - First feedback capacitor; 360 - Second feedback capacitor;
[0045] 370 - Third PWM chip; 380 - Third P-type MOSFET; 391 - Fourth PWM chip;
[0046] 392 - Fourth P-type MOSFET; 400 - Second-stage inverter circuit. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0048] This application provides a locking device 100. It should be noted that the locking device 100 provided in this application can be applied to any type of wearable device, such as wristbands, watch straps, handcuffs, etc., and this application does not limit its application to any product.
[0049] like Figure 1 As shown in one embodiment of this application, a digitally isolated dual-voltage output inverter includes a primary regulation board 100, a secondary regulation board 200, a primary inverter circuit 300, and a secondary inverter circuit 400.
[0050] The primary regulating plate 100 includes a primary level response plate 110, a primary current detection circuit 120, and a primary voltage circuit 130. The primary level response plate 110 is electrically connected to the primary current detection circuit 120, and the primary level response plate 110 is electrically connected to the primary voltage circuit 130.
[0051] The secondary adjustment board 200 includes a secondary level response board 210, a secondary current detection circuit 220, and a secondary voltage circuit 230. The secondary level response board 210 is electrically connected to the secondary current detection circuit 220, the secondary level response board 210 is electrically connected to the secondary voltage circuit 230, and the primary level response board 110 is electrically connected to the secondary level response board 210.
[0052] The first-stage inverter circuit 300 is electrically connected to the first-stage level response board 110.
[0053] The secondary inverter circuit 400 is electrically connected to the secondary level response board 210.
[0054] This embodiment relates to a digitally isolated dual-voltage output inverter. A PWM signal output for one circuit branch is achieved through a first-level level response board 110, a first-level current detection circuit 120, and a first-level voltage circuit 130. A PWM signal output for the other circuit branch is achieved through a second-level level response board 210, a second-level current detection circuit 220, and a second-level voltage circuit 230. The first-level inverter circuit 300 outputs AC voltage from one input power source based on the PWM signal from the first-level level response board 110. The second-level inverter circuit 400 outputs AC voltage from another input power source based on the PWM signal from the second-level level response board 210. The first-level level response board 110 receives electrical signals from the first-level current detection circuit 120 and the first-level voltage circuit 130, and the second-level level response board 210 receives electrical signals from the second-level current detection circuit 220 and the second-level voltage circuit 230. The first-level level response board 110 sends four PWM wave signals to the first-level inverter circuit 300, and the first-level inverter circuit 300 outputs 120V AC power. The primary level response board 110 sends four PWM wave signals to the secondary inverter circuit 400, and the secondary inverter circuit 400 outputs another 120V AC power.
[0055] like Figure 1 As shown, in one embodiment of this application, the circuit structure of the first-stage inverter circuit 300 is the same as that of the second-stage inverter circuit 400.
[0056] This embodiment involves a first-stage inverter circuit 300 and a second-stage inverter circuit 400. When the digitally isolated dual-voltage output inverter is powered on, the DC high voltage of M_POW_X on the first-stage level response board 110 and M_POW_Y on the second-stage level response board 210 is stabilized.
[0057] The main microcontroller UC2 of the first-level response board 110 and the slave microcontroller US4 of the second-level response board 210 are powered on synchronously. The main microcontroller sends eight PWM wave signals: O_PWMXL, O_PWMXH, O_PWMYL, and O_PWMYH to the first-level inverter circuit 300. The four signals O_PWMZL, O_PWMZH, O_PWMOL, and O_PWMOH are sent to the second-level inverter circuit 400. The first-level inverter circuit 300 and the second-level inverter circuit 400 output two 120V AC signals.
[0058] This solves the problem that the output voltage of the H-bridge inverter in traditional inverters cannot meet the stable voltage requirements.
[0059] like Figure 2 As shown, in one embodiment of this application, the first-stage inverter circuit 300 includes a first PWM chip 310 and a first P-type MOSFET 320. The signal input terminal of the first PWM chip 310 is electrically connected to the first signal output terminal of the first-stage level response board 110. The signal output terminal of the first PWM chip 310 is electrically connected to the gate of the first P-type MOSFET 320. The drain of the first P-type MOSFET 320 is electrically connected to the first input power supply of the digitally isolated dual-voltage output inverter. The source of the first P-type MOSFET 320 is defined as the first output terminal of the first-stage inverter circuit 300.
[0060] The first-stage inverter circuit 300 further includes a second PWM chip 330 and a second P-type MOSFET 340. The signal input terminal of the second PWM chip 330 is electrically connected to the second signal output terminal of the first-stage level response board 110. The signal output terminal of the second PWM chip 330 is electrically connected to the gate of the second P-type MOSFET 340. The drain of the second P-type MOSFET 340 is electrically connected to the source of the first P-type MOSFET 320. The source of the second P-type MOSFET 340 is grounded.
[0061] The first-stage inverter circuit 300 further includes a first feedback capacitor 350 and a second feedback capacitor 360. The first feedback capacitor 350 is electrically connected between the first input power terminal and the second input power terminal of the second PWM chip 330. The second feedback capacitor 360 is electrically connected between the first feedback capacitor 350 and the second input power terminal of the second PWM chip 330. The connection node between the first feedback capacitor 350 and the second feedback capacitor 360 is grounded.
[0062] The embodiment relates to a primary inverter circuit 300. A main path single-chip microcomputer of a primary level response board 110 sends four-way PWM wave signals to the primary inverter circuit 300, cooperates with a power signal, drives a chip to work, and inverts 120V alternating current.
[0063] In an embodiment of the application, the primary inverter circuit 300 further comprises a third PWM chip 370 and a third P-type MOS tube 380. A signal input end of the third PWM chip 370 is electrically connected with a third signal output end of the primary level response board 110. A signal output end of the third PWM chip 370 is electrically connected with a gate of the third P-type MOS tube 380. A drain of the third P-type MOS tube 380 is electrically connected with a second input power supply of a digital isolation double-voltage output inverter. A source of the third P-type MOS tube 380 is defined as a second output end of the primary inverter circuit 300.
[0064] The primary inverter circuit 300 further comprises a fourth PWM chip 391 and a fourth P-type MOS tube 392. A signal input end of the fourth PWM chip 391 is electrically connected with a fourth signal output end of the primary level response board 110. A signal output end of the fourth PWM chip 391 is electrically connected with a gate of the fourth P-type MOS tube 392. A drain of the fourth P-type MOS tube 392 is electrically connected with a source of the third P-type MOS tube 380. A source of the fourth P-type MOS tube 392 is grounded.
[0065] The embodiment relates to a secondary inverter circuit 400. A main path single-chip microcomputer of a primary level response board 110 sends four-way PWM wave signals to the secondary inverter circuit 400, cooperates with a power signal, drives a chip to work, and inverts 120V alternating current.
[0066] As shown in the figure, Figure 1 In an embodiment of the application, a load of the digital isolation double-voltage output inverter is connected between the first output end of the primary inverter circuit 300 and the second output end of the primary inverter circuit 300.
[0067] The embodiment relates to the first output end of the primary inverter circuit 300 and the second output end of the primary inverter circuit 300. A main path single-chip microcomputer of a primary level response board 110 simultaneously controls two driving inverter circuits of the primary inverter circuit 300 and the secondary inverter circuit 400, uses a secondary level response board 210 to synchronously give a signal detected by the secondary inverter circuit 400 to the main path single-chip microcomputer of the primary level response board 110 in real time, realizes that the primary level response board 110 and the secondary level response board 210 jointly cooperate, realizes double-voltage output of the inverter, and can simultaneously output 2-way 120V alternating current or 1-way 240V alternating current.
[0068] Briefly, the first output end and the second output end of the primary inverter circuit 300 can serve as a 120V AC output end. Similarly, the circuit structure of the primary inverter circuit 300 and the circuit structure of the secondary inverter circuit 400 are the same. The first output end and the second output end of the secondary inverter circuit 400 can also serve as a 120V AC output end.
[0069] When the first output end of the primary inverter circuit 300 is electrically connected to the first output end of the secondary inverter circuit 400, and the second output end of the primary inverter circuit 300 is electrically connected to the second output end of the secondary inverter circuit 400, the primary inverter circuit 300 and the secondary inverter circuit 400 can serve as a common whole to become a 240V AC output end.
[0070] As shown in the embodiment of the present application, the circuit structure of the primary voltage circuit 130 is the same as that of the secondary voltage circuit 230. Figure 2 The primary voltage circuit 130: The main road AC output OUTX, OUTY is collected to the voltage signal A_TUX, A_TUY through the voltage dividing resistor and sent to the main single-chip microcomputer for detection.
[0071] The primary current detection circuit 120: The main road AC signal input is collected to the current signal A_IIX, A_IIY through the current sampling resistor, and the signal is amplified to A_TIX, A_TIY through the operational amplifier and sent to the main single-chip microcomputer for detection.
[0072] The secondary voltage circuit 230: The slave road AC output OUTO, OUTY is collected to the voltage signal A_TUO, A_TUZ through the voltage dividing resistor and sent to the slave single-chip microcomputer for detection.
[0073] The secondary current detection circuit 220: The slave road AC signal input is collected to the current signal A_IIZ, A_IIO through the current sampling resistor, and the signal is amplified to A_TIZ, A_TIO through the operational amplifier and sent to the slave single-chip microcomputer for detection.
[0074] The technical features of the above-mentioned embodiments can be combined in any way, and the execution order of the method steps is not limited. In order to make the description simple, all possible combinations of the technical features in the above-mentioned embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.
[0075]
[0076] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific manner, but should not be construed as limiting the scope of the patent of the present application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A digitally isolated dual voltage output inverter, characterized by, The application relates to a power supply device, which comprises a primary regulating board, a secondary regulating board, a primary inverter circuit and a secondary inverter circuit. The primary regulating board comprises a primary level response board, a primary current detection circuit and a primary voltage circuit, the primary level response board is electrically connected with the primary current detection circuit, and the primary level response board is electrically connected with the primary voltage circuit. The secondary regulating board comprises a secondary level response board, a secondary current detection circuit and a secondary voltage circuit, the secondary level response board is electrically connected with the secondary current detection circuit, the secondary level response board is electrically connected with the secondary voltage circuit, and the primary level response board is electrically connected with the secondary level response board. The primary inverter circuit is electrically connected with the primary level response board. The secondary inverter circuit is electrically connected with the secondary level response board.
2. The digitally isolated dual voltage output inverter of claim 1, wherein, The circuit structure of the primary inverter circuit is the same as that of the secondary inverter circuit.
3. The digitally isolated dual voltage output inverter of claim 2, wherein, The primary inverter circuit comprises a first PWM chip and a first P-type MOS tube. The signal input end of the first PWM chip is electrically connected with the first signal output end of the primary level response board. The signal output end of the first PWM chip is electrically connected with the gate of the first P-type MOS tube. The drain of the first P-type MOS tube is electrically connected with the first input power supply of a digital isolation double-voltage output inverter. The source of the first P-type MOS tube is defined as the first output end of the primary inverter circuit.
4. The digitally isolated dual voltage output inverter of claim 3, wherein, The primary inverter circuit further comprises a second PWM chip and a second P-type MOS tube. The signal input end of the second PWM chip is electrically connected with the second signal output end of the primary level response board. The signal output end of the second PWM chip is electrically connected with the gate of the second P-type MOS tube. The drain of the second P-type MOS tube is electrically connected with the source of the first P-type MOS tube. The source of the second P-type MOS tube is grounded.
5. The digitally isolated dual voltage output inverter of claim 4, wherein, The primary inverter circuit further comprises a first feedback capacitor and a second feedback capacitor. The first feedback capacitor is electrically connected between the connecting link between the first input power supply end of the second PWM chip and the second input power supply end of the second PWM chip. The second feedback capacitor is electrically connected between the connecting link between the first feedback capacitor and the second input power supply end of the second PWM chip. The connecting node between the first feedback capacitor and the second feedback capacitor is grounded.
6. The digitally isolated dual voltage output inverter of claim 5, wherein, The primary inverter circuit further comprises a third PWM chip and a third P-type MOS tube. The signal input end of the third PWM chip is electrically connected with the third signal output end of the primary level response board. The signal output end of the third PWM chip is electrically connected with the gate of the third P-type MOS tube. The drain of the third P-type MOS tube is electrically connected with the second input power supply of the digital isolation double-voltage output inverter. The source of the third P-type MOS tube is defined as the second output end of the primary inverter circuit.
7. The digitally isolated dual voltage output inverter of claim 6, wherein, The primary inverter circuit further comprises a fourth PWM chip and a fourth P-type MOS tube. The signal input end of the fourth PWM chip is electrically connected with the fourth signal output end of the primary level response board. The signal output end of the fourth PWM chip is electrically connected with the gate of the fourth P-type MOS tube. The drain of the fourth P-type MOS tube is electrically connected with the source of the third P-type MOS tube. The source of the fourth P-type MOS tube is grounded. The first output end of the primary voltage circuit and the second output end of the primary voltage circuit are connected with the load of the digital isolation double-voltage output inverter.
8. The digitally isolated dual voltage output inverter of claim 7, wherein, The circuit structure of the primary voltage circuit is the same as the circuit structure of the secondary voltage circuit.