Operational transconductance amplifier OTA

Abstract

Described herein is an operational transconductance amplifier (OTA). The OTA includes two input pairs of transistors: a first pair provides a variable current based on a feedback voltage and an input voltage, and a second pair also absorbs the variable current based on the feedback voltage and the input voltage. The folded cascode arrangement includes two branches, one of which includes a Monicelli cell. A class AB output stage exists, and the input of the class AB output stage is connected to the two ends of the Monicheri unit. Further, the bias stage mirrors and scales the constant current to generate the control voltage. Within the folded cascode branches, the compensation transistors are controlled by these control voltages to ensure that the magnitudes of various variable currents provided and absorbed are equal, making the OTA independent of the input voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to operational transconductance amplifiers (OTAs), and in particular to circuitry designed for implementing current balancing in folded cascode branches of rail-to-rail input OTAs with class-AB output stages. BACKGROUND

[0002] Operational transconductance amplifiers (OTAs) are fundamental building blocks in the design of analog integrated circuits. Their ability to convert a differential voltage input into a current output makes them important in a variety of applications such as filters, oscillators, and analog signal processing chains. The rail-to-rail input capability in OTAs ensures that the amplifier can handle input signals spanning the entire power supply range (e.g., 0 to VDD), providing greater design flexibility and wider applicability. SUMMARY

[0003] Disclosed herein is an operational transconductance amplifier (OTA) comprising a constant current source configured to provide a first constant current to a first node and a first input pair of transistors. The first input pair of transistors comprises: a first input transistor coupled between the first node and a third folded branch node, the first input transistor configured to provide a first variable current to the third folded branch node based on a feedback voltage; and a second input transistor coupled between the first node and a fourth folded branch node, the second input transistor configured to provide a second variable current to the fourth folded branch node based on an input voltage. A tail current source sinks a tail current from a second node. A second input pair of transistors comprises: a third input transistor coupled between a first folded branch node and the second node, the third input transistor configured to sink a third variable current from the first folded branch node based on the feedback voltage; and a fourth input transistor coupled between a second folded branch node and the second node, the fourth input transistor configured to sink a fourth variable current from the second folded branch node based on the input voltage. A folded cascode arrangement comprises a first folded cascode branch coupled to the first folded branch node and the third folded branch node and a second folded cascode branch coupled to the second folded branch node and the fourth folded branch node, wherein the second folded cascode branch comprises a Monticelli cell coupled between the second folded branch node and the fourth folded branch node. A class AB output stage has an input coupled across the Monticelli cell. A bias stage is configured to mirror and scale the first constant current and the tail current to generate first and second control voltages. The folded cascode arrangement comprises, within the first folded cascode branch: a first tail generator transistor controlled by the first control voltage to provide a fifth variable current to the first folded branch node, the fifth variable current having a magnitude equal to the third variable current; and a second tail generator transistor controlled by the second control voltage to sink a sixth variable current from the third folded branch node, the sixth variable current having a magnitude equal to the first variable current. The folded cascode arrangement comprises, within the second folded cascode branch: a third tail generator transistor controlled by the first control voltage to provide a seventh variable current to the second folded branch node, the seventh variable current having a magnitude equal to the fourth variable current; and a fourth tail generator transistor controlled by the second control voltage to sink an eighth variable current from the fourth folded branch node, the eighth variable current having a magnitude equal to the second variable current.

[0004] The tail current source can be a current mirror having a control node that receives the first control signal. The constant current source can have a control terminal that receives the second control signal. The bias stage can include a first bias transistor connected in a diode-coupled arrangement between a supply voltage node and a first compensation node, a second bias transistor connected between the first compensation node and ground, a control terminal of the second bias transistor connected to the control node of the current mirror, a third bias transistor connected between the supply voltage node and a second compensation node, a control terminal of the third bias transistor coupled to the second control signal, a fourth bias transistor connected between the second compensation node and ground, a control terminal of the fourth bias transistor coupled to the first control signal, and a fifth bias transistor connected in a diode-coupled arrangement between the second compensation node and ground.

[0005] The constant current source can have a control terminal that receives the second control signal. The folded cascode arrangement can further include, within the first folded cascode branch: a fifth tail generator transistor connected between the supply voltage node and a first folded branch node, the fifth tail generator transistor having a control terminal coupled to the second control signal; a first cascode transistor connected between the first folded branch node and a third cascode transistor, the first cascode transistor having a control terminal coupled to a first cascode control signal; a second cascode transistor connected between the first cascode transistor and the third cascode transistor, the second cascode transistor having a control terminal coupled to a third cascode control signal; a third cascode transistor connected between the second cascode transistor and a third folded branch node, the third cascode transistor having a control terminal coupled to a second cascode control signal; and a sixth tail generator transistor connected between the third folded branch node and ground, the sixth tail generator transistor having a control terminal coupled to a node between the second cascode transistor and the third cascode transistor. The folded cascode arrangement can further include, within the second folded cascode branch: a seventh tail generator transistor connected between the supply voltage node and a second folded branch node, the seventh tail generator transistor having a control terminal coupled to the second control signal; a fourth cascode transistor connected between the second folded branch node and the Monticelli cell, the fourth cascode transistor having a control terminal coupled to the first cascode control signal; a fifth cascode transistor connected between the Monticelli cell and a fourth folded branch node, the fifth cascode transistor having a control terminal coupled to the second cascode control signal; and an eighth tail generator transistor connected between the fourth folded branch node and ground, the eighth tail generator transistor having a control terminal coupled to the node between the second cascode transistor and the third cascode transistor.

[0006] The first folded branch node can be connected to a source of the first cascode transistor, and the second folded branch node can be connected to a source of the fourth cascode transistor. The folded cascode arrangement can further include a first chopper having first and second inputs and first and second outputs, the first chopper configured to chop voltages at the first and second inputs of the first chopper, the first output of the first chopper connected to a drain of the first cascode transistor, the second output of the first chopper connected to a drain of the fourth cascode transistor. The fifth tail generator transistor can have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper. The first tail generator transistor can have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper. The seventh tail generator transistor can have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper. The third tail generator transistor can have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper.

[0007] The third folded branch node can be connected to a source of the third cascode transistor, and the fourth folded branch node can be connected to a source of the fifth cascode transistor. The folded cascode arrangement can further include a second chopper having first and second inputs and first and second outputs, the second chopper configured to chop voltages at the first and second inputs of the second chopper, the first output of the second chopper connected to drains of the sixth tail generator transistor and the second tail generator transistor, the second output of the second chopper connected to drains of the eighth tail generator transistor and the fourth tail generator transistor. The third cascode transistor can have a first conduction terminal connected to the second cascode transistor and a second conduction terminal connected to the first input of the second chopper. The fifth cascode transistor can have a first conduction terminal connected to the Monticelli cell and a second conduction terminal connected to the second input of the second chopper.

[0008] The folded cascode arrangement can further include a first chopper having first and second inputs and first and second outputs, the first chopper configured to chop voltages at the first and second inputs of the first chopper, the first output of the first chopper connected to the drain of the first cascode transistor, the second output of the first chopper connected to the fourth cascode transistor. The fifth tail generator transistor can have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper. The first tail generator transistor can have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper. The seventh tail generator transistor can have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper. The third tail generator transistor can have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper. The folded cascode arrangement can further include a second chopper having first and second inputs and first and second outputs, the second chopper configured to chop voltages at the first and second inputs of the second chopper, the first output of the second chopper connected to the drains of the sixth tail generator transistor and the second tail generator transistor, the second output of the second chopper connected to the drains of the eighth tail generator transistor and the fourth tail generator transistor. The third cascode transistor can have a first conduction terminal connected to the second cascode transistor and a second conduction terminal connected to the first input of the second chopper. The fifth cascode transistor can have a first conduction terminal connected to the Monticelli cell and a second conduction terminal connected to the second input of the second chopper. The third chopper can be configured to chop the feedback voltage and the input voltage, provide the chopped feedback voltage to the control terminals of the first input transistor and the third input transistor, and provide the chopped input voltage to the control terminals of the second input transistor and the fourth input transistor.

[0009] The constant current source can have a control terminal that receives the second control signal. The class AB output stage can include a first input coupled to the first output terminal of the Monticelli cell, a second input coupled to the second output terminal of the Monticelli cell, a first output transistor connected between the supply node and an output node, the first output transistor having a control terminal connected to the first input, a second output transistor connected between the output node and ground, the second output transistor having a control terminal connected to the second input, a third output transistor connected between the supply node and a fourth output transistor, the third output transistor having a control terminal connected to the second control signal, a fourth output transistor connected in a diode coupled configuration between the third output transistor and the first input of the Monticelli cell, a fifth output transistor connected in a diode coupled configuration between the fourth output transistor and ground, a sixth output transistor connected in a diode coupled configuration between the supply node and a seventh output transistor, a seventh output transistor connected in a diode coupled configuration between the sixth output transistor and the second input of the Monticelli cell, and an eighth output transistor connected between the second input of the Monticelli cell and ground.

[0010] The Monticelli cell can include a first transistor connected between the first output terminal and the second output terminal, wherein the first transistor has a control terminal connected to a control terminal of the fourth output transistor, and a second transistor connected between the first output terminal and the second output terminal, wherein the second transistor has a control terminal connected to a control terminal of the seventh output transistor.

[0011] The class AB output stage can include a first resistor and a first capacitor connected in series between the first output terminal of the Monticelli cell and the output node, and a second resistor and a second capacitor connected in series between the second output terminal of the Monticelli cell and the output node.

[0012] The class AB output stage can include a first capacitor connected in series between the second folded branch node and the output node, and a second capacitor connected in series between the fourth folded branch node and the output node.

[0013] Disclosed herein is an operational transconductance amplifier (OTA) comprising: a constant current source p-channel transistor having a source connected to a supply voltage node, a drain connected to a first node, and a gate coupled to a first control voltage; a first input pair of transistors comprising: a first input p-channel transistor having a source connected to the first node, a drain connected to a third folded branch node, and a gate coupled to a feedback voltage; and a second input p-channel transistor having a source connected to the first node, a drain connected to a fourth folded branch node, and a gate coupled to an input voltage; a tail current source n-channel transistor having a drain connected to a second node, a source connected to ground, and a gate connected to the third node; a second input pair of transistors comprising: a first input n-channel transistor having a drain connected to the first folded branch node, a source connected to the second node, and a gate coupled to the feedback voltage; and a second input n-channel transistor having a drain connected to the second folded branch node, a source connected to the second node, and a gate coupled to the input voltage; a first mirror n-channel transistor having a drain and a gate connected to the third node, and a source connected to ground; a second mirror p-channel transistor having a source connected to the first node, a drain connected to the third node, and a gate connected to a fourth node; a third mirror p-channel transistor having a source connected to the supply voltage node, and a drain and a gate connected to the fourth node; a tail n-channel transistor having a drain connected to the fourth node, a source connected to ground, and a gate coupled to a second control voltage; a bias stage comprising: a first bias p-channel transistor having a source connected to the supply voltage node, a drain connected to a first bias node, and a gate coupled to the first control voltage; a first bias n-channel transistor having a drain connected to the first bias node, a source connected to ground, and a gate coupled to the first bias node; a second bias n-channel transistor having a drain connected to the first bias node, a source connected to ground, and a gate coupled to the second control voltage; a second bias p-channel transistor having a source connected to the supply voltage node, and a drain and a gate connected to a second bias node; and a third bias n-channel transistor having a drain connected to the second bias node, a source connected to ground, and a gate coupled to the third node.The folded cascode arrangement includes, within the first folded cascode branch: a first tail generator p-channel transistor having a source connected to a supply voltage node, a drain connected to a first folded branch node, and a gate connected to a second bias node; and a first tail generator n-channel transistor having a drain connected to a third folded branch node, a source connected to ground, and a gate connected to a first bias node; the folded cascode arrangement includes, within the second folded cascode branch: a second tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to a second folded branch node, and a gate connected to the first bias node; a second tail generator n-channel transistor having a drain connected to a fourth folded branch node, a source connected to ground, and a gate connected to the first bias node; and a Monticelli cell coupled between the drain of the second tail generator p-channel transistor and the drain of the second tail generator n-channel transistor; an AB class output stage having an input coupled across the Monticelli cell and an output connected to an output node.

[0014] In one embodiment, the folded cascode arrangement further includes, within the first folded cascode branch: a third tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to the first folded branch node, and a gate coupled to a first control voltage; a first cascode p-channel transistor having a source connected to the first folded branch node, a drain, and a gate coupled to a first cascode control signal; a second cascode p-channel transistor having a source connected to the drain of the first cascode p-channel transistor, a drain, and a gate connected to a first cascode control node; a first cascode n-channel transistor having a drain connected to the drain of the second cascode p-channel transistor, a source connected to the third folded branch node, and a gate coupled to a second cascode control signal; and a second cascode n-channel transistor having a drain connected to the third folded branch node, a source connected to ground, and a gate connected to the drain of the second cascode p-channel transistor.

[0015] In one embodiment, the folded cascode arrangement further includes, within the second folded cascode branch: a third cascode p-channel transistor having a source connected to a supply voltage node, a drain connected to the second folded branch node, and a gate coupled to a first control voltage; a fourth cascode p-channel transistor having a source connected to the second folded branch node, a drain, and a gate connected to a first cascode control signal; a third cascode n-channel transistor having a drain, a source connected to a fourth folded branch node, and a gate coupled to a second cascode control signal; a fourth cascode n-channel transistor having a drain connected to the fourth folded branch node, a source connected to ground, and a gate connected to a drain of the second cascode p-channel transistor; and a Monticelli cell having a first output connected to a drain of the fourth cascode p-channel transistor, a second output connected to a drain of the second cascode n-channel transistor, a first input connected to the first cascode control node, and a second input connected to the second cascode control node.

[0016] In one embodiment, the operational transconductance amplifier OTA further includes: a first chopper having a first input connected to a drain of the third tail generator p-channel transistor, a second input connected to a drain of the first tail generator p-channel transistor, a first output connected to the first folded branch node, and a second output connected to the second folded branch node; and a second chopper having a first input connected to a source of the first cascode n-channel transistor, a second input connected to a source of the third cascode n-channel transistor, a first output connected to the third folded branch node, and a second output connected to the fourth folded branch node.

[0017] In one embodiment, the operational transconductance amplifier OTA further includes a third chopper configured to chop the feedback voltage and the input voltage.

[0018] In one embodiment, the class AB output stage includes: a first input node connected to a first output of the Monticelli cell; a second input node connected to a second output of the Monticelli cell; a first output p-channel transistor having a source connected to a supply voltage node, a drain connected to an output node, and a gate connected to the first input node; a first output n-channel transistor having a drain connected to the output node, a source connected to ground, and a gate connected to the second input node; a second output p-channel transistor having a source connected to the supply voltage node, a drain connected to a second cascode control node, and a gate coupled to a first control voltage; a second output n-channel transistor having a drain and a gate connected to the second cascode control node, and a source; a third output n-channel transistor having a drain and a gate connected to the source of the second output n-channel transistor, and a source connected to ground; a third output p-channel transistor having a source connected to the supply voltage node, and a gate and a drain; a fourth output p-channel transistor having a source connected to the gate and the drain of the third output p-channel transistor, and a gate and a drain connected to a first cascode control node; and a fourth output n-channel transistor having a drain connected to the first cascode control node, a source connected to ground, and a gate coupled to the second control voltage.

[0019] In one embodiment, the class AB output stage further includes: a first resistor and a first capacitor connected in series between the first output of the Monticelli cell and the output node; and a second resistor and a second capacitor connected in series between the second output of the Monticelli cell and the output node.

[0020] In one embodiment, the class AB output stage further includes: a first capacitor connected in series between the second cascode node and the output node; and a second capacitor connected in series between the fourth cascode node and the output node. BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1 is a schematic diagram of a prior art operational transconductance amplifier (OTA).

[0022] Figure 2 is a schematic diagram of a first embodiment of the OTA disclosed herein.

[0023] Figure 3 is a schematic diagram of a second embodiment of the OTA disclosed herein.

[0024] Figure 4 is a schematic diagram of a third embodiment of an OTA disclosed herein.

[0025] Figure 5 is a schematic diagram of a fourth embodiment of an OTA disclosed herein. DETAILED DESCRIPTION

[0026] The following disclosure enables a person skilled in the art to make and use the subject matter described herein. The general principles outlined in the disclosure can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the disclosure. It is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0027] Note that in the following description, unless otherwise stated, any resistor or resistance referred to is a discrete device, and not merely an electrical lead between two points. Thus, any resistor or resistance connected between two points has a resistance higher than the electrical lead between those two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, unless otherwise stated, any capacitor or capacitance referred to is a discrete device, and not a parasitic element, unless otherwise stated. Also, unless otherwise stated, any inductor or inductance referred to is a discrete device, and not a parasitic element, unless otherwise stated.

[0028] One of the popular topologies employed in OTA design to achieve rail-to-rail input capability is the folded cascode configuration. Compared to the basic OTA structure, the folded cascode OTA offers advantages such as improved linearity, increased output resistance, and better swing capability. However, when the input voltage approaches the rail limits, the current distribution within the folded cascode branches can vary. These variations can lead to nonlinearity in the behavior of the amplifier, offset voltage, and other undesirable anomalies.

[0029] A known OTA 10 is now described with reference to Figure 1. The OTA 10 comprises a p-channel transistor Ml whose source is connected to a supply node VDD, whose drain is connected to a node Nl, and whose gate is coupled to a control signal ppol. In the OTA 10 described below, note that the voltages ppol, npol, ncasc, and pcasc are generated outside the OTA 10, and are generally available in a system in which such an OTA is integrated.

[0030] The first input pair 13 is formed by a p-channel transistor MP0, whose source is connected to node N1, whose drain is connected to node C, and whose gate is coupled to the feedback voltage VFB, and by a p-channel transistor MP1, whose source is connected to node N1, whose drain is connected to node D, and whose gate is coupled to the input voltage VIN. For simplicity, from now on the condition VIN almost equal to VFB will be applied, since this OTA is usually used in a closed loop system.

[0031] The second input pair 14 is formed by an n-channel transistor MN0, whose drain is connected to node A, whose source is connected to node N2, and whose gate is coupled to the feedback voltage VFB, and by an n-channel transistor MN1, whose drain is connected to node B, whose source is connected to node N2, and whose gate is coupled to the input voltage VIN.

[0032] The current mirror is formed by an n-channel transistor M5, whose drain is connected to node N2, whose source is connected to ground, and whose gate is connected to node N3 and receives the tail voltage ntail, and by an n-channel transistor M4, whose drain and gate are connected to node N3, and whose source is connected to ground.

[0033] The current splitting structure 12 is formed by a p-channel transistor M3, whose source is connected to node N1, whose drain is connected to node N3, and whose gate is connected to node N4, by a p-channel transistor M2, whose source is connected to the supply node VDD, whose drain is connected to node N4, and whose gate is connected to node N4, and by an n-channel transistor MC0, whose drain is connected to node N4, whose source is connected to ground, and whose gate is connected to the control signal npol.

[0034] The folded cascode 17 is formed from the following elements: a p-channel transistor M6 having its source connected to the supply node VDD, its drain connected to node A, and its gate coupled to the control signal ppol; a p-channel transistor M8 having its source connected to node A, its drain connected to node N5, and its gate connected to the gate of a p-channel transistor M9 and to the control signal pcasc; an n-channel transistor M13 having its drain connected to node N5, its source connected to node C, and its gate connected to the gate of an n-channel transistor M12 and to the control signal ncasc; an n-channel transistor M14 having its drain connected to node C, its source connected to ground, and its gate connected to node N5; a p-channel transistor M7 having its source connected to the supply node VDD, its drain connected to node B, and its gate connected to the control signal ppol; a p-channel transistor M9 having its source connected to node B, its drain connected to node N6, and its gate connected to the control signal pcasc; an n-channel transistor M12 having its drain connected to node N6, its source connected to node D, and its gate connected to the gate of the n-channel transistor M13 and to the control signal ncasc; and an n-channel transistor M15 having its drain connected to node D, its source connected to ground, and its gate connected to node N5.

[0035] The class AB output stage 19 is formed from the following elements: a p-channel transistor M16 having its source connected to the supply node VDD, its drain connected to the source of a p-channel transistor M17, and its gate connected to the gate of the p-channel transistor M7 and to the control signal ppol; the p-channel transistor M17 having its source connected to the drain of the p-channel transistor M16, its drain connected to node N7, and its gate coupled to the control signal pcasc; and the Monticelli cell 18. The Monticelli cell 18 is formed from the following elements: an n-channel transistor Ml l having its drain connected to node N7, its source connected to node N6, and its gate coupled to node H; and a p-channel transistor M10 having its source connected to node N7, its drain connected to node N6, and its gate coupled to node J.

[0036] The class AB output stage 19 further includes: an n-channel transistor M18 having its drain connected to node N6, its source connected to the drain of an n-channel transistor M19, and its gate coupled to a control signal ncasc; the n-channel transistor M19 having its drain connected to the source of the n-channel transistor M18, its source connected to ground, and its gate coupled to a control signal npol; a p-channel transistor M21 having its source connected to a supply node VDD, its drain connected to a node NO, and its gate connected to a node N7; an n-channel transistor M20 having its drain connected to the node NO, its source connected to ground, and its gate connected to the node N6; a p-channel transistor M34 having its source connected to VDD, its drain connected to a node H, and its gate coupled to a control signal ppol; an n-channel transistor M32 having its drain and gate connected to the node H, and its source connected to the gate and drain of an n-channel transistor M31; the n-channel transistor M31 having its drain and gate connected to the source of the n-channel transistor M32, and its source connected to ground; a p-channel transistor M35 in diode-coupled configuration having its source connected to VDD, and its gate and drain connected to the source of a p-channel transistor M36; the p-channel transistor M36 in diode-coupled configuration having its source connected to the gate and drain of the p-channel transistor M35, and its drain and gate connected to a node J; and an n-channel transistor M33 having its drain connected to the node J, its source connected to ground, and the gate of M33 coupled to the control signal npol.

[0037] A capacitor C2 is connected between the node NO and ground, and an output voltage Vout is developed across the capacitor C2. A resistor RO and a capacitor CO are connected in series between the node N7 and the node NO. A resistor Rl and a capacitor CI are connected in series between the node N6 and the node NO.

[0038] In operation, the voltage VIN is the non-inverting input of the OTA 10 (e.g., the gates of transistors MP1 and MN1), and the feedback voltage VFB is the inverting input of the OTA 10 (e.g., the gates of transistors MP0 and MN0). The p-channel transistor M1 is controlled via the control signal ppol such that a constant current of 2I TI magnitude is provided to the node N1.

[0039] The control signal npol causes a constant current of 2I TI to be drawn from N4 by MC0 and provided by M2, defining the voltage of node N4. M3 splits the current 2I TI from node N1 into 2(I TI -x) and 2x. The portion 2(I TI -x) is further split into equal-magnitude portions, namely, I TI- x. The current part 2x flows through M3 and is mirrored by M4 to M5 until it flows through MN0 and MN1. In more detail, transistor MC0 is a sink that absorbs the current read by transistor M2. This arrangement generates a voltage on node N4 that is used to control the gate of transistor M3. Consider the case where VIN is close to ground; in this case, 2I TI will flow into transistors MP0 and MP1, thus node N1 will follow VIN and the voltage at node N1 will be low enough to force transistor M3 off, so that 2x = 0, transistors MN0 and MN1 are also in the off state under this condition. Now consider the case where VIN is close to VDD; in this case, 2I TI will flow into transistor M1, node N1 will follow the voltage at node N4 and the voltage at node N1 will be low enough to force transistors MP0 and MP1 off, so that 2I TI will flow through transistor M3 and will be mirrored by M4:M5 to MN0:MN1, so that 2x = 2I TI , transistors MN0 and MN1 are in the on state under this condition. The dimensions of transistors MC0 and M2 are designed so that if VIN is close to VDD, then transistor M3 can absorb the current generated by transistor M1, so that this current essentially bypasses transistors MP0 and MP1.

[0040] With this in mind, the arrangement of n-channel transistor MC0, structure M2:M3 and current mirror M4:M5 allows to distinguish where the current of magnitude 2I TI provided by p-channel transistor M1 to node N1 will flow. If VIN is low enough, then this current flows into input pair 13 and if VIN is high enough, then this current flows into input pair 14. If VIN is at some intermediate position between the low and high values, then the current 2I TI is split into two parts (2I TI - 2x and 2x), where 2x can be larger or smaller depending on VIN.

[0041] For example, when VIN decreases and approaches 0, the value of x approaches 0, mathematically expressed as:

[0042]

[0043] When VIN is 0, the current of magnitude I TI thus flows into each of p-channel transistor MP0 and p-channel transistor MP1, while essentially no current flows through M3 and current mirror M4:M5.

[0044] Conversely, when VIN increases and approaches VDD, the value of x approaches I TI , mathematically expressed as:

[0045]

[0046] For VIN = VDD, the current has magnitude I TI Thus, current flows into each of the n-channel transistors MN0 and MN1, while substantially no current flows into the p-channel transistors MP0 and MP1.

[0047] Due to this current steering arrangement, the transconductance of the OTA 10 is independent of the input voltage at the first order.

[0048] In the cascode 17, the p-channel transistor M6, controlled via the control signal ppol, provides a current to the node A having magnitude I TF , but recalling that the n-channel transistor MN0 absorbs a current from the node A having magnitude x, it follows that the current provided by the p-channel transistor M8 to the node N5 has magnitude I TF -x. Similarly, the p-channel transistor M7, controlled via the control signal ppol, provides a current to the node B having magnitude I TF , but recalling that the n-channel transistor MN1 absorbs a current from the node B having magnitude x, it follows that the current provided by the p-channel transistor M9 to the node N6 has magnitude I TF -x. The n-channel transistor M13, controlled via the control signal ncasc, in turn provides a current to the node C having magnitude I TF -x, and, likewise, the n-channel transistor M12, controlled via the control signal ncasc, provides a current to the node D having magnitude I TF -x.

[0049] Since the n-channel transistor M13 provides a current to the node C having magnitude I TF -x and since the p-channel transistor MP0 provides a current to the node C having magnitude I TI -x, it follows that the magnitude of the current through the n-channel transistor M14 is I TF + I TI - 2x. Similarly, since the n-channel transistor M12 provides a current to the node D having magnitude I TF -x and since the p-channel transistor MP1 provides a current to the node D having magnitude I TI -x, it follows that the magnitude of the current through the n-channel transistor M15 is I TF + I TI - 2x.

[0050] With regard to the operation of the cascode 17, first consider the case where the value of VIN is 0. At this time, the n-channel transistor M13 provides a current to the node C having magnitude I TFThe current, with a value of I, is supplied to node D by the n-channel transistor M12. TF The current, with a value of I, is supplied to node C by the p-channel transistor MP0. TI The current, and the amount of I supplied to node D by the p-channel transistor MP1. TI The current. Therefore, the current absorbed by the n-channel transistor M14 from node C is I. TF +I TI And the current absorbed from node D by the n-channel transistor M15 is I. TF +I TI .

[0051] However, now consider the case where VIN is VDD. In this case, the n-channel transistor M13 supplies a quantity of I to node C. TF -I TI The current, with a value of I, is supplied to node D by the n-channel transistor M12. TF -I TI The p-channel transistor MP0 does not supply current to node C, and the p-channel transistor MP1 does not supply current to node D. Therefore, the current absorbed by the n-channel transistor M14 from node C is I. TF -I TI And the current absorbed by the n-channel transistor M15 from node D is I. TF -I TI .

[0052] Therefore, the bias current of the folded cascode 17 is input-dependent, which is undesirable because at high frequencies there may be some poles and zeros (generally, some singularities) that will shift undesirably with the input, making the dynamic response of the OTA input-dependent. Furthermore, the transconductance of the current mirrors M14:M15 is input-dependent, leading to an input-dependent noise contribution from the input reference mirrors M14:M15. In other words, in terms of noise and singularities (e.g., poles and zeros), OTA 10 is like three different OTAs, depending on whether the input voltage is close to VDD, close to ground, or somewhere between VDD and ground.

[0053] In the output stage 19, the Monticelli cell 18 dynamically generates a static bias voltage at nodes N7 and N6 to control the bias currents of M21 and M20, thus enabling low cross distortion by keeping the output transistors M21 and M20 slightly on in the absence of input signal. As the input signal amplitude rises, the Monticelli cell 18 modulates the gate voltages of these output transistors M21 and M20, thus providing adaptive driving capability. This provides balanced operation between the push transistor M21 and the pull transistor M20, thus equalizing their contribution during transitions. The Monticelli cell 18 provides thermal stability, dynamically adjusting the bias according to temperature variations. This results in an AB class output at the output node NO with balanced efficiency and linearity.

[0054] It is noted that here the Monticelli cell 18 is positioned in a separate branch from the folded cascode 17, as the Monticelli cell operates with a constant current, and as explained the folded cascode 17 does not provide a constant current. The use of this separate branch consumes space and increases the complexity of the OTA 10 design.

[0055] In view of the above-mentioned drawbacks of the folded cascode 17 and the resulting drawbacks in biasing the Monticelli cell 18, further development in the field of OTAs is needed.

[0056] Reference is now made to Figure 2 An improved OTA 20 with a folded cascode configuration is described. The OTA 20 comprises a p-channel transistor M1, the source of which is connected to a supply node VDD, the drain of which is connected to a node N1, and the gate of which is coupled to a control signal ppol.

[0057] The first input pair 13 is formed by a p-channel transistor MP0, the source of which is connected to the node N1, the drain of which is connected to a node C, and the gate of which is coupled to a feedback voltage VFB, and a p-channel transistor MP1, the source of which is connected to the node N1, the drain of which is connected to a node D, and the gate of which is coupled to an input voltage VIN. For simplicity, from now on the condition that VIN is almost equal to VFB will be applied, as this OTA is typically used in a closed loop system.

[0058] The second input pair 14 is formed by an n-channel transistor MN0, the drain of which is connected to a node A, the source of which is connected to a node N2, and the gate of which is coupled to a feedback voltage VFB, and an n-channel transistor MN1, the drain of which is connected to a node B, the source of which is connected to the node N2, and the gate of which is coupled to an input voltage VIN.

[0059] The current mirror is formed by an n-channel transistor M5, whose drain is connected to node N2, whose source is connected to ground, and whose gate is connected to node N3 and receives a tail voltage ntail, and an n-channel transistor M4, whose drain and gate are connected to node ntail, and whose source is connected to ground.

[0060] The current split structure 12 is formed by a p-channel transistor M3, whose source is connected to node N1, whose drain is connected to node N3, and whose gate is connected to node N4, a p-channel transistor M2, whose source is connected to a supply node VDD, whose drain is connected to node N4, and whose gate is connected to node N4, and an n-channel transistor MC0, whose drain is connected to node N4, whose source is connected to ground, and whose gate is connected to a control signal npol.

[0061] The bias stage 21 includes a p-channel transistor M30, whose source is connected to a supply node VDD, and whose drain and gate are connected to node F, an n-channel transistor M29, whose drain is connected to node F, whose source is connected to ground, and whose gate is coupled to a control voltage ntail, a p-channel transistor M27, whose source is connected to a supply node VDD, whose drain is connected to node E, and whose gate is coupled to a control voltage ppol, an n-channel transistor M28, whose drain is connected to node E, whose source is connected to ground, and whose gate is coupled to a control voltage ntail, and a diode-coupled n-channel transistor M26, whose drain and gate are connected to node E and whose source is connected to ground, between node E and ground.

[0062] The folded cascode 17 is formed from the following elements: a p-channel transistor M6 having its source connected to the supply node VDD, its drain connected to node A, and its gate coupled to the control signal ppol; a p-channel transistor M24 having its source connected to the supply node VDD, its drain connected to node A, and its gate coupled to node F; a p-channel transistor M8 having its source connected to node A, its drain connected to the source of a p-channel transistor M37, and its gate connected to the gate of a p-channel transistor M9 and to the control signal pcasc; a p-channel transistor M37 having its source connected to the drain of the p-channel transistor M8, its drain connected to node N5, and its gate connected to node J; an n-channel transistor M13 having its drain connected to node N5, its source connected to node C, and its gate connected to the gate of an n-channel transistor M12 and to the control signal ncasc; an n-channel transistor M14 having its drain connected to node C, its source connected to ground, and its gate connected to node N5; an n-channel transistor M23 having its drain connected to node C, its source connected to ground, and its gate connected to node E; a p-channel transistor M7 having its source connected to the supply node VDD, its drain connected to node B, and its gate connected to the control signal ppol; a p-channel transistor M25 having its source connected to the supply node VDD, its drain connected to node B, and its gate coupled to node F; and a p-channel transistor M9 having its source connected to node B, its drain connected to node N7, and its gate connected to the gate of the p-channel transistor M8 and to the control signal pcasc.

[0063] The folded cascode 17 also includes a Monticelli unit 18 formed from the following elements: an n-channel transistor Ml 1 having its drain connected to node N7, its source connected to node N6, and its gate coupled to node H; and a p-channel transistor M10 having its source connected to node N7, its drain connected to node N6, and its gate coupled to node J.

[0064] The folded cascode 17 also includes: an n-channel transistor M12 having its drain connected to node N6, its source connected to node D, and its gate connected to the gate of the n-channel transistor M13 and to the control signal ncasc; an n-channel transistor M15 having its drain connected to node D, its source connected to ground, and its gate connected to node N5; and an n-channel transistor M22 having its drain connected to node D, its source connected to ground, and its gate coupled to node E.

[0065] The Class AB output stage 19 includes: a p-channel transistor M21, whose source is connected to the power supply node VDD, its drain is connected to node NO, and its gate is connected to node N7; an n-channel transistor M20, whose drain is connected to node NO, its source is connected to ground, and its gate is connected to node N6; a p-channel transistor M34, whose source is connected to the supply voltage VDD, its drain is connected to node H, and its gate is coupled to the control signal ppol; and a diode-coupled n-channel transistor M32, whose drain and gate are connected to node H, and whose source is connected to the drain and gate of the n-channel transistor M31. Gate; a diode-coupled n-channel transistor M31, whose drain and gate are connected to the source of an n-channel transistor M32, and whose source is connected to ground; a diode-coupled p-channel transistor M35, whose source is connected to the supply voltage VDD, and whose drain and gate are connected to the source of a p-channel transistor M36; a diode-coupled p-channel transistor M36, whose source is connected to the drain and gate of transistor M35, and whose drain and gate are connected to node J; and an n-channel transistor M33, whose drain is connected to node J, whose source is connected to ground, and whose gate is coupled to the control voltage npol.

[0066] Resistor R0 and capacitor C0 are connected in series between node N7 and node NO. Resistor R1 and capacitor C1 are connected in series between node N6 and node NO.

[0067] The operation is now described. In operation, voltage VIN is located at the non-inverting input of OTA 20 (e.g., the gates of transistors MP1 and MN1), and feedback voltage VFB is located at the inverting input of OTA 20 (e.g., the gates of transistors MP0 and MN0). P-channel transistor M1 is controlled via control signal ppol, resulting in a 2I... TI A constant current of a certain magnitude is supplied to node N1.

[0068] The control signal npol causes a constant current to be absorbed from N4 and supplied by M2, thereby limiting the voltage at node N4. M3 splits the current supplied by M1 from node N1 into fractions with a value of 2(I TI -x) part, where I TI -x flows through MP0 and I TI -x flows through MP1, and another part 2x flows through M3 and is mirrored from M4 to M5, until it flows through MN0 and MN1.

[0069] In bias stage 21, the value provided by p-channel transistor M1 is 2I. TI The current is replicated to the p-channel transistor M27 with a scaling factor of 1 / N, causing the p-channel transistor M27 to supply a value of 2I to node E. TIcurrent from N2 of magnitude 2x, and this current is replicated with a scaling factor of 1 / N to n-channel transistor M28, causing n-channel transistor M28 to sink current from node E of magnitude 2x / N. Thus, since p-channel transistor M27 provides current to node E of magnitude 2I TI / N and n-channel transistor M28 sinks current from node E of magnitude 2x / N, the difference between the two currents, equal to 2I TI / N - 2x / N is forced to flow through M26, setting the voltage at node E. In addition, the current of magnitude 2x sunk by n-channel transistor M5 from node N2 is replicated to n-channel transistor M29 and scaled by a factor of 1 / N, causing n-channel transistor M29 to sink current from node F of magnitude 2x / N. In addition, diode-coupled transistor M30 provides current to node F of magnitude 2x / N, setting the voltage at node F.

[0070] In the folded cascode 17, p-channel transistor M6, controlled via control signal ppol, provides current to node A of magnitude I TF , and p-channel transistor M24, controlled by the voltage at node F, mirrors the current provided by p-channel transistor M30 to node F with a scaling factor of N / 2, providing current to node A of magnitude x. N-channel transistor MN0 sinks current from node A of magnitude x, and p-channel transistors M8 and M37, controlled by the voltages at nodes pcasc and J, respectively, cause a constant current of magnitude I TF is provided to node N5. N-channel transistor M13, controlled via control signal ncasc, in turn provides current to node C of magnitude I TF . P-channel transistor MP0 provides current to node C of magnitude I TI -x. N-channel transistor M23, controlled by the voltage at node E, mirrors the current sunk by n-channel transistor M26 from node E with a scaling factor of N / 2, sinking current from node C of magnitude I TI -x. Thus, n-channel transistor M14 sinks current from node C of magnitude I TF .

[0071] Similarly, p-channel transistor M7, controlled via control signal ppol, provides current to node B of magnitude I TF , and p-channel transistor M25, controlled by the voltage at node F, mirrors the current provided by p-channel transistor M30 to node F with a scaling factor of N / 2, providing current to node B of magnitude x. N-channel transistor MN1 sinks current from node B of magnitude x, causing the current provided by p-channel transistor M9 to node N7 to have magnitude ITF The Monticelli cell 18 in turn provides a current of magnitude I TF to node N6 under control of the voltage at nodes H and J. N-channel transistor M12, controlled via control signal ncasc, in turn provides a current of magnitude I TF to node D. P-channel transistor MP1 provides a current of magnitude I TI -x to node D. N-channel transistor M22, under control of the voltage at node E, mirrors the current drawn from node E by n-channel transistor M26 with a scaling factor of N / 2, drawing a current of magnitude I TI -x from node D. Thus, n-channel transistor M15 draws a current of magnitude I TF from node D.

[0072] Considering the case where the value of VIN is 0, the result is that x is 0. At this time, n-channel transistor M13 provides a current of magnitude I TF to node C. Since n-channel transistor M23 draws a current of magnitude I TI from node C to match the current of magnitude I TI provided to node C by p-channel transistor MP0, the current drawn by n-channel M14 from node C when x is 0 has magnitude I TF , not I TF +I TI of the prior art design of Figure 1. Similarly, n-channel transistor M12 provides a current of magnitude I TF to node D. Since n-channel transistor M22 draws a current of magnitude I TI from node D to match the current of magnitude I TI provided to node D by p-channel transistor MP1, the current drawn by n-channel M15 from node D when VIN is 0 has magnitude I TF , not I TF +I TI of the prior art design of Figure 1. The same current balancing considerations apply to nodes A and B. At this time, p-channel transistor M6 provides a current of magnitude I TF to node A. Since p-channel transistor M24 provides a current of magnitude equal to 0 to match the current of magnitude 0 drawn by n-channel transistor MN0, the current drawn by p-channel M8 from node A when x is 0 has magnitude I TF , as in the case of the prior art design of Figure 1. Similarly, p-channel transistor M7 provides a current of magnitude I TFof I. Since the p-channel transistor M25 provides a current of magnitude equal to zero to match the n-channel transistor MN1 absorbing a current of magnitude zero, the current absorbed by the p-channel M9 from node B when x is zero has magnitude I TF , as in the case of the prior art design of Fig. 1.

[0073] Now consider the case where the value of VIN is VDD, the result is that x is I TI . At this point, the n-channel transistor M13 eventually provides a current of magnitude I TF to node C, the M12 eventually provides a current of magnitude I TF to node D, the p-channel transistor MP0 does not provide a current to node C, the p-channel transistor MP1 does not provide a current to node D, the n-channel transistor M23 does not absorb a current from node C, and the n-channel transistor M22 does not absorb a current from node D. Thus, the current absorbed by the n-channel transistor M14 from node C is I TF , and the current absorbed by the n-channel transistor M15 from node D is I TF . Similarly, the p-channel transistor M6 eventually provides a current of magnitude I TF to node A, the M7 eventually provides a current of magnitude I TF to node B, the p-channel transistor M24 provides I TI to node A, the p-channel transistor M25 provides I TI to node B, the n-channel transistor MN0 absorbs I TI from node A, and the n-channel transistor MN1 absorbs I TI from node B. Thus, the current absorbed by the p-channel transistor M8 from node A is I TF , and the current absorbed by the p-channel transistor M9 from node B is I TF , which is different from I TF -I TI , as in the case of the prior art design of Fig. 1.

[0074] Thus, when VIN is VDD, the current absorbed by M14 from node C is I TF and the current flowing through the n-channel transistor M13 and the p-channel transistor M8 is I TF , which is the same as when VIN is zero. Likewise, when VIN is VDD, the current absorbed by M15 from node D and the current flowing through the n-channel transistor M12 and the p-channel transistor M9 is I TFThe same as for VIN = 0. Therefore, the bias current of the folded cascode 17 and the bias current of the M14:M15 mirror are input independent, unlike in the prior art design of Fig. 1. The high frequency poles and zeros generated from the cascode transistors M8, M9, M13, M12, M37 and by the Monticelli cell 18 are not shifted with the input. Moreover, the transconductance of the current mirror M14:M15 is input independent, unlike in the prior art design of Fig. 1. This aspect makes the input-referred noise contribution of the M14:M15 mirror input independent. Also, the additional branch for providing a constant bias current to the Monticelli cell 18 in the prior art design of Fig. 1 is now eliminated. Moreover, the additional current consumption given by the bias stage 21 to the OTA 20 is 2(I TI +x) / N. Since the scaling factor 1 / N used herein can be set to a desired number, this means that N can be increased to reduce the current consumption.

[0075] Variants of the OTA 20 are within the scope of the present disclosure. For example, Figure 3 A variant 20' of the OTA shown in Fig. 2 includes choppers 25 connected between the drains of the p-channel transistors M24, M6 and node A and between the drains of the p-channel transistors M25, M7 and node B. Moreover, there are choppers 26 connected between the drains of the n-channel transistors M23, M14 and node C and between the drains of the n-channel transistors M15, M22 and node D. These choppers 25 and 26 are used to modulate the contribution of the transistors M24, M6, M7, M25, M23, M14, M15 and M22 to flicker noise and offset.

[0076] Another variant is Figure 4 the OTA 20" shown in Fig. 3, which includes choppers 27 chopping the feedback voltage VFB and the input voltage VIN. The OTA 20" also includes choppers 25 connected between the sources of the p-channel transistors M8 and node A and between the sources of the p-channel transistors M9 and node B. The OTA 20" further includes choppers 26 connected between the sources of the n-channel transistors M13 and node C and between the sources of the n-channel transistors M12 and node D. As explained, these choppers 25 and 26 are used to modulate the contribution of the transistors MP0, MP1, MN0, MN1, M24, M6, M7, M25, M23, M14, M15 and M22 to flicker noise and offset.

[0077] Yet another variant is Figure 5The OTA 20"'" shown in the middle, which removes resistors R0 and R1, connects capacitor C0 between node B and node NO, and connects capacitor C1 between node D and node NO, thereby provides compatibility with Ahuja compensation.

[0078] The OTAs 20, 20', 20", 20'" described herein can be used in various applications. For example, the OTA 20 can be configured as a buffer, with the output node NO connected to the inverting input (the gates of MP1 and MN1). As a buffer or as a voltage-to-current converter, the OTAs 20, 20', 20", 20'" described herein can be used in various microelectromechanical system (MEMS) applications, particularly in applications where a consistent noise level and dynamic response are desired throughout the input and output dynamic range. In particular, the OTAs 20, 20', 20", 20'" described herein can be used to drive electrodes of a gyroscope resonator or a MEMS micromirror.

[0079] Finally, it is clear that modifications and changes can be made to what has been described and illustrated herein, without departing from the scope of the present disclosure.

[0080] While the present disclosure has been described by limited number of embodiments, those skilled in the art having benefit of the present disclosure can conceive other embodiments without departing from the scope disclosed. Furthermore, the skilled person can conceive embodiments representing various combinations of the embodiments disclosed herein in various ways.

Claims

1. An operational transconductance amplifier (OTA) comprising: comprises: a constant current source configured to provide a first constant current to a first node; a first pair of inputs of transistors comprising: a first input transistor coupled between the first node and a third folded branch node, the first input transistor configured to provide a first variable current to the third folded branch node based on a feedback voltage; and a second input transistor coupled between the first node and a fourth folded branch node, the second input transistor configured to provide a second variable current to the fourth folded branch node based on an input voltage; a tail current source configured to sink a tail current from a second node; a second pair of inputs of transistors comprising: a third input transistor coupled between a first folded branch node and the second node, the third input transistor configured to sink a third variable current from the first folded branch node based on the feedback voltage; and a fourth input transistor coupled between a second folded branch node and the second node, the fourth input transistor configured to sink a fourth variable current from the second folded branch node based on the input voltage; a folded cascode arrangement comprising: a first folded cascode branch coupled to the first folded branch node and the third folded branch node; a second folded cascode branch coupled to the second folded branch node and the fourth folded branch node; wherein the second folded cascode branch comprises a Monticelli cell coupled between the second folded branch node and the fourth folded branch node; an AB class output stage having an input coupled across the Monticelli cell; a bias stage configured to: mirror and scale the first constant current and the tail current to generate a first control voltage and a second control voltage; wherein the folded cascode arrangement comprises within the first folded cascode branch: a first tail generator transistor controlled by the first control voltage for providing a fifth variable current to the first folded branch node, the fifth variable current having a magnitude equal to the third variable current; a second tail generator transistor controlled by the second control voltage for sinking a sixth variable current from the third folded branch node, the sixth variable current having a magnitude equal to the first variable current; wherein the folded cascode arrangement comprises within the second folded cascode branch: a third tail generator transistor controlled by the first control voltage for providing a seventh variable current to the second folded branch node, the seventh variable current having a magnitude equal to the fourth variable current; and a fourth tail generator transistor controlled by the second control voltage for sinking an eighth variable current from the fourth folded branch node, the eighth variable current having a magnitude equal to the second variable current.

2. The operational transconductance amplifier (OTA) of claim 1, characterized in that, wherein, the tail current source comprises a current mirror having a control node that receives the first control signal; wherein the constant current source has a control terminal that receives the second control signal; wherein the bias stage comprises: a first bias transistor connected in diode-connected arrangement between a supply voltage node and a first compensation node; a second bias transistor connected between the first compensation node and ground, a control terminal of the second bias transistor connected to a control node of the current mirror; a third bias transistor connected between the supply voltage node and a second compensation node, a control terminal of the third bias transistor coupled to a second control signal; a fourth bias transistor connected between the second compensation node and ground, a control terminal of the fourth bias transistor coupled to a first control signal; and a fifth bias transistor connected in diode-connected arrangement between the second compensation node and ground.

3. The operational transconductance amplifier (OTA) of claim 1, characterized in that wherein the constant current source has a control terminal that receives the second control signal; wherein the folded cascode arrangement further comprises within the first folded cascode branch: a fifth tail generator transistor connected between the supply voltage node and a first folded branch node, the fifth tail generator transistor having a control terminal coupled to the second control signal; a first cascode transistor connected between the first folded branch node and a third cascode transistor, the first cascode transistor having a control terminal coupled to a first cascode control signal; a second cascode transistor connected between the first cascode transistor and the third cascode transistor, the second cascode transistor having a control terminal coupled to a third cascode control signal; a third cascode transistor connected between the second cascode transistor and a third folded branch node, the third cascode transistor having a control terminal coupled to a second cascode control signal; and a sixth tail generator transistor connected between the third folded branch node and ground, the sixth tail generator transistor having a control terminal coupled to a node between the second cascode transistor and the third cascode transistor; wherein the folded cascode arrangement further comprises within the second folded cascode branch: a seventh tail generator transistor connected between the supply voltage node and a second folded branch node, the seventh tail generator transistor having a control terminal coupled to the second control signal; a fourth cascode transistor connected between the second folded branch node and the Monticelli cell, the fourth cascode transistor having a control terminal coupled to the first cascode control signal; a fifth cascode transistor connected between the Monticelli cell and a fourth folded branch node, the fifth cascode transistor having a control terminal coupled to the second cascode control signal; and a sixth cascode transistor connected between the fourth folded branch node and ground, the sixth cascode transistor having a control terminal coupled to a node between the fourth cascode transistor and the fifth cascode transistor. a seventh tail generator transistor connected between the fourth folded branch node and ground, the seventh tail generator transistor having a control terminal coupled to a node between the second and third cascode transistors.

4. The operational transconductance amplifier (OTA) of claim 1, characterized in that wherein the first folded branch node is connected to a source of the first cascode transistor, and wherein the second folded branch node is connected to a source of the fourth cascode transistor; wherein the folded cascode arrangement further comprises a first chopper having first and second inputs and first and second outputs, the first chopper configured to chop voltages at the first and second inputs of the first chopper, the first output of the first chopper connected to a drain of the first cascode transistor, the second output of the first chopper connected to a drain of the fourth cascode transistor; wherein the fifth tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper; wherein the first tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper; wherein the seventh tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper; and wherein the third tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper.

5. The operational transconductance amplifier (OTA) of claim 4, characterized in that wherein the third folded branch node is connected to a source of the third cascode transistor, and wherein the fourth folded branch node is connected to a source of the fifth cascode transistor; wherein the folded cascode arrangement further comprises a second chopper having first and second inputs and first and second outputs, the second chopper configured to chop voltages at the first and second inputs of the second chopper, the first output of the second chopper connected to drains of the sixth and second tail generator transistors, the second output of the second chopper connected to drains of the eighth and fourth tail generator transistors; wherein the third cascode transistor has a first conduction terminal connected to the second cascode transistor and a second conduction terminal connected to the first input of the second chopper; wherein the fifth cascode transistor has a first conduction terminal connected to the Monticelli cell and a second conduction terminal connected to the second input of the second chopper.

6. The operational transconductance amplifier (OTA) of claim 1, characterized in that wherein the folded cascode arrangement further comprises a first chopper having first and second inputs and first and second outputs, the first chopper configured to chop voltages at the first and second inputs of the first chopper, the first output of the first chopper connected to a drain of the first cascode transistor, the second output of the first chopper connected to a drain of the fourth cascode transistor; wherein the fifth tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to a first input of the first chopper; wherein the first tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to a first input of the first chopper; wherein the seventh tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to a second input of the first chopper; wherein the third tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to a second input of the first chopper; wherein the folded cascode arrangement further comprises a second chopper having a first input and a second input and a first output and a second output, the second chopper being configured to chop voltages at the first input and the second input of the second chopper, the first output of the second chopper being connected to the drains of the sixth tail generator transistor and the second tail generator transistor, the second output of the second chopper being connected to the drains of the eighth tail generator transistor and the fourth tail generator transistor; wherein the third cascode transistor has a first conduction terminal connected to the second cascode transistor and a second conduction terminal connected to a first input of the second chopper; wherein the fifth cascode transistor has a first conduction terminal connected to the Monticelli cell and a second conduction terminal connected to a second input of the second chopper; and further comprising a third chopper configured to chop the feedback voltage and the input voltage, the chopped feedback voltage being provided to the control terminals of the first input transistor and the third input transistor, and the chopped input voltage being provided to the control terminals of the second input transistor and the fourth input transistor.

7. The operational transconductance amplifier (OTA) of claim 1, characterized in that wherein the constant current source has a control terminal receiving the second control signal; wherein the class AB output stage comprises: a first input coupled to a first output terminal of the Monticelli cell; a second input coupled to a second output terminal of the Monticelli cell; a first output transistor connected between the supply node and an output node, the first output transistor having a control terminal connected to the first input; a second output transistor connected between the output node and ground, the second output transistor having a control terminal connected to the second input; a third output transistor connected between the supply node and a fourth output transistor, the third output transistor having a control terminal connected to the second control signal; a fourth output transistor connected in a diode-coupled configuration between the third output transistor and a first input of the Monticelli cell; a fifth output transistor connected in a diode-coupled configuration between the fourth output transistor and ground; a sixth output transistor connected in a diode-coupled configuration between the supply node and a seventh output transistor; a seventh output transistor connected in a diode-coupled configuration between the sixth output transistor and a second input of the Monticelli cell; and an eighth output transistor connected between the second input of the Monticelli cell and ground.

8. The operational transconductance amplifier (OTA) of claim 7, wherein, The Monticelli cell comprises: a first transistor connected between the first output terminal and the second output terminal, wherein the first transistor has a control terminal connected to a control terminal of the fourth output transistor; and a second transistor connected between the first output terminal and the second output terminal, wherein the second transistor has a control terminal connected to a control terminal of the seventh output transistor.

9. The operational transconductance amplifier (OTA) of claim 7, wherein, The class-AB output stage comprises: a first resistor and a first capacitor connected in series between the first output terminal of the Monticelli cell and the output node; and a second resistor and a second capacitor connected in series between the second output terminal of the Monticelli cell and the output node.

10. The operational transconductance amplifier (OTA) of claim 7, wherein, The class-AB output stage comprises: a first capacitor connected in series between the second folded branch node and the output node; and a second capacitor connected in series between the fourth folded branch node and the output node.

11. An operational transconductance amplifier (OTA) characterized by, comprises: a constant current source p-channel transistor having a source connected to a supply voltage node, a drain connected to the first node, and a gate coupled to a first control voltage; a first input pair of transistors comprising: a first input p-channel transistor having a source connected to the first node, a drain connected to the third folded branch node, and a gate coupled to a feedback voltage; and a second input p-channel transistor having a source connected to the first node, a drain connected to the fourth folded branch node, and a gate coupled to an input voltage; a tail current source n-channel transistor having a drain connected to the second node, a source connected to ground, and a gate connected to the third node; a second input pair of transistors comprising: a first input n-channel transistor having a drain connected to the first folded branch node, a source connected to the second node, and a gate coupled to the feedback voltage; and a second input n-channel transistor having a drain connected to the second folded branch node, a source connected to the second node, and a gate coupled to the input voltage; a first mirror n-channel transistor having a drain and a gate connected to the third node, and a source connected to ground; a second mirror p-channel transistor having a source connected to the first node, a drain connected to the third node, and a gate connected to the fourth node; and a third mirror p-channel transistor having a source connected to the supply voltage node, and a drain and a gate connected to the fourth node. a tail n-channel transistor having a drain connected to the fourth node, a source connected to ground, and a gate coupled to the second control voltage; a bias stage comprising: a first bias p-channel transistor having a source connected to a supply voltage node, a drain connected to a first bias node, and a gate coupled to the first control voltage; a first bias n-channel transistor having a drain connected to the first bias node, a source connected to ground, and a gate coupled to the first bias node; a second bias n-channel transistor having a drain connected to the first bias node, a source connected to ground, and a gate coupled to the second control voltage; a second bias p-channel transistor having a source connected to the supply voltage node, and a drain and a gate connected to a second bias node; and a third bias n-channel transistor having a drain connected to the second bias node, a source connected to ground, and a gate coupled to the third node; a folded cascode arrangement comprising within a first folded cascode branch: a first tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to a first folded branch node, and a gate connected to the second bias node; and a first tail generator n-channel transistor having a drain connected to a third folded branch node, a source connected to ground, and a gate connected to the first bias node; a folded cascode arrangement comprising within a second folded cascode branch: a second tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to a second folded branch node, and a gate connected to the first bias node; a second tail generator n-channel transistor having a drain connected to a fourth folded branch node, a source connected to ground, and a gate connected to the first bias node; and a Monticelli cell coupled between the drain of the second tail generator p-channel transistor and the drain of the second tail generator n-channel transistor; a class AB output stage having an input coupled across the Monticelli cell and an output connected to an output node.

12. The operational transconductance amplifier (OTA) of claim 11, wherein, the folded cascode arrangement further comprising within the first folded cascode branch: a third tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to the first folded branch node, and a gate coupled to the first control voltage; a first cascode p-channel transistor having a source connected to the first folded branch node, a drain, and a gate coupled to a first cascode control signal; and a second cascode p-channel transistor having a source connected to the first folded branch node, a drain, and a gate coupled to a second cascode control signal. a second cascode p-channel transistor having a source connected to a drain of the first cascode p-channel transistor, a drain, and a gate connected to the first cascode control node; a first cascode n-channel transistor having a drain connected to a drain of the second cascode p-channel transistor, a source connected to the third folded branch node, and a gate coupled to the second cascode control signal; and a second cascode n-channel transistor having a drain connected to the third folded branch node, a source connected to ground, and a gate connected to a drain of the second cascode p-channel transistor.

13. The operational transconductance amplifier (OTA) of claim 12, wherein, The folded cascode arrangement further includes within the second folded cascode branch: a third cascode p-channel transistor having a source connected to a supply voltage node, a drain connected to the second folded branch node, and a gate coupled to the first control voltage; a fourth cascode p-channel transistor having a source connected to the second folded branch node, a drain, and a gate connected to the first cascode control signal; a third cascode n-channel transistor having a drain, a source connected to the fourth folded branch node, and a gate coupled to the second cascode control signal; a fourth cascode n-channel transistor having a drain connected to the fourth folded branch node, a source connected to ground, and a gate connected to a drain of the second cascode p-channel transistor; and a Monticelli cell having a first output connected to a drain of the fourth cascode p-channel transistor, a second output connected to a drain of the second cascode n-channel transistor, a first input connected to the first cascode control node, and a second input connected to the second cascode control node.

14. The operational transconductance amplifier (OTA) of claim 13, wherein, Further included are: a first chopper having a first input connected to a drain of the third tail generator p-channel transistor, a second input connected to a drain of the first tail generator p-channel transistor, a first output connected to the first folded branch node, and a second output connected to the second folded branch node; and a second chopper having a first input connected to a source of the first cascode n-channel transistor, a second input connected to a source of the third cascode n-channel transistor, a first output connected to the third folded branch node, and a second output connected to the fourth folded branch node.

15. The operational transconductance amplifier (OTA) of claim 14, wherein, Further included is a third chopper configured to chop a feedback voltage and an input voltage.

16. The operational transconductance amplifier (OTA) of claim 11, wherein, The class AB output stage includes: a first input node connected to the first output of the Monticelli cell; a second input node connected to the second output of the Monticelli cell; a first output p-channel transistor having a source connected to a supply voltage node, a drain connected to an output node, and a gate connected to a first input node; a first output n-channel transistor having a drain connected to the output node, a source connected to ground, and a gate connected to a second input node; a second output p-channel transistor having a source connected to the supply voltage node, a drain connected to a second cascode control node, and a gate coupled to a first control voltage; a second output n-channel transistor having a drain and a gate connected to the second cascode control node, and a source; a third output n-channel transistor having a drain and a gate connected to a source of the second output n-channel transistor, and a source connected to ground; a third output p-channel transistor having a source connected to the supply voltage node, and a gate and a drain; a fourth output p-channel transistor having a source connected to the gate and the drain of the third output p-channel transistor, and a gate and a drain connected to a first cascode control node; and a fourth output n-channel transistor having a drain connected to the first cascode control node, a source connected to ground, and a gate coupled to a second control voltage.

17. The operational transconductance amplifier (OTA) of claim 16, wherein, The class AB output stage further includes: a first resistor and a first capacitor connected in series between the first output of the Monticelli cell and the output node; and a second resistor and a second capacitor connected in series between the second output of the Monticelli cell and the output node.

18. The operational transconductance amplifier (OTA) of claim 16, wherein, The class AB output stage further includes: a first capacitor connected in series between the second folded leg node and the output node; and a second capacitor connected in series between the fourth folded leg node and the output node.

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