Signal acquisition circuit and electronic equipment

Abstract

The utility model relates to a signal acquisition circuit and electronic equipment. The signal acquisition circuit comprises a control chip and at least one signal acquisition unit, wherein the signal acquisition unit comprises a reference voltage generation circuit and a sampling circuit. The reference voltage generation circuit is used for outputting reference voltage. The sampling circuit is used for accessing an analog voltage signal and outputting a sampling voltage corresponding to the analog voltage signal. And the control chip is connected with the sampling circuit and the reference voltage generation circuit, and is used for adjusting the sampling voltage output by the sampling circuit according to a comparison result of the sampling voltage and the reference voltage, and outputting a digital signal corresponding to the analog voltage signal under the condition that the sampling voltage is matched with the reference voltage. Therefore, each path of signal acquisition unit can access one path of analog voltage signal, and the analog voltage signal is processed in parallel through the control chip. In a scene with a high requirement for signal acquisition synchronism, the signal acquisition circuit can process analog-to-digital conversion of a plurality of analog voltage signals in parallel, and the requirement for high-synchronism signal acquisition is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a signal acquisition circuit and electronic equipment. BACKGROUND

[0002] In the design of electronic circuit, analog voltage signal acquisition is usually sampled by an ADC (Analog-to-Digital Converter) module, and the ADC module outputs a digital signal corresponding to the analog voltage signal to the back end for relevant analysis or calculation.

[0003] The ADC module is usually integrated in a controller, and in some cases, the ADC sampling channel resources of the controller are relatively scarce. In order to increase the number of ADC sampling channels, the conventional technology controls the switching of external analog inputs by a logic device, multiplexes the ADC sampling channels of the controller, and realizes the expansion of the ADC sampling channels.

[0004] However, the multiplexing of the ADC sampling channels of the controller has a time difference between channels, and in the case where the signal acquisition synchronization requirement is high, it has the limitation of low signal acquisition synchronization. UTILITY MODEL CONTENT

[0005] Therefore, it is necessary to provide a signal acquisition circuit and electronic equipment for improving signal acquisition synchronization in view of the above problems.

[0006] A signal acquisition circuit, comprising: a control chip and at least one signal acquisition unit, wherein the signal acquisition unit comprises a reference voltage generation circuit and a sampling circuit;

[0007] The reference voltage generation circuit is configured to output a reference voltage.

[0008] The sampling circuit is configured to access an analog voltage signal and output a sampling voltage corresponding to the analog voltage signal.

[0009] The control chip is connected to the sampling circuit and the reference voltage generation circuit, and is configured to adjust the sampling voltage output by the sampling circuit according to the comparison result of the sampling voltage and the reference voltage, and output a digital signal corresponding to the analog voltage signal when the sampling voltage matches the reference voltage.

[0010] In one embodiment, the signal acquisition unit further comprises a comparison circuit, wherein

[0011] The reference voltage generation circuit is connected to a first input end of the comparison circuit, the sampling circuit is connected to a second input end of the comparison circuit, and the control chip is connected to an output end of the comparison circuit; and the control chip is further connected to the sampling circuit.

[0012] In one of the embodiments, the comparison circuit comprises a comparator; the reference voltage generation circuit is connected to a non-inverting input end of the comparator, the sampling circuit is connected to an inverting input end of the comparator, and the control chip is connected to an output end of the comparator.

[0013] In one of the embodiments, the control chip comprises:

[0014] A comparison module is connected to the sampling circuit and the reference voltage generation circuit, and is configured to compare the sampling voltage and the reference voltage and output a corresponding comparison result.

[0015] A filtering module is connected to the comparison module and the sampling circuit, and is configured to output a feedback signal to the sampling circuit according to the comparison result, so as to adjust the sampling voltage, and output a digital signal corresponding to the analog voltage signal according to the feedback signal in the case that the sampling voltage matches the reference voltage.

[0016] In one of the embodiments, the sampling circuit comprises a first sampling resistor and a second sampling resistor; a first end of the first sampling resistor is configured to access the analog voltage signal, a second end of the first sampling resistor is connected to a first end of the second sampling resistor, and a second end of the second sampling resistor is connected to the control chip; and a common end of the first sampling resistor and the second sampling resistor is configured to output the sampling voltage.

[0017] In one of the embodiments, the control chip is configured to output a feedback signal of a PWM waveform to the second end of the second sampling resistor, so as to adjust the sampling voltage, and output a digital signal corresponding to the analog voltage signal according to a duty ratio of the feedback signal in the case that the sampling voltage matches the reference voltage.

[0018] In one of the embodiments, the sampling circuit further comprises a capacitor, a first end of the capacitor is connected to the first end of the second sampling resistor, and a second end of the capacitor is grounded.

[0019] In one of the embodiments, the reference voltage generation circuit comprises a first voltage dividing resistor and a second voltage dividing resistor; a first end of the first voltage dividing resistor is configured to be connected to a power voltage input end, and a second end of the first voltage dividing resistor is connected to ground through the second voltage dividing resistor; and a common end of the first voltage dividing resistor and the second voltage dividing resistor is configured to output the reference voltage.

[0020] In one of the embodiments, the control chip is an FPGA chip or a CPLD chip.

[0021] An electronic device comprising the signal acquisition circuit as described above.

[0022] The signal acquisition circuit and the electronic device as described above, comprising a control chip and at least one signal acquisition unit, the signal acquisition unit comprising a reference voltage generation circuit and a sampling circuit. The reference voltage generation circuit is configured to output a reference voltage. The sampling circuit is configured to access an analog voltage signal and output a sampling voltage corresponding to the analog voltage signal. The control chip is connected to the sampling circuit and the reference voltage generation circuit, configured to adjust the sampling voltage output by the sampling circuit according to the comparison result of the sampling voltage and the reference voltage, and output a digital signal corresponding to the analog voltage signal in the case that the sampling voltage matches the reference voltage. Thus, each signal acquisition unit can access an analog voltage signal and be processed in parallel by the control chip. Therefore, in the case that the signal acquisition synchronization requirement is high, the signal acquisition circuit can process the analog-digital conversion of multiple analog voltage signals in parallel, meeting the demand of high-synchronization signal acquisition. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A module schematic diagram of the signal acquisition circuit in one embodiment;

[0024] Figure 2 A module schematic diagram of the signal acquisition circuit in another embodiment;

[0025] Figure 3 A module schematic diagram of the signal acquisition circuit in yet another embodiment;

[0026] Figure 4 A module schematic diagram of the signal acquisition circuit in yet another embodiment;

[0027] Figure 5 A circuit structure schematic diagram of the signal acquisition circuit in one embodiment. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0030] It can be understood that the terms "first", "second" and the like used in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. For example, without departing from the scope of the present application, a first resistor can be called a second resistor, and similarly, a second resistor can be called a first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0031] It can be understood that "connection" in the following embodiments should be understood as "electrical connection", "communication connection" and the like if the circuits, modules, units and the like connected by the connection have transmission of electrical signals or data between each other.

[0032] It can be understood that "at least one" means one or more, and "multiple" means two or more. "At least part of the element" means part or all of the element.

[0033] As used herein, the singular forms "a", "an" and "the" can also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprise / comprising" or "have / having" specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in the present specification includes any and all combinations of the related listed items.

[0034] In one embodiment, a signal acquisition circuit is provided. As shown in Figure 1 The signal acquisition circuit includes a control chip 100 and at least one signal acquisition unit 200.

[0035] Specifically, the signal acquisition unit 200 is connected to the IO (Input / Output) port of the control chip 100. Thus, in the case of the ADC port resource of the control chip 100 being tight, the number of ADC sampling channels is increased through the IO port.

[0036] The number of signal acquisition units 200 needs to be determined according to the specific needs in the actual application scenario. Exemplarily, the number of signal acquisition units 200 is determined according to the number of analog signals (VIN1-VINn) to be processed and the number of idle IO ports available to the control chip 100.

[0037] The sampling result of the signal acquisition unit 200 is transmitted to the control chip 100, the control chip 100 processes the output signal of each signal acquisition unit 200, and feeds back the control signal acquisition unit 200 according to the processing result, so as to obtain the digital signal (DOUT1-DOUTn) corresponding to each analog signal. Thus, parallel acquisition and conversion processing of multiple analog signals can be realized, and the demand for high synchronization signal acquisition can be met.

[0038] In some embodiments, referring to Figure 2 , the signal acquisition unit 200 includes a reference voltage generation circuit 210 and a sampling circuit 220. The reference voltage generation circuit 210 is used to output a reference voltage Vref. The sampling circuit 220 is used to access an analog voltage signal VIN and output a sampling voltage corresponding to the analog voltage signal VIN.

[0039] The control chip 100 is connected to the reference voltage generation circuit 210 and the sampling circuit 220. It can be understood that the control chip 100 can be directly or indirectly connected to the reference voltage generation circuit 210, and can be directly or indirectly connected to the sampling circuit 220. Figure 2 For example, the control chip 100 is directly connected to the reference voltage generation circuit 210 and the sampling circuit 220, wherein the reference voltage generation circuit 210 is connected to the IO3 port of the control chip 100, and the sampling circuit 220 is connected to the IO1 port and the IO2 port of the control chip 100.

[0040] The control chip 100 is used to adjust the sampling voltage output by the sampling circuit 220 according to the comparison result of the sampling voltage and the reference voltage Vref, and output the digital signal DOUT corresponding to the analog voltage signal VIN in the case that the sampling voltage matches the reference voltage Vref. Wherein, the sampling voltage matches the reference voltage Vref can be that the sampling voltage and the reference voltage Vref are equal, or that the difference between the two is within a certain range.

[0041] Specifically, the control chip 100 includes a filtering module, which is used to process (for example, accumulate statistics and sum average) the comparison result of the sampling voltage and the reference voltage Vref, obtain a feedback signal, and output the feedback signal to the sampling circuit 220 through the IO2 port to adjust the sampling voltage output by the sampling circuit 220. The filtering module is also used to calculate the voltage value of the analog voltage signal VIN according to the feedback signal in the case that the sampling voltage matches the reference voltage Vref, and output the corresponding digital signal DOUT, realizing the ADC function.

[0042] The control chip 100 is a chip with parallel processing capability. In some application scenarios, the control chip 100 can be an FPGA (Field-Programmable Gate Array) chip. The FPGA chip is a highly flexible and programmable hardware chip, and the designer can configure the internal logic circuit according to the specific requirements to realize a specific function. Using the FPGA chip as the control chip 100 can exert its powerful parallel processing capability and meet the processing requirements of a complex system.

[0043] In other scenarios, the control chip 100 can also be a CPLD (Complex Programmable Logic Device) chip. The CPLD chip has higher integration and lower cost, and also has parallel processing capability, and is suitable for a control system with certain cost requirements. In other application scenarios, the control chip 100 can also select other types of processor chips with parallel processing capability, which are not limited in the embodiment.

[0044] The signal acquisition circuit includes the control chip 100 and at least one signal acquisition unit 200. The signal acquisition unit 200 includes a reference voltage generation circuit 210 and a sampling circuit 220. The reference voltage generation circuit 210 is configured to output a reference voltage Vref. The sampling circuit 220 is configured to access an analog voltage signal VIN and output a sampling voltage corresponding to the analog voltage signal VIN. The control chip 100 is connected to the sampling circuit 220 and the reference voltage generation circuit 210, and is configured to adjust the sampling voltage output by the sampling circuit 220 according to a comparison result of the sampling voltage and the reference voltage Vref, and output a digital signal DOUT corresponding to the analog voltage signal VIN in a case where the sampling voltage matches the reference voltage Vref. Thus, each signal acquisition unit 200 can access an analog voltage signal and be processed in parallel by the control chip 100. Therefore, in a scenario where the signal acquisition synchronization requirement is high, the signal acquisition circuit can process the analog-digital conversion of multiple analog voltage signals in parallel, and meet the requirement of high-synchronization signal acquisition.

[0045] In some embodiments, as shown in FIG. 1, the control chip 100 includes a comparison module 110 and a filtering module 120. Figure 3

[0046] The comparison module 110 is connected to the sampling circuit 220 and the reference voltage generation circuit 210, and is configured to compare the sampling voltage and the reference voltage Vref and output a corresponding comparison result.

[0047] ​The filter module 120 is connected to the comparison module 110 and the sampling circuit 220. It is used to output a feedback signal to the sampling circuit 220 according to the comparison result to adjust the sampling voltage. When the sampling voltage matches the reference voltage Vref, it outputs the digital signal DOUT corresponding to the analog voltage signal VIN according to the feedback signal.

[0048] In this embodiment, the control chip 100 is directly connected to the sampling circuit 220 and the reference voltage generation circuit 210 via I / O ports. The comparison module 110 and the filtering module 120 inside the control chip 100 compare the sampled voltage and the reference voltage Vref, calculate the voltage value of the analog voltage signal VIN, and finally output the digital signal DOUT corresponding to the analog voltage signal VIN. Thus, the ADC port resources are increased using I / O ports, resulting in a simple circuit structure that is easy to implement.

[0049] It should be noted that when the ADC port resources of the control chip 100 are scarce, external ADC chips are often used to expand the number of ADC sampling channels in related technologies. However, for cost-sensitive scenarios, increasing ADC resources by adding ADC chips will significantly increase costs.

[0050] In this embodiment, both the sampling circuit 220 and the reference voltage generation circuit 210 can be implemented using analog devices, which is low-cost and can meet the expansion requirements of ADC sampling channels in cost-sensitive scenarios.

[0051] In some embodiments, such as Figure 4 As shown, the signal acquisition unit 200 also includes a comparison circuit 230. A reference voltage generation circuit 210 is connected to the first input terminal of the comparison circuit 230, a sampling circuit 220 is connected to the second input terminal of the comparison circuit 230, and a control chip 100 is connected to the output terminal of the comparison circuit 230. The control chip 100 is also connected to the sampling circuit 220.

[0052] The control chip 100 is indirectly connected to the reference voltage generation circuit 210 and the sampling circuit 220 through the comparison circuit 230. The comparison circuit 230 receives and compares the sampled voltage and the reference voltage Vref, and outputs the corresponding comparison result to the control chip 100.

[0053] The control chip 100 is also directly connected to the sampling circuit 220. After receiving the comparison result output by the comparison circuit 230, it outputs a feedback signal to the sampling circuit 220 according to the comparison result to adjust the sampling voltage. When the sampling voltage matches the reference voltage Vref, it outputs the digital signal DOUT corresponding to the analog voltage signal VIN according to the feedback signal.

[0054] In this embodiment, the control chip 100 only needs to occupy two IO ports to realize the collection and conversion of one analog signal, which significantly reduces the occupation of the IO resources of the control chip 100, and further improves the flexibility of the circuit.

[0055] The implementation of the comparison circuit 230 is not unique. In some embodiments, the comparison circuit 230 includes a comparator U1. The reference voltage generation circuit 210 is connected to the non-inverting input end IN+ of the comparator U1, the sampling circuit 220 is connected to the inverting input end IN- of the comparator U1, and the control chip 100 is connected to the output end of the comparator U1.

[0056] The comparator U1 is used to compare the amplitudes of the sampling voltage and the reference voltage Vref, and output the comparison result to the control chip 100. Since the comparator has accurate comparison and output capabilities, the subsequent processing and calculation results of the control chip 100 are more accurate and reliable, thereby improving the reliability of the output.

[0057] In other embodiments, the comparison circuit 230 can also be implemented in the form of an operational amplifier or a combination of logic circuits, and those skilled in the art can refer to the commonly used technologies in the art for setting, as long as the corresponding functions described above are realized.

[0058] In some embodiments, as shown in FIG. 2B, the sampling circuit 220 includes a first sampling resistor R1 and a second sampling resistor R2. The first end of the first sampling resistor R1 is used to access the analog voltage signal VIN, the second end of the first sampling resistor R1 is connected to the first end of the second sampling resistor R2, and the second end of the second sampling resistor R2 is connected to the control chip 100. The common end connected by the first sampling resistor R1 and the second sampling resistor R2 is used to output the sampling voltage. Figure 5

[0059] Figure 5 In the embodiment shown in FIG. 2B, the common end connected by the first sampling resistor R1 and the second sampling resistor R2 is connected to the inverting input end IN- of the comparator U1, the reference voltage generation circuit 210 is connected to the non-inverting input end IN+ of the comparator U1, and the sampling voltage and the reference voltage Vref are compared through the comparator U1. The output end of the comparator U1 is connected to one IO port (illustrated as IO1 port) of the control chip 100, and the second end of the second sampling resistor R2 is connected to another IO port (illustrated as IO2 port) of the control chip 100.

[0060] ​The filter module in the control chip 100 accumulates and averages the comparison results output by the comparator U1, obtains a feedback signal, and outputs the feedback signal to the second end of the second sampling resistor R2 through the IO2 port to adjust the voltage at the common end connected by the first sampling resistor R1 and the second sampling resistor R2 (i.e., the sampling voltage). The filter module can dynamically adjust the sampling voltage by dynamically adjusting the feedback signal. When the sampling voltage matches the reference voltage Vref, the voltage value of the analog voltage signal VIN is calculated according to the feedback signal, and the corresponding digital signal DOUT is output, realizing the ADC function.

[0061] In some scenarios, the sampling circuit 220 and the reference voltage generation circuit 210 are directly connected to the control chip 100. In this case, the common end connected by the first sampling resistor R1 and the second sampling resistor R2 is connected to one IO port (e.g., the IO1 port) of the control chip 100, and the second end of the second sampling resistor R2 is connected to another IO port (e.g., the IO2 port) of the control chip 100. The reference voltage generation circuit 210 is connected to another IO port (e.g., the IO3 port) of the control chip 100. At this time, the comparison module and the filter module inside the control chip 100 work together to realize the ADC function.

[0062] The first sampling resistor R1 and the second sampling resistor R2 can be implemented by resistance elements or equivalent circuits, and the resistance values of the first sampling resistor R1 and the second sampling resistor R2 do not need to be limited, which can be set according to specific conditions by those skilled in the art.

[0063] In this embodiment, by using the first sampling resistor R1 and the second sampling resistor R2 for voltage division sampling, the sampling value of the analog voltage signal VIN can be more accurately obtained, and the sampling signal can be adjusted according to the feedback signal, and the circuit is flexible. In actual implementation, by adjusting the resistance values of the two resistors, the voltage division ratio of the sampling circuit can be changed to adapt to different input voltage ranges and sampling requirements.

[0064] In some embodiments, the control chip 100 is configured to output a feedback signal of a PWM (Pulse Width Modulation) waveform to the second end of the second sampling resistor R2 to adjust the sampling voltage, and output a digital signal DOUT corresponding to the analog voltage signal VIN according to the duty cycle of the feedback signal when the sampling voltage matches the reference voltage Vref.

[0065] In this embodiment, the feedback signal output by the control chip 100 is a PWM signal. When the duty cycle of the PWM signal changes, the voltage at the common terminal connected by the first sampling resistor R1 and the second sampling resistor R2 can be changed, thereby adjusting the sampling voltage. This adjustment mechanism enables the sampling voltage to gradually approach the reference voltage Vref. When the DC levels of points b (the non-inverting input terminal IN+ of the comparator U1) and c (the inverting input terminal IN- of the comparator U1) are equal, the balance state is reached, and the filter module can convert the analog voltage signal VIN into a digital signal DOUT according to the duty cycle of the feedback signal to realize the ADC function.

[0066] In some embodiments, as shown in FIG. 2, the sampling circuit further includes a capacitor C. A first end of the capacitor C is connected to a first end of the second sampling resistor R2, and a second end of the capacitor C is grounded. Figure 5

[0067] The capacitor C can filter out small fluctuations in the DC signal, making the sampling voltage more stable, thereby improving the sampling accuracy, and further improving the accuracy of analog-to-digital conversion and the anti-interference ability of the circuit.

[0068] The structure of the reference voltage generation circuit 210 is not unique. In some embodiments, the reference voltage generation circuit 210 includes a first voltage dividing resistor R3 and a second voltage dividing resistor R4. A first end of the first voltage dividing resistor R3 is used to connect a power voltage input terminal to access a power voltage VCCIO. A second end of the first voltage dividing resistor R3 is grounded through the second voltage dividing resistor R4. The common terminal connected by the first voltage dividing resistor R3 and the second voltage dividing resistor R4 is used to output the reference voltage Vref.

[0069] Figure 5 In the embodiment shown in FIG. 2, the common terminal connected by the first voltage dividing resistor R3 and the second voltage dividing resistor R4 is connected to the non-inverting input terminal IN+ of the comparator U1. In the scenario where the reference voltage generation circuit 210 is directly connected to the control chip 100, the common terminal connected by the first voltage dividing resistor R3 and the second voltage dividing resistor R4 is connected to an IO port (e.g., the IO3 port) of the control chip 100. At this time, the ADC function is realized by the cooperative action of the comparison module and the filter module inside the control chip 100.

[0070] ​In this embodiment, the first voltage dividing resistor R3 and the second voltage dividing resistor R4 form a voltage dividing structure, and the common end connected by the two outputs a voltage after voltage division, that is, the reference voltage Vref. The size of the reference voltage Vref depends on the resistance values of the first voltage dividing resistor R3 and the second voltage dividing resistor R4 and the size of the power supply voltage VCCIO. In actual applications, the size of the reference voltage Vref can be flexibly set by adjusting the resistance values of the first voltage dividing resistor R3 and the second voltage dividing resistor R4. This flexible setting mode enables the reference voltage generation circuit 210 to adapt to different application requirements and improves the flexibility of the signal acquisition circuit.

[0071] The reference voltage generation circuit 210 is composed of the first voltage dividing resistor R3 and the second voltage dividing resistor R4, has a simple circuit structure, requires fewer components, and all are common resistor components, so that the signal acquisition circuit has a significant advantage in cost.

[0072] The power supply voltage VCCIO can be the same as or different from the power supply signal VCC connected to the comparator U1. In some embodiments, the power supply pin of the control chip 100 is connected to the power supply voltage input end to access the power supply voltage VCCIO.

[0073] By using the same power supply voltage VCCIO to power the reference voltage generation circuit 210 and the control chip 100, on the one hand, the number of introduced power supplies can be reduced, and the circuit structure can be simplified; on the other hand, when calculating the reference voltage Vref, the control chip 100 can simplify the calculation amount and improve the processing speed.

[0074] In other embodiments, the reference voltage generation circuit 210 can also use a reference voltage source or a special chip structure, and those skilled in the art can select according to specific conditions.

[0075] In order to better understand the above embodiments, the following will be explained in detail in combination with an optional embodiment.

[0076] In a conventional circuit, an analog signal is usually sampled by an ADC module in a controller, so as to output a digital signal to a back end for related analysis or calculation. However, in a certain cost condition, the ADC resources of the controller are relatively scarce. In order to increase the number of ADC sampling channels, an external ADC chip is usually used to expand the ADC sampling channels in related technologies, or the input of an external analog quantity is switched by a logic device to realize the multiplexing of the ADC channels and the expansion of the ADC sampling channels.

[0077] However, in a cost-sensitive scenario, increasing the ADC resources by increasing the ADC chip will increase the cost. Multiplexing the ADC channels will cause a time difference in the processing of each signal, and in some high-synchronization scenarios, this signal acquisition mode has limitations.

[0078] To solve the above problems, the application provides a signal acquisition circuit capable of improving signal acquisition synchronization, which can increase the ADC resources of an FPGA chip or a CPLD chip, is simple in circuit and low in use cost. Meanwhile, the signal acquisition circuit can avoid the problem of inconsistent signal acquisition caused by the ADC multiplexing mode.

[0079] In an optional embodiment, the signal acquisition circuit includes a control chip and a signal acquisition unit, as shown in FIG. 2. Figure 5 The signal acquisition unit includes a reference voltage generation circuit 210, a sampling circuit 220 and a comparator U1. Specifically, the reference voltage generation circuit 210 includes a first voltage dividing resistor R3 and a second voltage dividing resistor R4. The first end of the first voltage dividing resistor R3 is used to connect a power voltage input end to access a power voltage VCCIO. The second end of the first voltage dividing resistor R3 is grounded through the second voltage dividing resistor R4. The common end of the first voltage dividing resistor R3 and the second voltage dividing resistor R4 is used to output a reference voltage Vref. The sampling circuit 220 includes a first sampling resistor R1 and a second sampling resistor R2. The first end of the first sampling resistor R1 is used to access an analog voltage signal VIN, and the second end of the first sampling resistor R1 is connected to the first end of the second sampling resistor R2. The second end of the second sampling resistor R2 is connected to the IO2 port of the control chip 100. The common end of the first sampling resistor R1 and the second sampling resistor R2 is used to output a sampling voltage.

[0080] The common end of the first sampling resistor R1 and the second sampling resistor R2 is connected to the inverting input end IN- of the comparator U1, and the reference voltage generation circuit 210 is connected to the non-inverting input end IN+ of the comparator U1. The output end of the comparator U1 is connected to the IO1 port of the control chip 100.

[0081] The comparator U1 compares the sampling voltage and the reference voltage Vref and outputs the comparison result to the control chip 100. The control chip 100 collects and judges the output value of the comparator U1 through the IO1 port and outputs a PWM waveform as a feedback signal through the IO2 port.

[0082] The control chip 100 further includes a filter module composed of internal software logic, which realizes the functions of accumulation statistics and summation average of the output value of the comparator U1, obtains the output PWM duty ratio, and finally calculates the input voltage value according to the size of the duty ratio to realize the ADC function.

[0083] In this embodiment, the matching of the sampling voltage and the reference voltage Vref can be that the direct current voltages at the non-inverting input end IN+ and the inverting input end IN- of the comparator U1 are equal, reaching a balanced state.

[0084] Specifically, the control chip 100 can be an FPGA chip, the power supply voltage VCCIO is a power supply voltage of the FPGA chip, VIN is an input analog voltage signal, Vref is a reference voltage input to the positive terminal (IN+ pin) of the comparator U1, IO1 and IO2 are input / output pins of the FPGA chip, and PWM_out is a feedback signal output by the IO2 port.

[0085] When a divided voltage signal (i.e., a sampling voltage) of the analog voltage signal VIN is input from the negative terminal (IN- pin) of the comparator U1, the IO1 port of the chip collects and judges the comparison value output by the comparator U1, and outputs a feedback signal of a PWM waveform to the negative terminal of the comparator U1 through the IO2 port, so that the direct current levels of points b and c are equal, and a balance state is reached.

[0086] If the maximum value of the analog voltage signal VIN is denoted as VINmax, the minimum swing is 0, PWM_duty is the negative duty cycle of the feedback signal PWM_out, and the output swing of the feedback signal PWM_out is the power supply voltage VCCIO, when the feedback circuit composed of the first sampling resistor R1, the second sampling resistor R2, and the capacitor C reaches a balance state, the levels of points b and c are equal, and the level of point d is equivalent to VCCIO*PWM_duty.

[0087] When the analog voltage signal VIN is the maximum value VINmax, PWM_duty is the minimum value 0, and the voltage of point d is 0, the following formula is satisfied:

[0088] VINmax=Vref / R2*(R1+R2) (1);

[0089] wherein Vref represents the reference voltage, R1 represents the resistance value of the first sampling resistor R1, and R2 represents the resistance value of the second sampling resistor R2.

[0090] When the analog voltage signal VIN is the minimum value 0, PWM_duty is the maximum value 1, and the voltage of point d is the maximum value, the following formula is satisfied:

[0091] Vref=VCCIO*R1 / (R1+R2) (2);

[0092] When the feedback circuit is dynamically balanced, the following formula can be obtained according to Ohm's law:

[0093] VIN=Vref+(Vref-VCCIO*PWM_duty) / R2*R1 (3);

[0094] The following formula can be obtained by transforming equation (3):

[0095] VIN = vref / R2*(R1+R2) - VCCIO*R1 / R2*PWM_duty (4)

[0096] As can be seen from equation (4), the reference voltage Vref, the resistance value of the first sampling resistor R1, the resistance value of the second sampling resistor R2, and the power supply voltage VCCIO are constant values, and thus the size of the analog voltage signal VIN can be calculated through PWM_duty.

[0097] PWM_duty is the negative duty cycle (i.e., the ratio of low-level time to the entire cycle time) of the feedback signal PWM_out, which is obtained by sampling the output value of the comparator U1 through a software filter module, averaging the cumulative value, and expressed as a digital quantity with a bit width of DATA_width, for example, swing_out. The relationship between swing_out and PWM_duty can be expressed as follows:

[0098] swing_out = 2^DATA_width - pwm_duty*2^DATA_width (5)

[0099] Substituting equation (5) into equation (4) gives:

[0100] VIN = vref / R2*(R1+R2) - VCCIO*R1 / R2*(2^DATA_width - swing_out) / 2^DATA_width (6)

[0101] Suppose R1 = 40kΩ, R2 = 10kΩ, vref = 2.7V, VCCIO = 3.3V, and swing_out = 227, DATA_WIDTH = 8. The analog voltage signal VIN can be calculated through equation (6) as follows:

[0102] VIN = 2.7*(40+10) / 10 - 3.3*40 / 10*(256 - 227) / 256 = 13.5 - 1.449 = 12.05 (V).

[0103] As can be seen from the above derivation, there is a certain linear relationship between the input analog quantity (analog voltage signal VIN) and the digital quantity swing_out, and ultimately the ADC function can be realized to convert the analog quantity into a digital quantity.

[0104] The signal acquisition circuit can simultaneously convert multiple input analog quantities into digital quantities, realize ADC function, and expand chip ADC resources. The circuit has simple structure and low cost, and can expand more ADC channels with less cost without using external ADC sampling chips. The signal acquisition circuit can process multiple analog voltage signals in parallel, thereby avoiding inconsistent sampling signals, and can meet the demand for high-synchronization signal acquisition in a high-synchronization signal acquisition scenario.

[0105] Based on the same concept, the embodiments of the present application also provide an electronic device. The electronic device includes any one of the signal sampling circuits provided by the above embodiments.

[0106] Since the electronic device includes the signal sampling circuit provided by the embodiments of the present application, the electronic device also has the beneficial effects of the signal sampling circuit in the above embodiments, and the same parts can be understood by referring to the above explanation and description of the signal sampling circuit, which will not be repeated here.

[0107] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0108] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the utility model patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A signal acquisition circuit, characterized by comprising: The signal acquisition circuit comprises a control chip and at least one signal acquisition unit, wherein the signal acquisition unit comprises a reference voltage generation circuit and a sampling circuit. The reference voltage generation circuit is configured to output a reference voltage. The sampling circuit is configured to access an analog voltage signal and output a sampling voltage corresponding to the analog voltage signal. The control chip is connected to the sampling circuit and the reference voltage generation circuit, and is configured to adjust the sampling voltage output by the sampling circuit according to a comparison result of the sampling voltage and the reference voltage, and output a digital signal corresponding to the analog voltage signal when the sampling voltage matches the reference voltage. The signal acquisition unit further comprises a comparison circuit; wherein 2. The signal acquisition circuit of claim 1, wherein, The reference voltage generation circuit is connected to a first input end of the comparison circuit, the sampling circuit is connected to a second input end of the comparison circuit, and the control chip is connected to an output end of the comparison circuit; and the control chip is further connected to the sampling circuit. The comparison circuit comprises a comparator; the reference voltage generation circuit is connected to a non-inverting input end of the comparator, the sampling circuit is connected to an inverting input end of the comparator, and the control chip is connected to an output end of the comparator.

3. The signal acquisition circuit of claim 2, wherein, The control chip comprises:

4. The signal acquisition circuit of claim 1, wherein, a comparison module connected to the sampling circuit and the reference voltage generation circuit, configured to compare the sampling voltage and the reference voltage and output a corresponding comparison result; a filtering module connected to the comparison module and the sampling circuit, configured to output a feedback signal to the sampling circuit according to the comparison result to adjust the sampling voltage, and output a digital signal corresponding to the analog voltage signal according to the feedback signal when the sampling voltage matches the reference voltage. The sampling circuit comprises a first sampling resistor and a second sampling resistor; a first end of the first sampling resistor is configured to access the analog voltage signal, a second end of the first sampling resistor is connected to a first end of the second sampling resistor, and a second end of the second sampling resistor is connected to the control chip; and a common end of the first sampling resistor and the second sampling resistor is configured to output the sampling voltage.

5. The signal acquisition circuit of claim 1, wherein, The control chip is configured to output a feedback signal of a PWM waveform to the second end of the second sampling resistor to adjust the sampling voltage, and output a digital signal corresponding to the analog voltage signal according to a duty cycle of the feedback signal when the sampling voltage matches the reference voltage.

6. The signal acquisition circuit of claim 5, wherein, The sampling circuit further comprises a capacitor, a first end of the capacitor is connected to the first end of the second sampling resistor, and a second end of the capacitor is grounded.

7. The signal acquisition circuit of claim 5, wherein, The reference voltage generation circuit comprises a first voltage dividing resistor and a second voltage dividing resistor; a first end of the first voltage dividing resistor is configured to be connected to a power voltage input end, a second end of the first voltage dividing resistor is connected to ground through the second voltage dividing resistor; and a common end of the first voltage dividing resistor and the second voltage dividing resistor is configured to output the reference voltage.

8. The signal acquisition circuit of claim 1, wherein, The control chip is an FPGA chip or a CPLD chip.

9. The signal acquisition circuit of any one of claims 1-8, wherein, The signal acquisition circuit according to any one of claims 1-9.

10. An electronic device, comprising: The signal acquisition circuit according to any one of claims 1-9. ​

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