TSN network switch with Ethernet port rate compatible with 1Gbps and 2.5 Gbps

Abstract

The utility model discloses a TSN network switch with Ethernet network port rate compatible with 1Gbps and 2.5 Gbps, which belongs to the technical field of network switches and comprises a programmable logic device, the programmable logic device comprises an Ethernet port processing module and an Ethernet PCS / PMA module, and the Ethernet port processing module is connected with the Ethernet PCS / PMA module. And the Ethernet port processing module is connected with the Ethernet PCS / PMA module through a data bus and a configuration bus. According to the TSN network switch with the Ethernet network port rate compatible with 1Gbps and 2.5 Gbps, through a link state reporting module, a link detection module and a dynamic configuration module in the Ethernet port processing module, the state is established according to a dynamic detection link, a dynamic configuration mode is adopted, IP network port rate related parameters of a 1G / 2.5 G Ethernet PCS / PMA module in an FPGA are modified, a clock phase-locked loop and a channel phase-locked loop are matched, and the Ethernet network port rate compatible with 1Gbps and 2.5 Gbps is realized. Compared with an existing device, the device has the advantages that the problem that the network port rate of TSN Ethernet switch equipment is not compatible with 1Gbps and 2.5 Gbps is solved, and the practicability and convenience of the device are improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to network switch technical field especially relates to a TSN network switch of Ethernet network interface rate compatible 1Gbps and 2.5Gbps. BACKGROUND

[0002] Ethernet switch is the key equipment of computer, Ethernet network card, router and other network equipment in LAN, is responsible for the forwarding of network data packet, broadcast processing and collision domain isolation, effectively improves network performance and management efficiency. TSN series switch is a new generation of industrial Ethernet switch, provides completely determined real-time communication through TSN network technology, guarantees the delivery of time-sensitive data, and TSN industrial switch is suitable for the application of strict determinacy requirement to communication delay.

[0003] The network interface rate characteristics of the existing TSN Ethernet switch equipment are incompatible with 1Gbps and 2.5Gbps, which is not convenient for use in 1G and 2.5G mixed use LAN scene.

[0004] Therefore, the utility model provides a TSN network switch of Ethernet network interface rate compatible 1Gbps and 2.5Gbps to solve the above problems. CONTENT OF UTILITY MODEL

[0005] The utility model discloses a TSN network switch of Ethernet network interface rate compatible 1Gbps and 2.5Gbps to solve the problem of the network interface rate of the traditional TSN network switch in the prior art being incompatible with 1Gbps and 2.5Gbps.

[0006] In order to achieve the above object, the utility model adopts the following technical scheme:

[0007] A TSN network switch of Ethernet network interface rate compatible 1Gbps and 2.5Gbps, including programmable logic device, the programmable logic device includes Ethernet port processing module and Ethernet PCS PMA module, the Ethernet port processing module is connected with Ethernet PCS PMA module through data bus and configuration bus;

[0008] The Ethernet PCS PMA module includes reset module, clock control module, shared clock resource module and 1G 2.5G Ethernet PCS PMA module, and the Ethernet port processing module includes link state reporting module, link detection module and dynamic configuration module;

[0009] The shared clock resource module is provided with a clock phase-locked loop, the 1G / 2.5G Ethernet PCS / PMA module is provided with a channel phase-locked loop, the dynamic configuration module cooperates with a link detection module to modify the 1G / 2.5G Ethernet PCS / PMA module IP network port rate related parameters in the FPGA, and the dynamic configuration module configures the clock phase-locked loop and the channel phase-locked loop parameters through a DRP bus.

[0010] Preferably, the programmable logic device is an Xilinx Zynq series FPGA, the programmable logic device further comprises an embedded software processing module, a message switching matrix module and a TSN protocol processing module, the message switching matrix module is connected with the embedded software processing module and the TSN protocol processing module through a data bus, and the Ethernet port processing module is connected with the TSN protocol processing module through a data bus.

[0011] Preferably, the embedded software processing module comprises a MICRO_BLAZE soft core in the programmable logic device and a RAM and an interrupt management peripheral thereof.

[0012] Preferably, the programmable logic device is electrically connected with an Ethernet PHY, an RJ45 network port, an optical module, a 1PPS+TOD interface and an RS232 serial port, the Ethernet PHY and the optical module support 1Gbps and 2.5Gbps rates, and the RJ45 network port is a standard RJ45 connector.

[0013] Preferably, the 1PPS+TOD interface comprises a group of 1PPS and TOD input signals, the 1PPS signal is input once per second, and the TOD signal is input following the 1PPS signal.

[0014] Preferably, the TSN protocol processing module executes IEEE802.1AS, IEEE802.1Qav, IEEE802.1Qbv, IEEE802.1Qci, IEEE802.1CB and IEEE802.1QBu / 802.3Br protocols on the message receiving and sending paths.

[0015] In summary, the technical effects and advantages of the present application are as follows: the TSN network switch compatible with 1Gbps and 2.5Gbps of the Ethernet port rate, through the link state reporting module, the link detection module and the dynamic configuration module in the Ethernet port processing module, according to the dynamic detection link establishment state, using the dynamic configuration mode, modifying the 1G / 2.5G Ethernet PCS / PMA module IP port rate related parameters in the FPGA, cooperating with the clock phase-locked loop and the channel phase-locked loop, realizing the link rate switching, compared with the prior art device, avoiding the problem that the TSN Ethernet switch device is not compatible with 1Gbps and 2.5Gbps of the port rate, improving the practicability and convenience of the device.

[0016] In addition, through the multi-stage flow design of the port processing module, the TSN protocol processing and the message exchange matrix module, each module has higher data processing bandwidth, so that the TSN network switch supports more Ethernet ports and more comprehensive TSN protocols, improving the practicability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 The hardware structure diagram of the present application is shown in the figure;

[0018] Figure 2 The functional composition block diagram of the programmable logic device in the present application is shown in the figure;

[0019] Figure 3 The functional composition block diagram of the Ethernet port link rate adaptive switching in the present application is shown in the figure;

[0020] Figure 4 The flow chart of the Ethernet port link rate adaptive switching in the present application is shown in the figure. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments.

[0022] Referring to Figure 1 An Ethernet port rate compatible TSN network switch with 1Gbps and 2.5Gbps, comprising a programmable logic device, the programmable logic device comprising an Ethernet port processing module and an Ethernet PCS / PMA module, the Ethernet port processing module being connected with the Ethernet PCS / PMA module through a data bus and a configuration bus.

[0023] Referring to Figure 3The Ethernet PCS / PMA module comprises a reset module, a clock control module, a shared clock resource module and a 1G / 2.5G Ethernet PCS / PMA module, and the Ethernet port processing module comprises a link state reporting module, a link detection module and a dynamic configuration module.

[0024] The Ethernet port processing module configures the working mode and link rate of the Ethernet PHY through an MDIO bus on the FPGA chip and exchanges data with the Ethernet PCS / PMA module through a GMII interface.

[0025] The Ethernet PCS / PMA module is re-packaged on the basis of a 1G / 2.5G Ethernet PCS / PMA in the xilinx IP library by adding a shared clock resource module and a 1G / 2.5G Ethernet PCS / PMA module drp configuration bus, and provides a data link layer and a physical layer transmission function of a TSN network switch port.

[0026] The shared clock resource module is provided with a clock phase-locked loop, the 1G / 2.5G Ethernet PCS / PMA module is provided with a channel phase-locked loop, the dynamic configuration module cooperates with the link detection module to modify the 1G / 2.5G Ethernet PCS / PMA module IP port rate related parameters in the FPGA, and the dynamic configuration module configures the clock phase-locked loop and the channel phase-locked loop parameters through a DRP bus.

[0027] Referring to Figure 1 , Figure 4 , the Ethernet port is compatible with 1Gbps and 2.5Gbps TSN network switches, in use, an optical fiber is inserted into an optical module or a network cable is inserted into an RJ45 network port, the link detection module in the Ethernet port processing module scans the physical connection state of the network port according to a configurable detection period, the electrical interface type network port detects the LINK signal of the peripheral hardware PHY chip, and the optical interface type network port detects the RX_LOS signal of the peripheral hardware optical module.

[0028] Referring to Figures 3-4, after detecting that the network port physical connection is normal, the link establishment and link rate state information output by the 1G / 2.5G Ethernet PCS / PMA module is detected, the default data transmission rate is 1Gbps, the state information includes the reset flow success signal, the link establishment success signal and the self-negotiation rate information output by the reset module; if the state information is normal, the link state information is reported through the register mode; if the described state information is abnormal, it indicates that the link establishment fails, and then the switching process of the 1Gbps / 2.5Gbps data transmission rate is triggered. In the first use, since the default data transmission rate is 1Gbps, the 1G / 2.5G Ethernet PCS / PMA module IP network port rate related parameters will be modified after the link establishment fails, and the data transmission rate is switched to 2.5Gbps; if it is not the first use, the default data transmission rate is the transmission rate after the last link establishment is successful.

[0029] The dynamic configuration module configures the clock phase-locked loop parameters of the shared clock resource module and the channel phase-locked loop parameters of the 1G / 2.5G Ethernet PCS / PMA module through the drp bus according to the link rate switching control signal of the link detection module, that is, the automatic detection and switching of the network port rate are completed.

[0030] The clock phase-locked loop (PLL) can multiply or divide the frequency of the input signal to generate a stable output frequency related to it. During the rate switching process, by adjusting the parameters of the PLL, the frequency of the clock signal can be quickly changed to adapt to the new data transmission rate, ensuring that the operation of each component in the data transmission process is consistent and avoiding signal drift and distortion.

[0031] The channel phase-locked loop (CPLL) can be used to realize synchronization between channels, ensuring that each channel outputs signals of the same frequency and phase at the same time, thereby improving the consistency and accuracy of data transmission. In addition, it can also reduce the signal quality problems caused by electromagnetic interference (EMI) and improve the stability and reliability of the system.

[0032] Referring to Figure 4 , the phase-locked loop parameter configuration process of the shared clock resource module: first reset the phase-locked loop, configure the phase-locked loop parameters, and finally release the phase-locked loop reset; wait for the phase-locked loop of the shared clock resource module to lock, if it continues to be in the unlocked state, re-execute the phase-locked loop parameter configuration process; after the phase-locked loop of the shared clock resource module is locked, start configuring the related parameters of the CPLL channel phase-locked loop (the channel phase-locked loop of the 1G / 2.5G Ethernet PCS / PMA module) of the GTX / GTH Transceiver module in the FPGA; after the parameter configuration is completed, wait for the channel phase-locked loop to lock; after the channel phase-locked loop is locked, the Ethernet link establishment state is detected again.

[0033] The programmable logic device is a Xilinx Zynq series FPGA, and the programmable logic device further comprises an embedded software processing module, a message switching matrix module, and a TSN protocol processing module.

[0034] The embedded software processing module comprises a MICRO_BLAZE soft core in the programmable logic device and a RAM and an interrupt management peripheral thereof.

[0035] The programmable logic device is electrically connected with an Ethernet PHY, an RJ45 network port, an optical module, a 1PPS+TOD interface, and an RS232 serial port for debugging.

[0036] The 1PPS+TOD interface comprises a group of 1PPS and TOD input signals, the 1PPS signal is input once per second, and the TOD signal is input following the 1PPS signal.

[0037] The TSN protocol processing module executes IEEE802.1AS, IEEE802.1Qav, IEEE802.1Qbv, IEEE802.1Qci, IEEE802.1CB, and IEEE802.1QBu / 802.3Br protocols on the message receiving and sending paths according to TSN characteristic configuration information, so as to ensure the deterministic, low-delay, and high-reliability transmission of data.

[0038] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can make equivalent replacement or change according to the technical scheme and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A TSN network switch compatible with 1 Gbps and 2.5 Gbps Ethernet port rates, characterized in that, The programmable logic device comprises an Ethernet port processing module and an Ethernet PCS / PMA module, and the Ethernet port processing module is connected with the Ethernet PCS / PMA module through a data bus and a configuration bus; The Ethernet PCS / PMA module comprises a reset module, a clock control module, a shared clock resource module and a 1G / 2.5G Ethernet PCS / PMA module, and the Ethernet port processing module comprises a link state reporting module, a link detection module and a dynamic configuration module; The shared clock resource module is provided with a clock phase-locked loop, the 1G / 2.5G Ethernet PCS / PMA module is provided with a channel phase-locked loop, the dynamic configuration module cooperates with the link detection module to modify the 1G / 2.5G Ethernet PCS / PMA module IP network port rate related parameters in the FPGA, and the dynamic configuration module configures the clock phase-locked loop and the channel phase-locked loop parameters through a DRP bus.

2. The TSN network switch compatible with 1 Gbps and 2.5 Gbps of Ethernet port rates according to claim 1, wherein, The programmable logic device is an Xilinx Zynq series FPGA, and the programmable logic device further comprises an embedded software processing module, a message switching matrix module and a TSN protocol processing module, the message switching matrix module is connected with the embedded software processing module and the TSN protocol processing module through a data bus, and the Ethernet port processing module is connected with the TSN protocol processing module through a data bus.

3. The TSN network switch compatible with 1 Gbps and 2.5 Gbps of Ethernet port rates according to claim 2, characterized in that, The embedded software processing module comprises a MICRO_BLAZE soft core in the programmable logic device and a RAM and an interrupt management peripheral thereof.

4. The TSN network switch compatible with 1 Gbps and 2.5 Gbps of Ethernet port rates according to claim 1, wherein, The programmable logic device is electrically connected with an Ethernet PHY, an RJ45 network port, an optical module, a 1PPS+TOD interface and an RS232 serial port, the Ethernet PHY and the optical module support 1Gbps and 2.5Gbps rates, and the RJ45 network port is a standard RJ45 connector.

5. The TSN network switch compatible with 1 Gbps and 2.5 Gbps of Ethernet port rates according to claim 4, characterized in that, The 1PPS+TOD interface comprises a group of 1PPS and TOD input signals, the 1PPS signal is input once per second, and the TOD signal is input following the 1PPS signal.

6. The TSN network switch compatible with 1 Gbps and 2.5 Gbps of Ethernet port rates according to claim 2, wherein, The TSN protocol processing module executes IEEE802.1AS, IEEE802.1Qav, IEEE802.1Qbv, IEEE802.1Qci, IEEE802.1CB and IEEE802.1QBu / 802.3Br protocols on the message receiving and sending paths.

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