PCB capable of assisting in controlling back drilling depth and high-speed chip

Abstract

The utility model relates to the field of chips, in particular to a PCB capable of assisting in controlling the depth of a back drill and a high-speed chip. The PCB is provided with N circuit layers, the upper surface circuit layer is the first layer, the lower surface circuit layer is the Nth layer, the effective transmission path of the via hole is from the n1th layer to the n2th layer circuit layer, N is greater than or equal to 3, n1 and n2 are positive integers, and n1 is less than n2; wherein under the condition that n1 is equal to 1 and n2 is smaller than N, at least one layer from the first layer to the n2th layer and the (n2 + 1) th circuit layer are respectively connected with signal lines; under the condition that n1 is greater than 1 and n2 is equal to N, at least one layer from the n1th layer to the Nth layer and the (n1-1) th circuit layer are respectively connected with a signal line; under the condition that n1 is larger than 1 and smaller than n2 and smaller than N, at least one layer from the n1th layer to the n2th layer, the (n1-1) th layer and the (n2 + 1) th layer are connected with signal lines respectively. According to the utility model, the back drilling depth can be accurately controlled in the back drilling process, and the length consistency of stubs is ensured, so that the performance consistency of element pins is ensured.

Description

TECHNICAL FIELD

[0001] The utility model relates to chip field, concretely relates to a PCB board and high -speed chip of supplementary control back drilling depth. BACKGROUND

[0002] As Figure 1 Shown, in the design of PCB board, PCB board can be divided into AB two sides, A side is generally the upper surface, B side is generally the lower surface, AB two sides can become the 2 surface circuit layers of PCB board. If PCB board is multilayer board design, then there will be 1 to more internal circuit layers. If signal line needs to be communicated between different circuit layers 1, then needs to realize the layer change through via 3. Via 3 is usually a conductive hole that penetrates all layers of PCB board.

[0003] As Figure 1 Shown, a signal first passes through the signal line of n1 (n1=1) layer, connects to the circuit layer 1 of n2 layer through a via 3, and the effective transmission path of the signal is shown by the dashed line. It can be seen that the via 3 part below the circuit layer 1 of n2 layer is not the effective transmission path of the signal, and can be considered as the redundant part of via 3; because the end of the redundant part of via 3 is not terminated, the signal transmission to the end of via 3 will form a reflection, which will interfere with the signal on the effective transmission path; the redundant part of via 3 also has a parasitic effect that will affect the impedance of the signal, and further affect the signal integrity; the redundant part of via 3 will also cause electromagnetic radiation problems due to the antenna effect, which will affect other signals on the PCB board.

[0004] In the conventional PCB board design, most of the signals are low-speed signals, and the board thickness and the number of layers are small, so the negative effects caused by the redundant part of via 3 are small, and can even be ignored. In some high-thickness and high-layer-number PCB board designs with special purposes (such as ATE test boards, which can have a thickness of 5-8 mm and a layer number of more than 60), the signal rate on the board can reach hundreds of megahertz to gigahertz, and in this case, the negative effects caused by the redundant part of via 3 will seriously affect the transmission quality of the signal.

[0005] In order to solve the negative influence caused by the excess part of the via 3 in the PCB board with high thickness and high layer number, the back drilling technology is usually used to eliminate the excess part of the via 3, that is, a larger drill than the previous via size is used to drill again to drill off the excess part of the via 3, so as to achieve the purpose of eliminating the excess via 3. In theory, after the back drilling processing, the excess part of the via 3 can be completely removed. However, in the actual processing process, there will be errors in the control of the drilling depth. If the back drilling depth is too deep, the signal will be open circuit, and if the back drilling depth is too shallow, the excess part of the via 3 cannot be completely removed. The excess part of the via 3 that cannot be removed is called stub. The longer the stub, the lower the processing difficulty and the greater the negative influence on the signal. The shorter the stub, the higher the processing difficulty and the smaller the negative influence on the signal. For the PCB circuit board with high layer number, the plurality of circuit layers 1 and the plurality of dielectric layers 2 need to be processed separately and then pressed into a complete PCB board. The more the layers, the more difficult to control the expansion and contraction during pressing. Finally, the thickness of the circuit board cannot be completely uniform on the micro level. The inconsistency of the thickness of the PCB circuit board is proportional to the area of the PCB circuit board. Therefore, the thicker the PCB circuit board, the more difficult to control the length of the stub.

[0006] The traditional back drilling processing scheme defines the depth of back drilling by theoretical calculation, and measures the actual stub length by slicing analysis of the PCB circuit board, that is, destructive measurement, and has hysteresis. Therefore, a PCB board capable of controlling the depth of back drilling in an intuitive and non-destructive manner is needed, especially for high thickness and high layer number PCB boards. SUMMARY

[0007] The technical problem to be solved by the utility model is to overcome the defects of the prior art, and provide a PCB board capable of assisting in controlling the depth of back drilling. The PCB board can accurately control the depth of back drilling during back drilling, ensure the consistency of the length of the stub, and ensure the consistency of the performance of the element pin.

[0008] In order to solve the above technical problems, the technical scheme of the utility model is as follows: a PCB board capable of assisting in controlling the depth of back drilling, the PCB board has N circuit layers, the upper surface circuit layer is the first layer, the lower surface circuit layer is the Nth layer, the effective transmission path of the via is from the nth1 layer to the nth2 layer circuit layer, N is greater than or equal to 3, n1 and n2 are positive integers and n1 is less than n2; wherein,

[0009] In the case that n1 is equal to 1 and n2 is less than N, at least one layer from the first layer to the nth2 layer and the nth2+1 layer circuit layer are respectively connected with a signal line;

[0010] In the case of n1>1 and n2=N, the signal lines are connected to at least one layer among the n1th layer to the Nth layer and the n1-1th layer, respectively;

[0011] In the case of 1

[0012] Further, in order to know the specific position of back drilling in the process of back drilling from the lower surface to the target layer, in the case of n1=1 and n2

[0013] Further, in order to know the specific position of back drilling in the process of back drilling from the upper surface to the target layer, in the case of n1>2 and n2=N, the signal lines are connected to at least one layer above the n1-1th layer, respectively.

[0014] Further, in order to know the specific position of back drilling in the process of back drilling from the upper surface and the lower surface to the target layer, respectively, in the case of 2

[0015] In the case of 1

[0016] Further, in order to facilitate the test of the continuity between the corresponding signal lines, each signal line is connected to a test point, respectively.

[0017] Further, in order to facilitate the distinction of different types of test points, in the case of n1=1 and n2

[0018] In the case of n1>1 and n2=N, the test points connected by the signal lines of the circuit layers among the n1th layer to the Nth layer are back drilling test points, and the test points connected by the signal lines of the other circuit layers are external test points.

[0019] In the case of 1

[0020] The external test points are used to test the continuity between the external test points and the back drilling test points.

[0021] Further, each back-drilling test point is configured with a network property having a ground.

[0022] The utility model still relates to a high-speed chip, including the PCB board of supplementary control back-drilling depth.

[0023] After adopting the technical scheme, the utility model realizes accurate control of back-drilling depth by measuring the on-off between corresponding line layers, does not need to damage the PCB board, is suitable for high-plate thickness, high-layer number PCB board, is suitable for multi-pin number, large size high-speed chip design. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is the effective transmission path schematic diagram of signal for via hole being the conductive hole of all layers of PCB board;

[0025] Figure 2 It is the ideal back-drilling schematic diagram of the effective transmission path of via hole in the utility model being from the n1 layer to the n2 layer line layer, and n1=1, n2

[0026] Figure 3 It is the ideal back-drilling schematic diagram of the effective transmission path of via hole in the utility model being from the n1 layer to the n2 layer line layer, and n1>1, n2=N;

[0027] Figure 4 It is the ideal back-drilling schematic diagram of the effective transmission path of via hole in the utility model being from the n1 layer to the n2 layer line layer, and 1

[0028] Figure 5 It is Figure 2 It is the schematic diagram of connecting signal line and test point of the effective transmission path being from the n1 layer to the n2 layer line layer, and n1=1, n2

[0029] In the drawing, 1, line layer;2, dielectric layer;3, via hole;4, signal line;5, test point;5a, back-drilling test point;5b, external test point. DETAILED DESCRIPTION

[0030] In order to make the content of the utility model more easily be clearly understood, the following according to specific embodiment and combining with the drawings, the utility model is further detailed.

[0031] As Figures 1 to 5As shown, a PCB board for assisting in controlling back-drilling depth is disclosed. The PCB board has N circuit layers 1, with adjacent circuit layers 1 separated by dielectric layers 2. The upper surface circuit layer 1 is layer 1, and the lower surface circuit layer 1 is layer N. The effective transmission path of the via 3 is from layer n1 to layer n2 of circuit layer 1, where N ≥ 3, n1 and n2 are both positive integers, and n1 < n2.

[0032] When n1 = 1 and n2 = N, the effective signal transmission path is from layer 1 to layer N, and there is no redundant via 3 at the actual back-drilling point.

[0033] When n1 = 1 and n2 < N, as follows Figure 2 As shown, the effective signal transmission path is from layer 1 to layer n2 (line layer 1). The via 3 portion from layer n2+1 to layer N is redundant, and the actual back-drilling point needs to start from layer N. Signal lines 4 are connected to at least one of layers 1 to n2 and to layer n2+1 (line layer 1). A short circuit is measured between the signal line 4 connected to layer n2+1 and the signal line 4 connected to one of the line layers 1 from layers 1 to n2, indicating that back-drilling has not yet reached layer n2+1 (line layer 1). Back-drilling continues. An open circuit is measured between the signal line 4 connected to layer n2+1 and the signal line 4 connected to one of the line layers 1 from layers 1 to n2, indicating that back-drilling has reached layer n2+1 (line layer 1), and back-drilling can be stopped. Connecting signal lines 4 to any one of layers 1 to n2 is sufficient, preferably to layer 1. Connecting signal lines 4 to at least two layers can improve reliability.

[0034] When n1 > 1 and n2 = N, such as Figure 3 As shown, the effective signal transmission path is from the n1st line layer 1 to the Nth line layer 1. The via 3 portion from the 1st layer to the n1-1st layer is redundant, and the actual back-drilling point needs to start from the 1st layer. Signal lines 4 are connected to at least one of the line layers from the n1st to the Nth layer and to the n1-1st line layer 1. A short circuit is measured between the signal line 4 connected to the n1-1st line layer 1 and the signal line 4 connected to one of the line layers from the n1st to the Nth layer 1, indicating that back-drilling has not yet reached the n1-1st line layer 1. Back-drilling continues. An open circuit is measured between the signal line 4 connected to the n1-1st line layer and the signal line 4 connected to one of the line layers from the n1st to the Nth layer 1, indicating that back-drilling has reached the n1-1st line layer 1, and back-drilling can be stopped. Connecting signal lines 4 to any one of the n1st to the Nth layer is sufficient, preferably connecting signal lines 4 to the Nth layer. Connecting signal lines 4 to at least two of these layers can improve reliability.

[0035] In the case that 1 < n1 < n2 < N, such as Figure 4As shown, the signal effective transmission path is from the n1th layer to the n2th layer, the via hole 3 parts from the 1st layer to the n1-1th layer and from the n2+1th layer to the Nth layer are redundant parts, and the actual back drilling point needs to be back drilled from the 1st layer and the Nth layer respectively. The signal line 4 is connected to the 1st layer, the n1-1th layer and the n2+1th layer in the at least one layer among the n1th layer to the n2th layer respectively. When back drilling from the 1st layer, a short circuit is measured between the signal line 4 connected to the n1-1th layer and the signal line 4 connected to one of the n1th layer to the n2th layer, which proves that the n1-1th layer has not been back drilled, and the back drilling is continued. When the signal line 4 connected to the n1-1th layer and the signal line 4 connected to one of the n1th layer to the n2th layer are measured to be open, it is proved that the n1-1th layer has been back drilled, and the back drilling can be stopped. When back drilling from the Nth layer, a short circuit is measured between the signal line 4 connected to the n2+1th layer and the signal line 4 connected to one of the n1th layer to the n2th layer, which proves that the n2+1th layer has not been back drilled, and the back drilling is continued. When the signal line 4 connected to the n2+1th layer and the signal line 4 connected to one of the n1th layer to the n2th layer are measured to be open, it is proved that the n2+1th layer has been back drilled, and the back drilling can be stopped. The signal line 4 can be connected to one of the n1th layer to the n2th layer, and the reliability can be improved when the signal line 4 is connected to at least two layers respectively.

[0036] In one embodiment, as shown in Figure 5 In the case of n1 = 1 and n2 < N-1, the signal line 4 is connected to at least one layer closest to the n2+1th layer below the n2+1th layer. That is, in the case that the n2th layer is not the second last layer, in order to facilitate knowing which layer has been back drilled, a signal line 4 can be connected to each layer below the n2+1th layer during the back drilling process from the Nth layer, and the continuity between the signal line 4 of the n2+1th layer and the layers below it and the signal line 4 connected to one of the 1st layer to the n2th layer is measured during the back drilling process from the Nth layer. The layer which changes from short circuit to open circuit indicates that the via hole 3 of the layer has been back drilled.

[0037] In one embodiment, when n1>2 and n2=N, at least one layer of the circuit layer 1 closest to the nth1-1 layer of the circuit layer 1 is connected with the signal line 4. That is, when the nth1 layer of the circuit layer 1 is not the second layer from the top, in order to know which layer has been drilled from the top, a signal line 4 can be connected to each layer above the nth1-1 layer. In the drilling process from the first layer, the continuity between the signal line 4 of the nth1-1 layer and the signal line 4 of one of the nth1 layer to the Nth layer is measured. When the continuity changes from short circuit to open circuit, it indicates that the via 3 of the layer has been drilled.

[0038] In one embodiment, when 2

[0039] That is, when the nth1 layer of the circuit layer 1 is not the second layer from the top, in order to know which layer has been drilled from the top, a signal line 4 can be connected to each layer above the nth1-1 layer.

[0040] In one embodiment, when 1

[0041] That is, when the nth2 layer of the circuit layer 1 is not the second layer from the bottom, in order to know which layer has been drilled from the bottom, a signal line 4 can be connected to each layer below the nth2+1 layer.

[0042] In one embodiment, as shown in FIG. 1, each signal line 4 is connected with a test point 5. In this way, the continuity between the corresponding signal lines 4 can be measured conveniently. In this embodiment, the test point 5 is connected with the signal line 4 through a resistor 6. Figure 5

[0043] When n1=1 and n2

[0044] When n1>1 and n2=N, the test points 5 connected with the signal lines 4 of the circuit layers 1 from the nth1 layer to the Nth layer are the back drilling test points 5a, and the test points 5 connected with the signal lines 4 of the other circuit layers 1 are the external test points 5b.

[0045] ​In the case where 1 < n1 < n2 < N, the test point 5 connected to the line layer 1 in layers n1 to n2 by the signal line 4 is the back-drilling test point 5a, and the test points 5 connected to the line layer 1 in other layers by the signal line 4 are the external test points 5b.

[0046] During back drilling, the continuity between each external test point 5b and one of the back drilling test points 5a is tested. Each back drilling test point 5a can be configured with a grounded network attribute.

[0047] To facilitate understanding of the solution in this embodiment, Figure 2 The example is taken from back drilling at the Nth layer.

[0048] like Figure 5 As shown, assuming the effective signal path is from layer 01 to layer n (i.e., n1 = 1, n2 = n), then the back-drilling implementation should be from layer N to layer n+1. A test point TEST is set up on layer 1 (line layer 1), which has a grounded network attribute. Starting from layer n+1, one or more external test points T1, T2...Tx are set up. Signal lines 4 are used to connect layer n+1 and external test point T1, layer n+2 and external test point T2, and so on. T0 serves as the back-drilling test point, connected to test point TEST via a signal line. T0 itself already has the same connection attribute as test point TEST.

[0049] After back drilling is performed, the electrical performance connection relationship of Tx...T2, T1 and T0 are measured sequentially from bottom to top. If an open circuit is measured, it proves that the back drilling has drilled away part of the layer where Tx is located, and Tx-1 can be measured. If a short circuit is measured, it proves that the back drilling has not reached the layer where Tx is located. Then the length of the remaining pile is the sum of the thickness of all line layer 1 and dielectric layer 2 between the nth layer and the layer where Tx is located.

[0050] In one embodiment, a high-speed chip includes a PCB board that can assist in controlling the back-drilling depth as described in any of the above embodiments.

[0051] Based on the above-described preferred embodiments of this utility model, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A PCB board capable of assisting in controlling back drilling depth, characterized in that, the PCB board has N layers of circuit layers (1), with the upper surface circuit layer (1) being the first layer and the lower surface circuit layer (1) being the Nth layer, the effective transmission path of the via (3) being from the nth1 layer to the nth2 layer of circuit layers (1), N≥3, n1 and n2 are positive integers and n1 in the case of n1=1 and n2 in the case of n1>1 and n2=N, at least one of the nth1 layer to the Nth layer of circuit layers (1) is connected with a signal line (4) respectively. in the case of 1 2. The PCB board capable of assisting in controlling back drilling depth according to claim 1, characterized in that, in the case of n1=1 and n2 3. The PCB board capable of assisting in controlling back drilling depth according to claim 1, characterized in that, in the case of n1>2 and n2=N, at least one of the circuit layers (1) closest to the nth1-1 layer of circuit layers (1) is connected with a signal line (4).

4. The PCB board capable of assisting in controlling back drilling depth according to claim 1, characterized in that, in the case of 2 in the case of 1 5. The PCB board capable of assisting in controlling back drilling depth according to any one of claims 1-4, characterized in that, each signal line (4) is connected with a test point (5) respectively.

6. The PCB board capable of assisting in controlling back drilling depth according to claim 5, characterized in that, in the case of n1=1 and n2 in the case of n1>1 and n2=N, the test points (5) connected by the signal lines (4) of the circuit layers (1) in the nth1 layer to the Nth layer are back drilling test points (5a) and the test points (5) connected by the signal lines (4) of the other circuit layers (1) are external test points (5b). In the case of 1 < n1 < n2 < N, the test points (5) connected by the signal lines (4) of the circuit layers (1) in the n1th to n2th layers are back-drilling test points (5a), and the test points (5) connected by the signal lines (4) of the other circuit layers (1) are external test points (5b); The external test points (5b) are used to test the on-off circuit between them and the back-drilling test points (5a).

7. The PCB capable of assisting in controlling the back-drilling depth according to claim 6, characterized in that, Each back-drilling test point (5a) is configured with a network attribute with grounding.

8. A high-speed chip, characterized in that, It comprises the PCB capable of assisting in controlling the back-drilling depth according to any one of claims 1-7.

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