Embedded error correction system and embedded integrated circuit
By designing an embedded error correction system and utilizing interface modules to achieve signal interaction between modules, the high-cost debugging problem caused by the complexity of digital IP core design is solved, and a flexible and low-cost error correction system is realized.
Patent Information
- Application Number
- CN202520406411.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-06
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2035-03-06
AI Technical Summary
The complexity of digital IP core design in existing on-chip systems leads to high debugging and design costs, requiring improved debugging interfaces and complex host computer hardware to complete chip debugging and design processing.
An embedded error correction system is provided, including an error estimation module, a coefficient calculation module, an error correction module, and an interface module. The interface module enables signal interaction between modules, reducing debugging and design difficulty. The SPI module is used for communication, saving chip pins.
This reduces the difficulty of debugging and designing the error correction system, improves the system's flexibility, and meets usage requirements.
Smart Images
Figure CN223692666U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and particularly relates to an embedded error correction system and an embedded integrated circuit. BACKGROUND
[0002] With the continuous reduction of process, the intrinsic gain of the transistor is continuously reduced, and the analog circuit design is increasingly challenging. In order to meet the speed and accuracy requirements of signal conversion of the whole system on chip (SOC), powerful digital processing technology is needed to assist analog signal processing, and corresponding digital circuit correction is needed in different analog modules. Especially, high-performance mixed-signal SOC needs to integrate complex digital design to meet flexible computing requirements. Therefore, various digital designs, including application-specific integrated circuits (ASIC) and embedded IP cores (such as processor, memory, and other functional units), are integrated in the SOC. The circuit structure of the SOC is as shown in Figure 1
[0003] In Figure 1 , the embedded IP core reads the data processed by the ASIC, and completes the corresponding data processing and error processing according to the predetermined algorithm program in the embedded IP core, and then outputs to the ASIC to complete the algorithm processing of the error information and realize error correction. Since the SOC integrates a large number of IP core designs, the use of this digital architecture design has high flexibility, high configurability, and good portability.
[0004] However, due to the complexity of the digital IP core design, the debugging and design cost of the SOC is very high, and a special debugging interface and a complex host computer hardware are often needed to complete the corresponding chip debugging and design processing. Therefore, it is necessary to improve the SOC in the related art. CONTENT OF THE UTILITY MODEL
[0005] In view of the above-mentioned shortcomings of the prior art, the present application provides an embedded error correction system and an embedded integrated circuit to solve the above technical problems.
[0006] The application provides an embedded error correction system, which comprises an error estimation module connected with an interface module, an error correction coefficient calculation module connected with the interface module, an error correction module connected with the interface module, and the interface module connected with an external module.
[0007] In an embodiment of the application, the system further comprises a register connected with the error estimation module, the error correction coefficient calculation module and the error correction module, and the register is used for receiving and storing the error estimation signal, the error correction coefficient and the correction result.
[0008] In an embodiment of the application, the system further comprises a selector, a first input end of the selector connected with the error correction coefficient calculation module, a second input end of the selector connected with the error estimation module, a third input end of the selector connected with the error correction module, a fourth input end of the selector connected with the interface module, and an output end of the selector connected with the register.
[0009] In an embodiment of the application, the system further comprises an analog-digital conversion module connected with the error estimation module, a digital-analog conversion module connected with the error estimation module, a phase-locked loop connected with the error estimation module, and a sensor connected with the error estimation module.
[0010] In an embodiment of the present application, the error estimation module comprises an adder and an accumulator; a first input terminal of the adder is connected with the analog-digital conversion module, a second input terminal of the adder is connected with the register, used for adding the analog-digital conversion signal and the error correction coefficient pre-stored in the register to obtain an added signal; an input terminal of the accumulator is connected with an output terminal of the adder, an output terminal of the accumulator is connected with the register, used for accumulating the added signal to obtain a first accumulated signal, and writing the first accumulated signal as the error estimation signal into the register for reading by the coefficient calculation module.
[0011] In an embodiment of the present application, the error estimation module comprises a squarer, a multiplier and an accumulator; an input terminal of the squarer is connected with the analog-digital conversion module, used for calculating a square value of the analog-digital conversion signal; a first input terminal of the multiplier is connected with an output terminal of the squarer, a second input terminal of the multiplier is connected with the register, used for multiplying the square value and the error correction coefficient pre-stored in the register to obtain a multiplied signal; a first input terminal of the accumulator is connected with an output terminal of the multiplier, a second input terminal of the accumulator is connected with the register, used for accumulating the multiplied signal to obtain a second accumulated signal, and writing the second accumulated signal as the error estimation signal into the register for reading by the coefficient calculation module.
[0012] In an embodiment of the present application, the error estimation module comprises a delay device and a multiplier; a first input terminal of the delay device is connected with the analog-digital conversion module, a second input terminal of the delay device is connected with the register, used for delaying the analog-digital conversion signal to obtain a first delayed signal, and delaying the error correction coefficient pre-stored in the register to obtain a second delayed signal; a first input terminal of the multiplier is connected with output terminals of the delay device, a second input terminal of the multiplier is connected with the register, used for multiplying the first delayed signal with the analog-digital conversion signal to obtain a first correlation signal, multiplying the second delayed signal with the analog-digital conversion signal to obtain a second correlation signal, and writing the first correlation signal and the second correlation signal as the error estimation signal into the register for reading by the coefficient calculation module.
[0013] In an embodiment of the present application, the external module comprises an external calculation module connected with the interface module, used for acquiring the error estimation signal through the interface module, calculating the error correction coefficient, writing the error correction coefficient into the register through the interface module for reading by the error correction module.
[0014] In an embodiment of the present application, the external module further comprises an external memory connected with the interface module, for obtaining the error estimation signal, the error correction coefficient and the correction result through the interface module, and storing the error estimation signal, the error correction coefficient and the correction result.
[0015] According to an aspect of an embodiment of the present application, there is provided an embedded integrated circuit, which comprises the embedded error correction system as described above.
[0016] The present application has the following advantages: the interface module is provided, which not only facilitates the signal interaction between the error estimation module, the coefficient calculation module and the error correction module, but also facilitates the signal interaction between the error estimation module and the external module, the coefficient calculation module and the external module, and the error correction module and the external module, thereby reducing the debugging and design difficulty of the error correction system, having high flexibility, and meeting the use requirement to a greater extent.
[0017] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not limiting to the present application. BRIEF DESCRIPTION OF DRAWINGS
[0018] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. It is clear that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art without creative labor based on these drawings. In the drawings:
[0019] Figure 1 is a schematic diagram of an embedded error correction system shown in the related art;
[0020] Figure 2 is a schematic diagram of an embedded error correction system shown in an exemplary embodiment of the present application;
[0021] Figure 3 is a schematic diagram of an embedded error correction system shown in another exemplary embodiment of the present application;
[0022] Figure 4 is a schematic diagram of signal interaction between a processor and a digital circuit shown in an exemplary embodiment of the present application;
[0023] Figure 5 is a schematic diagram of access to a register by a digital circuit shown in an exemplary embodiment of the present application;
[0024] Figure 6 is a schematic diagram of access to a register by a processor shown in an exemplary embodiment of the present application;
[0025] Figure 7 is a schematic diagram showing signal interaction between an external module and a digital circuit according to an exemplary embodiment of the present application;
[0026] Figure 8 is a schematic diagram showing signal interaction between an external module and a processor according to an exemplary embodiment of the present application;
[0027] Figure 9 is a schematic diagram showing access to a register according to an exemplary embodiment of the present application;
[0028] Figure 10 is a schematic diagram showing an error estimation module according to an exemplary embodiment of the present application;
[0029] Figure 11 is a schematic diagram showing an error estimation module according to another exemplary embodiment of the present application;
[0030] Figure 12 is a schematic diagram showing an error estimation module according to yet another exemplary embodiment of the present application. DETAILED DESCRIPTION
[0031] Other advantages and novel features of the present application will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that the Figures provided herein are by way of illustration only and should not be construed in the context of limiting the scope of the present application.
[0032] It should be noted that the graphical illustrations provided in the following embodiments are merely schematic representations for explaining the basic concept of the present application, and thus the Figures only show the components related to the present application without showing the number, shape and size of the components as they are in actual implementation, and the actual implementation of the components can be arbitrarily changed in terms of shape, number and ratio, and the layout of the components can be more complicated.
[0033] In the following description, numerous specific details are discussed in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one of ordinary skill in the art that the embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the embodiments of the present application.
[0034] Figure 1 is a schematic diagram showing an embedded error correction system according to the related art, as shown in Figure 1As shown, the embedded error correction system comprises an analog circuit, a digital circuit and a processor, wherein the analog circuit is configured to detect, sample or filter a signal, and comprises an analog-digital conversion module, a digital-analog conversion module, a phase-locked loop and a sensor; the digital circuit is configured to receive the signal sent by the analog circuit, and perform error estimation on the signal sent by the analog circuit; the processor is configured to calculate an error correction coefficient according to the error estimation signal; and the digital circuit is configured to perform error correction on the signal sent by the analog circuit according to the error correction coefficient, and comprises an error estimator, an accumulator and a filter.
[0035] The technical scheme of the embodiment of the application relates to integrated circuits and related technologies, and is specifically described as follows:
[0036] In an embodiment of the application, the embedded error correction system comprises:
[0037] An error estimation module is connected with the interface module, and is configured to perform error estimation and send an error estimation signal to the interface module;
[0038] A coefficient calculation module is connected with the interface module, and is configured to read the error estimation signal and calculate an error correction coefficient, and send the error correction coefficient to the interface module;
[0039] An error correction module is connected with the interface module, and is configured to read the error correction coefficient and perform error correction, and send a correction result to the interface module;
[0040] The interface module is further configured to be connected with an external module, and provide the external module with the error estimation signal, the error correction coefficient and the correction result.
[0041] In an embodiment of the application, the error estimation module and the error correction module are arranged in the digital circuit, the coefficient calculation module can be implemented by a processor, the processor can be a digital signal processor (DSP) or a microcontroller unit (MCU), the interface module is an SPI (Serial Peripheral Interface) module, the SPI module is a high-speed, full-duplex and synchronous communication bus, and at most 4 lines are required, thereby saving the pins of the chip, the devices connected with the SPI module can communicate in a full-duplex mode, and therefore, the SPI module has the characteristics of low cost, simplicity and reliability.
[0042] In an embodiment of the present application, the error estimation module can implement the error estimation process on the signal sent by the analog circuit by referring to the method for error estimation on the signal sent by the analog circuit in the related art; the coefficient calculation module can implement the process of calculating the error correction coefficient according to the error estimation signal by referring to the method for calculating the error correction coefficient according to the error estimation signal in the related art; the error correction module can implement the process of performing error correction on the signal sent by the analog circuit according to the error correction coefficient by referring to the method for performing error correction on the signal sent by the analog circuit according to the error correction coefficient in the related art, which is not limited here.
[0043] Figure 2 is a schematic diagram of an embedded error correction system according to an example embodiment of the present application, in which Figure 2 the embedded error correction system includes an analog circuit, a digital circuit and a processor, wherein the analog circuit includes an analog-to-digital conversion module, a digital-to-analog conversion module, a phase-locked loop and a sensor, the digital circuit includes an error estimation module (for example, an error estimator), an error correction module (for example, a filter) and the like, and the processor is used to implement the function of a coefficient calculation module; the digital circuit and the processor interact with each other through an interface module (for example, after the error correction coefficient is calculated by the coefficient calculation module, the coefficient of the error correction module is updated through the interface module to realize the configuration of the error correction module); and the digital circuit or the processor can interact with an external module through the interface module.
[0044] In an embodiment of the present application, by setting the interface module, the signal interaction between the error estimation module, the coefficient calculation module and the error correction module is facilitated, and the signal interaction between the error estimation module, the coefficient calculation module and the error correction module and an external module is also facilitated, which reduces the difficulty of debugging and design of the error correction system and has high flexibility, and meets the use requirements to a greater extent.
[0045] Figure 3 is a schematic diagram of an embedded error correction system according to another example embodiment of the present application, in which Figure 3 the embedded error correction system further includes:
[0046] a register;
[0047] a register connected to the error estimation module and used to receive and store the error estimation signal;
[0048] a register connected to the coefficient calculation module and used to receive and store the error correction coefficient;
[0049] a register connected to the error correction module and used to receive and store the correction result;
[0050] a register connected with the interface module, for providing the error estimation signal, the error correction coefficient and the correction result to the interface module.
[0051] In an embodiment of the present application, the register is divided into a control register and a data register. The control register can control the start and stop of some functions of the digital circuit. For example, the start and stop of the accumulation function in the digital circuit can be realized by assigning values to the control register. Therefore, the implementation is realized by writing to the control register by the processor. The data register is used to store the error correction parameters required by the digital circuit. The update of the error correction parameters is realized by writing to the data register by the processor, and the deployment of the error correction parameters in the digital circuit is realized by reading from the data register by the digital circuit. The data register is used to store the error estimation signal required by the processor. The update of the error estimation signal is realized by writing to the data register by the digital circuit, and the update of the error estimation signal in the processor is realized by reading from the data register by the processor. The register contains a group of register addresses, and the error estimation signal, the error correction coefficient and the correction result exist in the specified register addresses.
[0052] In an embodiment of the present application, the signal interaction between the error estimation module and the coefficient calculation module can be realized by reading and writing control of the register, or can be realized by interaction through the interface module. The signal interaction between the error estimation module and the error correction module can be realized by reading and writing control of the register, or can be realized by interaction through the interface module. The signal interaction between the external module and the error estimation module, the signal interaction between the external module and the coefficient calculation module, and the signal interaction between the external module and the error correction module are all realized through the interface module. Taking the signal interaction between the error estimation module and the coefficient calculation module as an example, the process of the signal interaction between the error estimation module and the coefficient calculation module includes: after the error estimation module obtains the reading and writing control right of the register, the error estimation signal is written into the specified position of the register, and after the coefficient calculation module obtains the reading and writing control right of the register, the error estimation signal is read out from the specified position of the register.
[0053] Figure 4 is a schematic diagram of the signal interaction between the processor and the digital circuit in an exemplary embodiment of the present application. In Figure 4 the signal interaction between the processor and the digital circuit is realized by accessing the register by the processor or the digital circuit and reading and writing the signals in the register. The signal interaction between the processor and the digital circuit includes the signal interaction between the processor and the error estimation module, the signal interaction between the processor and the error correction module, etc.
[0054] Figure 5is a schematic diagram of a digital circuit accessing a register according to an example embodiment of the present application, in which Figure 5 the digital circuit accesses the register by reading and writing signals in the register.
[0055] Figure 6 is a schematic diagram of a processor accessing a register according to an example embodiment of the present application, in which Figure 6 the processor accesses the register by reading and writing signals in the register.
[0056] Figure 7 is a schematic diagram of an external module interacting with a digital circuit according to an example embodiment of the present application, as shown in Figure 7 the digital circuit stores data by writing data to the register, the digital circuit obtains data of the external module by reading data from the register, the external module stores data by writing data to the register through the interface module, and the external module obtains data of the digital circuit by reading data from the register through the interface module, thereby realizing signal interaction between the external module and the digital circuit.
[0057] Figure 8 is a schematic diagram of an external module interacting with a processor according to an example embodiment of the present application, as shown in Figure 8 the processor stores data by writing data to the register, the processor obtains data of the external module by reading data from the register, the external module stores data by writing data to the register through the interface module, and the processor obtains data of the processor by reading data from the register, thereby realizing signal interaction between the external module and the processor.
[0058] Figure 9 is a schematic diagram of accessing a register according to an example embodiment of the present application, as shown in Figure 9 the embedded error correction system further comprises:
[0059] a selector;
[0060] a first input terminal of the selector is connected with the coefficient calculation module, a second input terminal of the selector is connected with the error estimation module, a third input terminal of the selector is connected with the error correction module, a fourth input terminal of the selector is connected with the interface module, and an output terminal of the selector is connected with the register.
[0061] In an embodiment of the present application, the selector can further set other input terminals for the multiplier or the accumulator to access. When the selector determines the access object of the register according to different selection signals, for example, the access object of the register is the coefficient calculation module when the selection signal is 00, the access object of the register is the error estimation module when the selection signal is 01, the access object of the register is the error correction module when the selection signal is 10, and the access object of the register is the interface module when the selection signal is 11.
[0062] In an embodiment of the present application, the embedded error correction system further comprises:
[0063] an analog-to-digital conversion module connected to the error estimation module, configured to perform analog-to-digital conversion on the analog sampling signal and send the analog-to-digital conversion signal to the error estimation module, so that the error estimation module performs error estimation on the analog-to-digital conversion signal;
[0064] a digital-to-analog conversion module connected to the error estimation module, configured to perform digital-to-analog conversion on the digital sampling signal and send the digital-to-analog conversion signal to the error estimation module, so that the error estimation module performs error estimation on the digital-to-analog conversion signal;
[0065] a phase-locked loop connected to the error estimation module, configured to perform clock synchronization operation, modulation operation, demodulation operation, phase synchronization operation or filtering operation on the input signal and send the operated signal to the error estimation module, so that the error estimation module performs error estimation on the operated signal;
[0066] a sensor connected to the error estimation module, configured to send the detection signal to the error estimation module, so that the error estimation module performs error estimation on the detection signal.
[0067] In an embodiment of the present application, the analog-to-digital conversion module can be a multi-channel analog-to-digital conversion module, for example, an n-channel analog-to-digital converter (ADCn). The error sources of the analog-to-digital conversion signal mainly include: offset error, gain error, inter-channel mismatch error and capacitance mismatch error, etc. The digital-to-analog conversion module can be a digital-to-analog converter. The error sources of the digital-to-analog conversion signal mainly include: segmented weight error, inter-channel nonlinearity error, etc. The error source of the detection signal is measurement error, etc.
[0068] Figure 10 is a schematic diagram of the error estimation module shown in an exemplary embodiment of the present application, as Figure 10 shown, the error estimation module comprises:
[0069] a multiplier and an accumulator;
[0070] The first input end of the adder is connected with the analog-digital conversion module, and the second input end of the adder is connected with the register, for adding the analog-digital conversion signal and the pre-stored error correction coefficient in the register to obtain an added signal;
[0071] The input end of the accumulator is connected with the output end of the adder, and the output end of the accumulator is connected with the register, for accumulating the added signal to obtain a first accumulated signal, and writing the first accumulated signal as an error estimation signal into the register for reading by the coefficient calculation module.
[0072] In an embodiment of the present application, the pre-stored error correction coefficient can be a preset offset error correction coefficient before the offset error of the analog-digital conversion signal is corrected, or can be an offset error correction coefficient calculated in the previous period and stored in the register as the pre-stored error correction coefficient during the correction process of the offset error of the analog-digital conversion signal.
[0073] In an embodiment of the present application, the adder and the accumulator are arranged in a digital circuit, and the analog-digital conversion module, the adder, the accumulator and the register are cooperated to realize periodic offset error estimation of the analog-digital conversion signal.
[0074] Figure 11 is a schematic diagram of an error estimation module according to another exemplary embodiment of the present application, in which Figure 11 The error estimation module comprises:
[0075] a squarer, a multiplier and an accumulator;
[0076] The input end of the squarer is connected with the analog-digital conversion module, for calculating the square value of the analog-digital conversion signal;
[0077] The first input end of the multiplier is connected with the output end of the squarer, and the second input end of the multiplier is connected with the register, for multiplying the square value and the pre-stored error correction coefficient in the register to obtain a multiplied signal;
[0078] The first input end of the accumulator is connected with the output end of the multiplier, and the second input end of the accumulator is connected with the register, for accumulating the multiplied signal to obtain a second accumulated signal, and writing the second accumulated signal as an error estimation signal into the register for reading by the coefficient calculation module.
[0079] In an embodiment of the present application, the pre-stored error correction coefficient can be a preset gain error correction coefficient before the gain error of the analog-digital conversion signal is corrected, or can be a gain error correction coefficient calculated in the previous period and stored in the register as the pre-stored error correction coefficient during the correction process of the gain error of the analog-digital conversion signal.
[0080] In an embodiment of the present application, the squarer, the multiplier and the accumulator are arranged in a digital circuit, and the gain error estimation of the analog-to-digital conversion signal is periodically implemented by cooperation of the analog-to-digital conversion module, the squarer, the multiplier, the accumulator and the register.
[0081] Figure 12 is a schematic diagram of an error estimation module according to another exemplary embodiment of the present application, in which Figure 12 The error estimation module comprises:
[0082] a delay unit and a multiplier;
[0083] The first input terminal of the delay unit is connected with the analog-to-digital conversion module, and the second input terminal of the delay unit is connected with the register, for delaying the analog-to-digital conversion signal to obtain a first delayed signal, and for delaying the pre-stored error correction coefficient in the register to obtain a second delayed signal;
[0084] The first input terminal of the multiplier is connected with the output terminal of the delay unit, and the second input terminal of the multiplier is connected with the register, for multiplying the first delayed signal with the analog-to-digital conversion signal to obtain a first correlation signal, and multiplying the second delayed signal with the analog-to-digital conversion signal to obtain a second correlation signal, and writing the first correlation signal and the second correlation signal as error estimation signals into the register for reading by the coefficient calculation module.
[0085] In an embodiment of the present application, the pre-stored error correction coefficient can be a preset inter-channel mismatch error correction coefficient before the inter-channel mismatch error of the analog-to-digital conversion signal is corrected, or can be an inter-channel mismatch error correction coefficient calculated in a previous period and stored in the register as the pre-stored error correction coefficient during the correction of the inter-channel mismatch error of the analog-to-digital conversion signal.
[0086] In an embodiment of the present application, the delay unit and the multiplier are arranged in a digital circuit, and the inter-channel mismatch error estimation of the analog-to-digital conversion signal is periodically implemented by cooperation of the analog-to-digital conversion module, the delay unit, the multiplier and the register.
[0087] In some embodiments of the present application, the error estimation module further has the functions of capacitance mismatch error estimation, front-end non-linear distortion estimation and segmented weight error estimation, and the process of implementing the capacitance mismatch error estimation, the front-end non-linear distortion estimation and the segmented weight error estimation by the error estimation module is not limited herein. After the capacitance mismatch error estimation, the front-end non-linear distortion estimation or the segmented weight error estimation is implemented by the error estimation module, the processor calculates the error correction coefficient according to the error estimation signal, and the error correction module corrects the analog-to-digital conversion signal according to the error correction coefficient.
[0088] In an embodiment of the present application, the external module comprises:
[0089] The external computing module is connected with the interface module, and is configured to obtain the error estimation signal through the interface module, calculate the error correction coefficient, and write the error correction coefficient into the register through the interface module for reading by the error correction module.
[0090] In an embodiment of the present application, the external computing module can be a digital signal processor or a micro control unit, etc. The error correction coefficient can be calculated through the external computing module, and provided to the error correction module for use, so as to meet the requirement of calculating the error correction coefficient through the external computing module.
[0091] In an embodiment of the present application, the external module further comprises:
[0092] The external memory is connected with the interface module, and is configured to obtain the error estimation signal, the error correction coefficient, and the correction result through the interface module, and store the error estimation signal, the error correction coefficient, and the correction result.
[0093] In an embodiment of the present application, the error estimation signal, the error correction coefficient, and the correction result can be stored through the external memory, so as to meet the requirement of storing data through the external memory.
[0094] Embodiments of the present application further provide an embedded integrated circuit comprising the embedded error correction system provided in the above embodiments.
[0095] It should be noted that the embedded integrated circuit provided in the above embodiments and the embedded error correction system provided in the above embodiments belong to the same concept, and the specific operation manner of each module and unit has been described in detail in the system embodiments, which will not be repeated here. In practical application, the above functions can be completed by different functional modules according to the need, i.e. the internal structure of the automobile is divided into different functional modules to complete all or part of the above described functions, which is not limited herein.
[0096] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.
Claims
1. An embedded error correction system, characterized by, The system comprises: The error estimation module is connected with the interface module, and is used for error estimation and sending of an error estimation signal to the interface module; The coefficient calculation module is connected with the interface module, and is used for reading of the error estimation signal and calculation of an error correction coefficient, and sending of the error correction coefficient to the interface module; The error correction module is connected with the interface module, and is used for reading of the error correction coefficient and error correction, and sending of a correction result to the interface module; The interface module is further used for connection with an external module, and providing of the error estimation signal, the error correction coefficient and the correction result for the external module.
2. The embedded error correction system of claim 1, wherein, The system further comprises: A register; The register is connected with the error estimation module, and is used for receiving and storing of the error estimation signal; The register is connected with the coefficient calculation module, and is used for receiving and storing of the error correction coefficient; The register is connected with the error correction module, and is used for receiving and storing of the correction result; The register is connected with the interface module, and is used for providing of the error estimation signal, the error correction coefficient and the correction result for the interface module.
3. The embedded error correction system of claim 2, wherein, The system further comprises: A selector; A first input end of the selector is connected with the coefficient calculation module, a second input end of the selector is connected with the error estimation module, a third input end of the selector is connected with the error correction module, a fourth input end of the selector is connected with the interface module, and an output end of the selector is connected with the register.
4. The embedded error correction system of claim 2, wherein, The system further comprises: An analog-digital conversion module connected with the error estimation module, and used for analog-digital conversion of an analog sampling signal, and sending of an analog-digital conversion signal to the error estimation module, so that the error estimation module performs error estimation on the analog-digital conversion signal; A digital-analog conversion module connected with the error estimation module, and used for digital-analog conversion of a digital sampling signal, and sending of a digital-analog conversion signal to the error estimation module, so that the error estimation module performs error estimation on the digital-analog conversion signal; A phase-locked loop connected with the error estimation module, and used for clock synchronization operation, modulation operation, demodulation operation, phase synchronization operation or filtering operation on an input signal, and sending of an operated signal to the error estimation module, so that the error estimation module performs error estimation on the operated signal; A sensor connected with the error estimation module, and used for sending of a detection signal to the error estimation module, so that the error estimation module performs error estimation on the detection signal.
5. The embedded error correction system of claim 4, wherein, The error estimation module comprises: An adder and an accumulator; A first input end of the adder is connected with the analog-digital conversion module, a second input end of the adder is connected with the register, and is used for addition of the analog-digital conversion signal and an error correction coefficient pre-stored in the register, to obtain an addition signal; The input end of the accumulator is connected with the output end of the adder, and the output end of the accumulator is connected with the register, for accumulating the added signal to obtain a first accumulated signal, and writing the first accumulated signal as the error estimation signal into the register for reading by the coefficient calculation module.
6. The embedded error correction system of claim 4, wherein, The error estimation module comprises: a squarer, a multiplier and an accumulator; The input end of the squarer is connected with the analog-digital conversion module, for calculating the square value of the analog-digital conversion signal; The first input end of the multiplier is connected with the output end of the squarer, and the second input end of the multiplier is connected with the register, for multiplying the square value with the pre-stored error correction coefficient in the register to obtain a multiplied signal; The first input end of the accumulator is connected with the output end of the multiplier, and the second input end of the accumulator is connected with the register, for accumulating the multiplied signal to obtain a second accumulated signal, and writing the second accumulated signal as the error estimation signal into the register for reading by the coefficient calculation module.
7. The embedded error correction system of claim 4, wherein, The error estimation module comprises: a delay device and a multiplier; The first input end of the delay device is connected with the analog-digital conversion module, and the second input end of the delay device is connected with the register, for delaying the analog-digital conversion signal to obtain a first delayed signal, and delaying the pre-stored error correction coefficient in the register to obtain a second delayed signal; The first input end of the multiplier is connected with the output end of the delay device, and the second input end of the multiplier is connected with the register, for multiplying the first delayed signal with the analog-digital conversion signal to obtain a first correlation signal, multiplying the second delayed signal with the analog-digital conversion signal to obtain a second correlation signal, and writing the first correlation signal and the second correlation signal as the error estimation signal into the register for reading by the coefficient calculation module.
8. The embedded error correction system according to any one of claims 2-7, wherein, The external module comprises: an external calculation module connected with the interface module, for acquiring the error estimation signal through the interface module, calculating an error correction coefficient, and writing the error correction coefficient into the register through the interface module for reading by the error correction module.
9. The embedded error correction system according to any one of claims 1-7, wherein, The external module further comprises: an external memory connected with the interface module, for acquiring the error estimation signal, the error correction coefficient and the correction result through the interface module, and storing the error estimation signal, the error correction coefficient and the correction result.
10. An embedded integrated circuit, characterized by An embedded error correction system comprising any one of claims 1 to 9.