Soft start circuit and low dropout regulator

Abstract

The utility model provides a soft start circuit and a low dropout linear regulator, and the soft start circuit comprises a driving unit and a reference unit. The driving unit comprises a first capacitor, starts to charge or discharge the first capacitor in a power-on process, and generates a driving signal when the first capacitor reaches a first potential; the reference unit comprises a second capacitor, is controlled by the driving signal to start charging the second capacitor, and generates a reference signal when the second capacitor reaches a second potential; wherein the establishment speed of the driving signal is set by setting the charging time or the discharging time of the first capacitor, and the establishment speed of the reference signal is at least set based on the establishment speed. According to the low dropout linear regulator, the problem that in the prior art, the output power-on speed of the low dropout linear regulator is too fast is solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrated circuit design technical field, especially to a kind of soft-starting circuit and low dropout linear regulator. BACKGROUND

[0002] Low dropout linear regulator (LDO) as the module that power reference is generated inside chip, is widely applied in chip design, and, LDO power-on also affects the overall function of chip.If LDO does not use soft-starting circuit to control the fast and slow of output power-on in power-on process, the output of LDO will quickly complete power-on and extract large current from power supply instantaneously, so that the work of chip overall can be caused to be not normal.In view of this, design a kind of soft-starting circuit, ensure that LDO will not extract large current from power supply instantaneously in power-on process, it is the technical problem that the technical personnel of the present art urgently want to solve.

[0003] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical scheme of the present application, and to facilitate the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art merely because it is described in the background section of the present application. CONTENT OF THE UTILITY MODEL

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present utility model is to provide a kind of soft-starting circuit and low dropout linear regulator, solve the problem of existing low dropout linear regulator that output power-on is too fast.

[0005] To achieve the above object and other related purposes, the utility model provides a kind of soft-starting circuit, applicable to low dropout linear regulator, comprising:

[0006] Drive unit, including first capacitor, starts to charge or discharge the first capacitor in power-on process, and generates drive signal when the first capacitor reaches first potential;

[0007] Reference unit, including second capacitor, starts to charge the second capacitor under the control of the drive signal, and generates reference signal when the second capacitor reaches second potential;

[0008] Wherein, the establishment speed of the drive signal is set by setting the charging time or discharging time of the first capacitor, and the establishment speed of the reference signal is set based at least on this.

[0009] Optionally, the drive unit further includes a first current source, a first PMOS tube and at least one second PMOS tube;

[0010] When the number of the second PMOS is one, the gate of the first PMOS is connected to the gate of the second PMOS, the source of the first PMOS is connected to the power voltage, the drain of the first PMOS is shorted to its gate and connected to the reference ground through the first current source, the source of the second PMOS is connected to the power voltage, and the drain of the second PMOS is connected to the reference ground through the first capacitor and outputs the driving signal.

[0011] When the number of the second PMOS is more than one, the gate of the first PMOS is connected to the gates of the second PMOS, the source of the first PMOS is connected to the power voltage, the drain of the first PMOS is shorted to its gate and connected to the reference ground through the first current source, the source of the first second PMOS is connected to the power voltage, the drain of the former second PMOS is connected to the source of the latter second PMOS, and the drain of the last second PMOS is connected to the reference ground through the first capacitor and outputs the driving signal.

[0012] Optionally, the reference unit further comprises at least one first NMOS.

[0013] When the number of the first NMOS is one, the gate of the first NMOS receives the driving signal, the drain of the first NMOS is connected to the input signal, and the source of the first NMOS is connected to the reference ground through the second capacitor and outputs the reference signal.

[0014] When the number of the first NMOS is more than one, the gate of each first NMOS receives the driving signal, the drain of the first first NMOS is connected to the input signal, the source of the former first NMOS is connected to the drain of the latter first NMOS, and the source of the last first NMOS is connected to the reference ground through the second capacitor and outputs the reference signal.

[0015] Optionally, the driving unit further comprises a second current source, a second NMOS and at least one third NMOS.

[0016] When the number of the third NMOS is one, the gate of the second NMOS is connected to the gate of the third NMOS, the source of the second NMOS is connected to the reference ground, the drain of the second NMOS is shorted to its gate and connected to the power voltage through the second current source, the source of the third NMOS is connected to the reference ground, and the drain of the third NMOS is connected to the power voltage through the first capacitor and outputs the driving signal.

[0017] When the number of the third NMOS tubes is more than one, the gate of the second NMOS tube is connected with the gate of each of the third NMOS tubes, the source of the second NMOS tube is connected with a reference ground, the drain of the second NMOS tube is short-circuited with the gate of the second NMOS tube and connected with a power voltage through the second current source, the source of the first third NMOS tube is connected with the reference ground, the drain of the previous third NMOS tube is connected with the source of the next third NMOS tube, and the drain of the last third NMOS tube is connected with the power voltage through the first capacitor and outputs the driving signal.

[0018] Optionally, the reference unit further comprises at least one third PMOS tube.

[0019] When the number of the third PMOS tubes is one, the gate of the third PMOS tube receives the driving signal, the source of the third PMOS tube is connected with an input signal, and the drain of the third PMOS tube is connected with a reference ground through the second capacitor and outputs the reference signal.

[0020] When the number of the third PMOS tubes is more than one, the gate of each of the third PMOS tubes receives the driving signal, the source of the first third PMOS tube is connected with the input signal, the drain of the previous third PMOS tube is connected with the source of the next third PMOS tube, and the drain of the last third PMOS tube is connected with the reference ground through the second capacitor and outputs the reference signal.

[0021] The utility model further provides a low voltage difference linear regulator, include:

[0022] The soft start circuit according to any one of the above;

[0023] The voltage stabilizing output circuit is connected with the soft start circuit, and is used for providing an output signal, wherein the establishment speed of the output signal is set by setting the establishment speed of the reference signal.

[0024] Optionally, the voltage stabilizing output circuit comprises a power tube, a feedback unit and an amplification unit.

[0025] The control end of the power tube receives a control signal, the first end of the power tube is connected with a power voltage, and the second end of the power tube outputs the output signal.

[0026] The feedback unit samples the output signal and outputs a feedback signal.

[0027] The amplification unit is connected with the soft start circuit and the feedback unit respectively, and outputs the control signal based on the reference signal and the feedback signal.

[0028] Optionally, the voltage stabilizing output circuit further comprises a third capacitor connected between the second end of the power tube and a reference ground.

[0029] Optionally, the feedback unit comprises a first resistor and a second resistor; a first end of the first resistor receives the output signal, and a second end of the first resistor is connected to a reference ground through the second resistor and outputs the feedback signal.

[0030] Optionally, the amplification unit comprises a fourth NMOS tube, a fifth NMOS tube, a fourth PMOS tube, a fifth PMOS tube and a third current source; a gate of the fourth NMOS tube receives the feedback signal, a source of the fourth NMOS tube is connected to a source of the fifth NMOS tube and connected to a reference ground through the third current source, a drain of the fourth NMOS tube is connected to a drain of the fourth PMOS tube, a gate of the fifth NMOS tube receives the reference signal, a drain of the fifth NMOS tube is connected to a drain of the fifth PMOS tube and outputs the control signal, a gate of the fourth PMOS tube is connected to a gate of the fifth PMOS tube, a source of the fourth PMOS tube is connected to a power voltage, a drain of the fourth PMOS tube is shorted to the gate thereof, and a source of the fifth PMOS tube is connected to the power voltage.

[0031] As described above, the soft start circuit and the low-dropout linear voltage regulator can slow down the establishment speed of the reference signal during the power-on process, ensure that the low-dropout linear voltage regulator does not instantaneously draw a large current from the power supply during the power-on process, and thus avoid affecting the normal operation of other circuits in the low-dropout linear voltage regulator. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 Fig. 1 shows a structure schematic diagram of a soft start circuit in an embodiment of the present application.

[0033] Figure 2 Fig. 2 shows another structure schematic diagram of the soft start circuit in the embodiment of the present application.

[0034] Figure 3 Fig. 3 shows a structure schematic diagram of a soft start circuit in another embodiment of the present application.

[0035] Figure 4 Fig. 4 shows another structure schematic diagram of the soft start circuit in the embodiment of the present application.

[0036] Figure 5 Fig. 5 shows a structure schematic diagram of a low-dropout linear voltage regulator in an embodiment of the present application.

[0037] Figure 6 Fig. 6 shows another structure schematic diagram of the low-dropout linear voltage regulator in the embodiment of the present application.

[0038] Component designation explanation

[0039] 100 Low Dropout Linear Regulator

[0040] 110 Soft-start circuit

[0041] 111 Drive Unit

[0042] 112 Reference Unit

[0043] 120V Regulated Output Circuit

[0044] 121 Feedback Unit

[0045] 122 Amplification Units Detailed Implementation

[0046] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.

[0047] Please see Figures 1 to 6 It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the scope of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this invention, should still fall within the scope of the disclosed technical content. Furthermore, the terms "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of this invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this invention.

[0048] Example 1

[0049] like Figure 1 and Figure 2 As shown, this embodiment provides a soft-start circuit 110, including a drive unit 111 and a reference unit 112. The soft-start circuit 110 of this embodiment is suitable for low dropout linear regulators (LDOs). By slowing down the establishment speed of the reference signal Vref, it ensures that the LDO will not draw a large current from the power supply instantaneously during the power-on process, thereby avoiding affecting the normal operation of other circuits in the LDO.

[0050] The driving unit 111 includes a first capacitor C1, and starts charging the first capacitor C1 in the power-on process, and generates the driving signal Ssc when the first capacitor C1 is charged to the first electric potential; wherein the establishment speed of the driving signal Ssc is set by setting the charging time of the first capacitor C1. In an embodiment, in addition to including the first capacitor C1, the driving unit 111 also includes a first current source I1, a first PMOS tube MP1 and at least one second PMOS tube.

[0051] For the case that the number of the second PMOS tubes is one, the second PMOS tube is marked as MP2, as shown in Figure 1 ; wherein the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2, the source of the first PMOS tube MP1 is connected to the power supply voltage VDD, the drain of the first PMOS tube MP1 is shorted with its gate and connected to the reference ground GND through the first current source I1, the source of the second PMOS tube MP2 is connected to the power supply voltage VDD, and the drain of the second PMOS tube MP2 is connected to the reference ground GND through the first capacitor C1 and outputs the driving signal Ssc.

[0052] The first PMOS tube MP1 and the second PMOS tube MP2 constitute a current mirror structure, and by setting the width-length ratio of the first PMOS tube MP1 and the second PMOS tube MP2, the current mirror ratio of the current mirror structure is set, that is, the charging current of the first capacitor C1 is set, so as to set the charging time of the first capacitor C1. In the example, the driving signal Ssc is generated when the first capacitor C1 is charged from the ground potential to the power supply potential, and by reducing the charging current of the first capacitor C1 to prolong the charging time, the establishment speed of the driving signal Ssc is slowed down.

[0053] For the case that the number of the second PMOS tubes is more than one, each second PMOS tube is marked as MP21, MP22, etc., as shown in Figure 2 ; wherein the gate of the first PMOS tube MP1 is connected to the gate of each second PMOS tube, the source of the first PMOS tube MP1 is connected to the power supply voltage VDD, the drain of the first PMOS tube MP1 is shorted with its gate and connected to the reference ground GND through the first current source I1, the source of the first second PMOS tube MP21 is connected to the power supply voltage VDD, the drain of the previous second PMOS tube is connected to the source of the next second PMOS tube, and the drain of the last second PMOS tube is connected to the reference ground GND through the first capacitor C1 and outputs the driving signal Ssc.

[0054] Taking the number of the second PMOS tubes as four as an example, the gate of the first PMOS tube MP1 is connected with the gates of the second PMOS tubes, the source of the first PMOS tube MP1 is connected with the power supply voltage VDD, the drain of the first PMOS tube MP1 is short-circuited with the gate of the first PMOS tube MP1 and connected with the reference ground GND through the first current source I1, the source of the first second PMOS tube MP21 is connected with the power supply voltage VDD, the drain of the first second PMOS tube MP21 is connected with the source of the second second PMOS tube MP22, the drain of the second second PMOS tube MP22 is connected with the source of the third second PMOS tube MP23, the drain of the third second PMOS tube MP23 is connected with the source of the fourth second PMOS tube MP24, the drain of the fourth second PMOS tube MP24 is connected with the reference ground GND through the first capacitor C1 and outputs the driving signal Ssc.

[0055] The second PMOS tubes in series can be equivalent to one PMOS tube, and the width-length ratio of the equivalent PMOS tube can be adjusted by connecting the second PMOS tubes in series, the first PMOS tube MP1 and the equivalent PMOS tube constitute a current mirror structure, and the width-length ratio of the first PMOS tube MP1 and the equivalent PMOS tube is set to set the current mirror ratio of the current mirror structure, that is, the charging current of the first capacitor C1 is set, so as to set the charging time of the first capacitor C1. In the example, the driving signal Ssc is generated when the first capacitor C1 is charged from the ground potential to the power supply potential, and the charging time is prolonged by reducing the charging current of the first capacitor C1, so as to slow down the establishment speed of the driving signal Ssc.

[0056] The reference unit 112 includes a second capacitor C2, and the second capacitor C2 is charged under the control of the driving signal Ssc, and the reference signal Vref is generated when the second capacitor C2 is charged to the second potential; wherein the establishment speed of the reference signal Vref is set at least by setting the establishment speed of the driving signal Ssc. In an embodiment, the reference unit 112 includes at least one first NMOS tube in addition to the second capacitor C2.

[0057] For the case that the number of the first NMOS tube is one, the first NMOS tube is marked as MN1, as shown in Figure 1 The gate of the first NMOS tube MN1 receives the driving signal Ssc, the drain of the first NMOS tube MN1 inputs the input signal Vin, and the source of the first NMOS tube MN1 is connected with the reference ground GND through the second capacitor C2 and outputs the reference signal Vref.

[0058] The first NMOS transistor MN1 is used as a switch transistor and is turned on based on the driving signal Ssc, such as being turned on when the driving signal Ssc is a power supply potential, and the input signal Vin is converted into a charging current of the second capacitor C2 based on the on-resistance of the first NMOS transistor MN1; in this example, the reference signal Vref is generated when the second capacitor C2 is charged from a ground potential to an input potential, and the turn-on time of the first NMOS transistor MN1 is delayed by slowing down the establishment speed of the driving signal Ssc, so as to slow down the establishment speed of the reference signal Vref.

[0059] For the case that the number of the first NMOS transistors is greater than one, each first NMOS transistor is marked as MN11, MN12, and the like, as shown in Figure 2 The gate of each first NMOS transistor receives the driving signal Ssc, the drain of the first first NMOS transistor is connected to the input signal Vin, the source of the previous first NMOS transistor is connected to the drain of the next first NMOS transistor, and the source of the last first NMOS transistor is connected to the reference ground GND through the second capacitor C2 and outputs the reference signal Vref.

[0060] Taking the number of the first NMOS transistors as four as an example, the gate of each first NMOS transistor receives the driving signal Ssc, the drain of the first first NMOS transistor MN11 is connected to the input signal Vin, the source of the first first NMOS transistor MN11 is connected to the drain of the second first NMOS transistor MN12, the source of the second first NMOS transistor MN12 is connected to the drain of the third first NMOS transistor MN13, the source of the third first NMOS transistor MN13 is connected to the drain of the fourth first NMOS transistor MN14, and the source of the fourth first NMOS transistor MN14 is connected to the reference ground GND through the second capacitor C2 and outputs the reference signal Vref.

[0061] Each first NMOS transistor is used as a switch transistor, and the on-resistance can be adjusted by connecting the first NMOS transistors in series, so as to adjust the charging current of the second capacitor C2 and thus adjust the charging time; in this example, the reference signal Vref is generated when the second capacitor C2 is charged from a ground potential to an input potential, the turn-on time of each first NMOS transistor is delayed by slowing down the establishment speed of the driving signal Ssc, and then the charging current of the second capacitor C2 is reduced by using a large on-resistance, and the charging time is thus prolonged, so as to slow down the establishment speed of the reference signal Vref.

[0062] Embodiment Two

[0063] As Figure 3 and Figure 4As shown, the embodiment provides a soft start circuit 110, which comprises a driving unit 111 and a reference unit 112; the soft start circuit 110 of the embodiment is applicable to a low dropout linear regulator (LDO), and by slowing down the establishment speed of a reference signal Vref, it ensures that the LDO will not instantaneously draw a large current from a power supply during power-on, thereby avoiding affecting the normal work of other circuits in the LDO.

[0064] The driving unit 111 comprises a first capacitor C1, discharges the first capacitor C1 at the beginning of the power-on process, and generates a driving signal Ssc when the first capacitor C1 is discharged to a first electric potential; wherein the establishment speed of the driving signal Ssc is set by setting the discharge time of the first capacitor C1. In an implementation manner, the driving unit 111 comprises a second current source I2, a second NMOS transistor MN2 and at least one third NMOS transistor in addition to the first capacitor C1.

[0065] For the case that the number of the third NMOS transistors is one, the third NMOS transistor is marked as MN3, as shown in Figure 3 ; wherein the gate of the second NMOS transistor MN2 is connected to the gate of the third NMOS transistor MN3, the source of the second NMOS transistor MN2 is connected to a reference ground GND, the drain of the second NMOS transistor MN2 is short-circuited with its gate and connected to a power supply voltage VDD through the second current source I2, the source of the third NMOS transistor MN3 is connected to the reference ground GND, and the drain of the third NMOS transistor MN3 is connected to the power supply voltage VDD through the first capacitor C1 and outputs the driving signal.

[0066] The second NMOS transistor MN2 and the third NMOS transistor MN3 constitute a current mirror structure, and by setting the width-length ratio of the second NMOS transistor MN2 and the third NMOS transistor MN3, the current mirror ratio of the current mirror structure is set, that is, the discharge current of the first capacitor C1 is set, thereby the discharge time of the first capacitor C1 is set. In the example, the driving signal Ssc is generated when the first capacitor C1 is discharged from the power supply potential to the ground potential, and by reducing the discharge current of the first capacitor C1 to prolong the discharge time, the establishment speed of the driving signal Ssc is slowed down.

[0067] For the case that the number of the third NMOS transistors is more than one, each third NMOS transistor is marked as MN31, MN32, etc., as shown in Figure 4The gate of the second NMOS transistor MN2 is connected to the gates of the third NMOS transistors, the source of the second NMOS transistor MN2 is connected to the reference ground GND, the drain of the second NMOS transistor MN2 is shorted to the gate of the second NMOS transistor MN2 and connected to the power supply voltage VDD through the second current source I2, the source of the first third NMOS transistor MN31 is connected to the reference ground GND, the drain of the first third NMOS transistor MN31 is connected to the source of the second third NMOS transistor MN32, the drain of the second third NMOS transistor MN32 is connected to the source of the third third NMOS transistor MN33, the drain of the third third NMOS transistor MN33 is connected to the source of the fourth third NMOS transistor MN34, and the drain of the fourth third NMOS transistor MN34 is connected to the power supply voltage VDD through the first capacitor C1 and outputs the driving signal Ssc.

[0068] The gate of the second NMOS transistor MN2 is connected to the gates of the third NMOS transistors, the source of the second NMOS transistor MN2 is connected to the reference ground GND, the drain of the second NMOS transistor MN2 is shorted to the gate of the second NMOS transistor MN2 and connected to the power supply voltage VDD through the second current source I2, the source of the first third NMOS transistor MN31 is connected to the reference ground GND, the drain of the first third NMOS transistor MN31 is connected to the source of the second third NMOS transistor MN32, the drain of the second third NMOS transistor MN32 is connected to the source of the third third NMOS transistor MN33, the drain of the third third NMOS transistor MN33 is connected to the source of the fourth third NMOS transistor MN34, and the drain of the fourth third NMOS transistor MN34 is connected to the power supply voltage VDD through the first capacitor C1 and outputs the driving signal Ssc.

[0069] The third NMOS transistors in series can be equivalent to an NMOS transistor, and the width-length ratio of the equivalent NMOS transistor can be adjusted by connecting the third NMOS transistors in series. The second NMOS transistor MN2 and the equivalent NMOS transistor constitute a current mirror structure, and the width-length ratio of the second NMOS transistor MN2 and the equivalent NMOS transistor is set to set the current mirror ratio of the current mirror structure, that is, to set the discharge current of the first capacitor C1, thereby setting the discharge time of the first capacitor C1. In the example, the driving signal Ssc is generated when the first capacitor C1 is discharged from the power supply potential to the ground potential. By reducing the discharge current of the first capacitor C1, the discharge time is prolonged, and thus the establishment speed of the driving signal Ssc is slowed down.

[0070] The reference unit 112 includes a second capacitor C2, and starts charging the second capacitor C2 under the control of the driving signal Ssc, and generates a reference signal Vref when the second capacitor C2 is charged to a second potential. At least by setting the establishment speed of the driving signal Ssc, the establishment speed of the reference signal Vref is set. In an embodiment, the reference unit 112 includes at least one third PMOS transistor in addition to the second capacitor C2.

[0071] For the case where the number of the third PMOS transistors is one, the third PMOS transistor is marked as MP3, as shown inFigure 3 As shown in the figure; wherein the gate of the third PMOS MP3 receives the driving signal Ssc, the source of the third PMOS MP3 accesses the input signal Vin, and the drain of the third PMOS MP3 is connected to the reference ground GND through the second capacitor C2 and outputs the reference signal Vref.

[0072] The third PMOS MP3 is used as a switch tube and is turned on based on the driving signal Ssc, such as when the driving signal Ssc is at ground potential, and the input signal Vin is converted into the charging current of the second capacitor C2 based on the on-resistance of the third PMOS MP3; in this example, the reference signal Vref is generated when the second capacitor C2 is charged from ground potential to input potential, and the establishment speed of the reference signal Vref is slowed down by slowing down the establishment speed of the driving signal Ssc to delay the opening time of the third PMOS MP3.

[0073] For the case where the number of third PMOS tubes is greater than one, each third PMOS tube is marked as MP31, MP32, etc., as shown in the figure. Figure 4 As shown in the figure; wherein the gate of each third PMOS receives the driving signal Ssc, the source of the first third PMOS MP31 accesses the input signal Vin, the drain of the previous third PMOS is connected to the source of the next third PMOS, and the drain of the last third PMOS is connected to the reference ground GND through the second capacitor C2 and outputs the reference signal Vref.

[0074] Taking the number of third PMOS tubes as an example, the gate of each third PMOS receives the driving signal Ssc, the source of the first third PMOS MP31 accesses the input signal Vin, the drain of the first third PMOS MP31 is connected to the source of the second third PMOS MP32, the drain of the second third PMOS MP32 is connected to the source of the third third PMOS MP33, the drain of the third third PMOS MP33 is connected to the source of the fourth third PMOS MP34, and the drain of the fourth third PMOS MP34 is connected to the reference ground GND through the second capacitor C2 and outputs the reference signal Vref.

[0075] Each third PMOS tube is used as a switch tube, and the on-resistance can be adjusted by connecting the third PMOS tubes in series, so as to adjust the charging current of the second capacitor C2, thereby adjusting the charging time; in this example, the reference signal Vref is generated when the second capacitor C2 is charged from ground potential to input potential, the establishment speed of the reference signal Vref is slowed down by slowing down the establishment speed of the driving signal Ssc to delay the opening time of each third PMOS, and then the large on-resistance is used to reduce the charging current of the second capacitor C2 and thereby to prolong the charging time, thereby slowing down the establishment speed of the reference signal Vref.

[0076] Embodiment three

[0077] As Figure 5 and Figure 6 The embodiment provides a low-dropout linear voltage regulator 100, which comprises a soft-start circuit 110 and a voltage output circuit 120.

[0078] The soft-start circuit 110 is implemented by the circuit structure described in Embodiment One or Embodiment Two, and the related content can be found in the foregoing, which will not be described here.

[0079] The voltage output circuit 120 is connected with the soft-start circuit 110 and is configured to provide an output signal Vout; wherein the establishment speed of the output signal Vout is set by setting the establishment speed of a reference signal Vref. In an embodiment, the voltage output circuit 120 comprises a power transistor M0, a feedback unit 121 and an amplification unit 122; further, the voltage output circuit 120 further comprises a third capacitor C3.

[0080] The control terminal of the power transistor M0 receives a control signal Drv, the first end of the power transistor M0 is connected with a power supply voltage VDD, and the second end of the power transistor M0 outputs the output signal Vout. Wherein the power transistor M0 is a PMOS transistor, the control terminal is a gate, the first end is a source, and the second end is a drain.

[0081] The feedback unit 121 samples the output signal Vout and outputs a feedback signal Vfb. In an example, the feedback unit 121 comprises a first resistor R1 and a second resistor R2; wherein the first end of the first resistor R1 receives the output signal Vout, and the second end of the first resistor R1 is connected with a reference ground GND through the second resistor R2 and outputs the feedback signal Vfb.

[0082] The amplification unit 122 is connected with the soft-start circuit 110 and the feedback unit 121 respectively, and outputs the control signal Drv based on the reference signal Vref and the feedback signal Vfb. In an example, the amplification unit 122 comprises a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5 and a third current source I3.

[0083] The gate of the fourth NMOS transistor MN4 receives a feedback signal Vfb, the source of the fourth NMOS transistor MN4 is connected with the source of the fifth NMOS transistor MN5 and is connected to a reference ground GND through the third current source I3, the drain of the fourth NMOS transistor MN4 is connected to the drain of the fourth PMOS transistor MP4, the gate of the fifth NMOS transistor MN5 receives a reference signal Vref, the drain of the fifth NMOS transistor MN5 is connected to the drain of the fifth PMOS transistor MP5 and outputs a control signal Drv, the gate of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5, the source of the fourth PMOS transistor MP4 is connected to a power supply voltage VDD, the drain of the fourth PMOS transistor MP5 is short-circuited to the gate thereof, and the source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD.

[0084] The third capacitor C3 is connected between the second end of the power transistor M0 and the reference ground GND, and performs output filtering processing on the output signal Vout.

[0085] In the low-dropout linear regulator 100 of the embodiment, the opening time of the power transistor M0 is regulated based on the error amplification result of the feedback signal Vfb and the reference signal Vref, so that the output signal Vout is stabilized at a target value. During the power-on process, based on the design of the soft-start circuit 110 (including the driving unit 111 and the reference unit 112), a slowly-changing driving signal Ssc is generated by using a capacitor charging and discharging model to control the gate of the post-stage switching transistor, so that the post-stage switching transistor experiences a process from high resistance to low resistance, thereby slowing down the establishment speed of the reference signal Vref to avoid instantaneous large current extraction from the power supply.

[0086] In summary, the soft-start circuit and the low-dropout linear regulator can slow down the establishment speed of the reference signal during the power-on process, ensure that the low-dropout linear regulator does not instantaneously extract large current from the power supply during the power-on process, and thus avoid affecting the normal operation of other circuits in the low-dropout linear regulator.

[0087] The above embodiments only exemplarily illustrate the principles and effects of the utility model, and are not used to limit the utility model. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and category of the utility model. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the utility model should be covered by the claims of the utility model.

Claims

1. A soft-start circuit adapted for use in a low-dropout linear regulator, characterized by, include: The driving unit includes a first capacitor, which starts charging or discharging the first capacitor during power-on and generates a driving signal when the first capacitor reaches a first potential. The reference unit includes a second capacitor, which is controlled by the drive signal to start charging the second capacitor and generates a reference signal when the second capacitor reaches a second potential; The establishment speed of the drive signal is set by setting the charging time or discharging time of the first capacitor, and the establishment speed of the reference signal is set based on this.

2. The soft start circuit of claim 1, wherein, The driving unit further includes a first current source, a first PMOS transistor, and at least one second PMOS transistor; When there is one second PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is shorted to its gate and connected to the reference ground through the first current source, the source of the second PMOS transistor is connected to the power supply voltage, and the drain of the second PMOS transistor is connected to the reference ground through the first capacitor and outputs the drive signal. When the number of second PMOS transistors is greater than one, the gate of the first PMOS transistor is connected to the gate of each second PMOS transistor, the source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is shorted to its gate and connected to the reference ground through the first current source, the source of the first second PMOS transistor is connected to the power supply voltage, the drain of the previous second PMOS transistor is connected to the source of the next second PMOS transistor, and the drain of the last second PMOS transistor is connected to the reference ground through the first capacitor and outputs the drive signal.

3. The soft start circuit of claim 2, wherein, The reference unit further includes at least one first NMOS transistor; When there is only one NMOS transistor, the gate of the first NMOS transistor receives the driving signal, the drain of the first NMOS transistor is connected to the input signal, and the source of the first NMOS transistor is connected to the reference ground through the second capacitor and outputs the reference signal. When the number of first NMOS transistors is greater than one, the gate of each first NMOS transistor receives the driving signal, the drain of the first first NMOS transistor is connected to the input signal, the source of the previous first NMOS transistor is connected to the drain of the next first NMOS transistor, and the source of the last first NMOS transistor is connected to the reference ground via the second capacitor and outputs the reference signal.

4. The soft start circuit of claim 1, wherein, The driving unit further includes a second current source, a second NMOS transistor, and at least one third NMOS transistor; When there is one third NMOS transistor, the gate of the second NMOS transistor is connected to the gate of the third NMOS transistor, the source of the second NMOS transistor is connected to the reference ground, the drain of the second NMOS transistor is shorted to its gate and connected to the power supply voltage through the second current source, the source of the third NMOS transistor is connected to the reference ground, and the drain of the third NMOS transistor is connected to the power supply voltage through the first capacitor and outputs the drive signal. When the number of the third NMOS is more than one, the gate of the second NMOS is connected to the gate of each of the third NMOS, the source of the second NMOS is connected to the reference ground, the drain of the second NMOS is shorted to the gate of the second NMOS and connected to the power voltage through the second current source, the source of the first third NMOS is connected to the reference ground, the drain of the previous third NMOS is connected to the source of the next third NMOS, and the drain of the last third NMOS is connected to the power voltage through the first capacitor and outputs the driving signal.

5. The soft start circuit of claim 4, wherein, The reference unit further comprises at least one third PMOS; When the number of the third PMOS is one, the gate of the third PMOS receives the driving signal, the source of the third PMOS is connected to the input signal, and the drain of the third PMOS is connected to the reference ground through the second capacitor and outputs the reference signal. When the number of the third PMOS is more than one, the gate of each of the third PMOS receives the driving signal, the source of the first third PMOS is connected to the input signal, the drain of the previous third PMOS is connected to the source of the next third PMOS, and the drain of the last third PMOS is connected to the reference ground through the second capacitor and outputs the reference signal.

6. A low-dropout linear voltage regulator, characterized by, The soft start circuit comprises: The soft start circuit according to any one of claims 1-5; The voltage stabilizing output circuit is connected to the soft start circuit and is configured to provide an output signal, wherein the establishment speed of the output signal is set by setting the establishment speed of the reference signal.

7. The low dropout linear regulator of claim 6, wherein, The voltage stabilizing output circuit comprises a power tube, a feedback unit and an amplification unit. The control end of the power tube receives a control signal, the first end of the power tube is connected to a power voltage, and the second end of the power tube outputs the output signal. The feedback unit samples the output signal and outputs a feedback signal. The amplification unit is connected to the soft start circuit and the feedback unit respectively and outputs the control signal based on the reference signal and the feedback signal.

8. The low dropout linear regulator of claim 7, wherein, The voltage stabilizing output circuit further comprises a third capacitor connected between the second end of the power tube and a reference ground.

9. The low dropout linear regulator of claim 7 or 8, wherein, The feedback unit comprises a first resistor and a second resistor, the first end of the first resistor receives the output signal, and the second end of the first resistor is connected to the reference ground through the second resistor and outputs the feedback signal.

10. The low dropout linear regulator of claim 7 or 8, wherein, The amplification unit comprises a fourth NMOS transistor, a fifth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a third current source; the gate of the fourth NMOS transistor receives the feedback signal, the source of the fourth NMOS transistor is connected with the source of the fifth NMOS transistor and is connected with a reference ground through the third current source, the drain of the fourth NMOS transistor is connected with the drain of the fourth PMOS transistor, the gate of the fifth NMOS transistor receives the reference signal, the drain of the fifth NMOS transistor is connected with the drain of the fifth PMOS transistor and outputs the control signal, the gate of the fourth PMOS transistor is connected with the gate of the fifth PMOS transistor, the source of the fourth PMOS transistor is connected with a power supply voltage, the drain of the fourth PMOS transistor is short-circuited with the gate of the fourth PMOS transistor, and the source of the fifth PMOS transistor is connected with the power supply voltage.

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