Circuit and system based on closed-loop control

Abstract

The utility model provides a circuit and a system based on closed-loop control, and belongs to the technical field of control circuits. The circuit comprises a bus voltage acquisition circuit, wherein one end of the bus voltage acquisition circuit is used for being connected with a drain electrode of a silicon carbide MOS module; one end of the FPGA chip is connected with the other end of the bus voltage acquisition circuit; one end of the self-adaptive push-pull matrix circuit is connected with the other end of the FPGA chip, the other end of the self-adaptive push-pull matrix circuit is connected with the grid electrode of the silicon carbide MOS module, and the self-adaptive push-pull matrix circuit is used for matching the resistance value of the real-time bus voltage value according to the collected real-time bus voltage value so as to control the silicon carbide MOS module to be in the optimal operation state. According to the utility model, the resistance value of the gate driving resistance circuit can be adaptively adjusted through closed-loop control under various bus voltage electric wave scenes so as to provide more adaptive gate driving voltage and current, and the multi-path selection switch is controlled so as to be suitable for various working scenes.

Description

TECHNICAL FIELD

[0001] The utility model relates to control circuit technical field, concretely relates to a circuit and system based on closed loop control. BACKGROUND

[0002] With the rapid development of electric vehicle drive system, as one of the core control components, the performance and stability of electric vehicle drive board have important influence on the efficiency and safety of the whole electric vehicle drive system. In the electric vehicle drive board, silicon carbide MOS (metal-oxide semiconductor field effect transistor) module is often used as a high-frequency switching element to control the drive of the electric motor. However, due to the fluctuation of power supply voltage in the working environment of electric vehicles, in order to ensure the normal switching operation of the silicon carbide MOS module, the gate drive voltage needs to be maintained within a certain range. Therefore, with the change of power supply voltage, the gate drive resistance needs to be adjusted in time.

[0003] In the prior art, the adjustment of gate drive resistance usually depends on fixed external resistance or mechanical adjustment, but these methods have significant defects. First of all, traditional manual adjustment or fixed resistance cannot quickly and accurately respond to voltage changes when the power supply voltage fluctuates greatly, resulting in unstable switching characteristics of the silicon carbide MOS module, and even may cause circuit failure or system performance degradation. Secondly, manual adjustment of resistance increases the complexity of system design, and is not conducive to automated production and debugging. In addition, the gate drive resistance in the traditional circuit cannot be dynamically adjusted according to the actual working conditions, so there are limitations on the adaptability and stability of electric vehicles under different operating conditions.

[0004] Therefore, how to automatically adjust the gate drive resistance during the change of power supply voltage and ensure that the silicon carbide MOS module always maintains stable working state under various voltage fluctuation conditions has become a technical problem in the design of electric vehicle drive board. UTILITY MODEL CONTENTS

[0005] The utility model aims at providing a circuit and system based on closed loop control, which can adaptively adjust the resistance value of the gate drive resistance circuit to provide more adaptive gate drive voltage and current under various bus voltage wave scenarios through closed loop control, and can be applied to various working scenarios through the control of the multi-way selection switch, and through the connection with the battery cell, the logical judgment of voltage level can be directly made at the hardware level, the delay is low and the customization processing can be realized.

[0006] In order to realize the above-mentioned purpose, the utility model provides a circuit based on closed loop control, which comprises:

[0007] A bus voltage acquisition circuit, one end of the bus voltage acquisition circuit is used for connecting with a drain of a silicon carbide MOS module, and the bus voltage acquisition circuit is used for acquiring a real-time bus voltage value;

[0008] An FPGA chip, one end of the FPGA chip is connected with the other end of the bus voltage acquisition circuit;

[0009] An adaptive push-pull matrix circuit, one end of the adaptive push-pull matrix circuit is connected with the other end of the FPGA chip, and one end of the adaptive push-pull matrix circuit is connected with a gate of the silicon carbide MOS module, and the adaptive push-pull matrix circuit is used for matching a resistance value of the real-time bus voltage value according to the acquired real-time bus voltage value, so as to control the silicon carbide MOS module to be in an optimal operating state.

[0010] Optionally, the circuit further comprises:

[0011] An MCU master chip, used for outputting a continuous and stable PWM wave to drive the silicon carbide MOS module;

[0012] An isolation circuit, one end of the isolation circuit is connected with one end of the adaptive push-pull matrix circuit, and the other end of the isolation circuit is connected with one end of the MCU master chip.

[0013] Optionally, the adaptive push-pull matrix circuit comprises a multipath selection switch, one end of the multipath selection switch is connected with the other end of the FPGA chip, and one end of the multipath selection switch is connected with one end of the isolation circuit, and the multipath selection switch comprises a first switch, a second switch and a third switch.

[0014] Optionally, the adaptive push-pull matrix circuit further comprises:

[0015] A power supply;

[0016] A first resistor, one end of the first resistor is connected with a positive electrode of the power supply;

[0017] A first triode, a base of the first triode is connected with the first switch of the multipath selection switch, a collector of the first triode is connected with the other end of the first resistor, and an emitter of the first triode is connected with the gate of the silicon carbide MOS module;

[0018] A second resistor, one end of the second resistor is connected with the positive electrode of the power supply;

[0019] A second triode, a base of the second triode is connected with the second switch of the multipath selection switch, a collector of the second triode is connected with the other end of the second resistor, and an emitter of the second triode is connected with the gate of the silicon carbide MOS module;

[0020] A third resistor, one end of the third resistor is connected with the positive pole of the power supply;

[0021] A third transistor, the base of the third transistor is connected with the third switch of the multi-way selection switch, the collector of the third transistor is connected with the other end of the third resistor, and the emitter of the third transistor is connected with the gate of the silicon carbide MOS module;

[0022] A fourth resistor, one end of the fourth resistor is connected with the negative pole of the power supply;

[0023] A fourth transistor, the base of the fourth transistor is connected with the first switch of the multi-way selection switch, the collector of the fourth transistor is connected with the other end of the fourth resistor, and the emitter of the fourth transistor is connected with the gate of the silicon carbide MOS module;

[0024] A fifth resistor, one end of the fifth resistor is connected with the negative pole of the power supply;

[0025] A fifth transistor, the base of the fifth transistor is connected with the second switch of the multi-way selection switch, the collector of the fifth transistor is connected with the other end of the fifth resistor, and the emitter of the fifth transistor is connected with the gate of the silicon carbide MOS module;

[0026] A sixth resistor, one end of the sixth resistor is connected with the negative pole of the power supply;

[0027] A sixth transistor, the base of the sixth transistor is connected with the third switch of the multi-way selection switch, the collector of the sixth transistor is connected with the other end of the sixth resistor, and the emitter of the sixth transistor is connected with the gate of the silicon carbide MOS module.

[0028] Optionally, the first transistor, the second transistor and the third transistor are NPN type transistors, and the fourth transistor, the fifth transistor and the sixth transistor are PNP type transistors.

[0029] In another aspect, the utility model also provides a system based on closed loop control, the system includes:

[0030] A silicon carbide MOS module, the source of the silicon carbide MOS module is grounded;

[0031] A bus voltage acquisition circuit, one end of the bus voltage acquisition circuit is connected with the drain of the silicon carbide MOS module, and the bus voltage acquisition circuit is used for acquiring a real-time bus voltage value;

[0032] An FPGA chip, one end of the FPGA chip is connected with the other end of the bus voltage acquisition circuit;

[0033] An adaptive push-pull matrix circuit, one end of the adaptive push-pull matrix circuit is connected with the other end of the FPGA chip, one end of the adaptive push-pull matrix circuit is connected with the gate of the silicon carbide MOS module, and the adaptive push-pull matrix circuit is used for matching the resistance value of the real-time bus voltage value according to the collected real-time bus voltage value, so as to control the silicon carbide MOS module to be in the best operating state.

[0034] Optionally, the system further comprises:

[0035] An MCU master chip is configured to output a continuous and stable PWM wave to drive the silicon carbide MOS module.

[0036] An isolation circuit, one end of the isolation circuit is connected with one end of the adaptive push-pull matrix circuit, and the other end of the isolation circuit is connected with one end of the MCU master chip.

[0037] Optionally, the adaptive push-pull matrix comprises a multiplexing switch, one end of the multiplexing switch is connected with the other end of the FPGA chip, and one end of the multiplexing switch is connected with one end of the isolation circuit, and the multiplexing switch comprises a first switch, a second switch and a third switch.

[0038] Optionally, the adaptive push-pull matrix circuit further comprises:

[0039] A power supply;

[0040] A first resistor, one end of the first resistor is connected with the positive electrode of the power supply;

[0041] A first triode, the base of the first triode is connected with the first switch of the multiplexing switch, the collector of the first triode is connected with the other end of the first resistor, and the emitter of the first triode is connected with the gate of the silicon carbide MOS module.

[0042] A second resistor, one end of the second resistor is connected with the positive electrode of the power supply;

[0043] A second triode, the base of the second triode is connected with the second switch of the multiplexing switch, the collector of the second triode is connected with the other end of the second resistor, and the emitter of the second triode is connected with the gate of the silicon carbide MOS module.

[0044] A third resistor, one end of the third resistor is connected with the positive electrode of the power supply;

[0045] A third triode, the base of the third triode is connected with the third switch of the multiplexing switch, the collector of the third triode is connected with the other end of the third resistor, and the emitter of the third triode is connected with the gate of the silicon carbide MOS module.

[0046] a fourth resistor, one end of the fourth resistor being connected with the negative pole of the power supply;

[0047] a fourth triode, a base of the fourth triode being connected with the first switch of the multi-way selection switch, a collector of the fourth triode being connected with the other end of the fourth resistor, and an emitter of the fourth triode being connected with the gate of the silicon carbide MOS module;

[0048] a fifth resistor, one end of the fifth resistor being connected with the negative pole of the power supply;

[0049] a fifth triode, a base of the fifth triode being connected with the second switch of the multi-way selection switch, a collector of the fifth triode being connected with the other end of the fifth resistor, and an emitter of the fifth triode being connected with the gate of the silicon carbide MOS module;

[0050] a sixth resistor, one end of the sixth resistor being connected with the negative pole of the power supply;

[0051] a sixth triode, a base of the sixth triode being connected with the third switch of the multi-way selection switch, a collector of the sixth triode being connected with the other end of the sixth resistor, and an emitter of the sixth triode being connected with the gate of the silicon carbide MOS module.

[0052] Optionally, the first triode, the second triode and the third triode are NPN type triodes, and the fourth triode, the fifth triode and the sixth triode are PNP type triodes.

[0053] Through the technical scheme, the utility model provides a kind of circuit and system based on closed loop control, and the real-time bus voltage value is collected by bus voltage acquisition circuit, and one end of bus voltage acquisition circuit is used to be connected with the drain of silicon carbide MOS module, one end of FPGA chip is connected with the other end of bus voltage acquisition circuit, one end of self-adapting push-pull matrix circuit is connected with the other end of FPGA chip, one end is connected with the gate of silicon carbide MOS module, and self-adapting push-pull matrix circuit is used to match the resistance value of real-time bus voltage value according to the real-time bus voltage value collected, to control silicon carbide MOS module to be in optimum operating state.The circuit and system can self-adaptingly adjust the resistance value of gate drive resistor circuit to provide more adaptive gate drive voltage and current under the scene of various bus voltage waves by closed loop control, and by controlling multi-way selection switch, it can be applied to multiple working scenes, and by being connected with FPGA chip, logical judgment of voltage level is directly carried out in hardware level, corresponding control signal is output, delay is low and can be customized. BRIEF DESCRIPTION OF DRAWINGS

[0054] The accompanying drawings, which are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the embodiments. In the drawings:

[0055] Figure 1 is a circuit schematic diagram based on closed-loop control according to an embodiment of the present application;

[0056] Figure 2 is a self-adaptive push-pull matrix circuit schematic diagram according to an embodiment of the present application.

[0057] Legend of reference signs

[0058] V+, power supply R1, first resistor

[0059] R2, second resistor R3, third resistor

[0060] R4, fourth resistor R5, fifth resistor

[0061] R, sixth resistor V1, first triode

[0062] V2, second triode V3, third triode

[0063] V4, fourth triode V5, fifth triode

[0064] V6, sixth triode S1, first switch

[0065] S2, second switch S3, third switch DETAILED DESCRIPTION

[0066] The specific embodiments of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the embodiments of the present application, and are not intended to limit the embodiments of the present application.

[0067] In the embodiments of the present application, unless otherwise stated, the positional words such as "upper", "lower", "top", "bottom" used are generally directed to the directions shown in the drawings or the positional relationships of the components with respect to each other in the vertical, perpendicular or gravitational direction.

[0068] In addition, if the description of "first", "second" and the like is involved in the embodiments of the present application, the description of "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can be explicitly or implicitly included at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of the ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the present application.

[0069] As shown in Figure 1 , it is a circuit schematic diagram based on closed-loop control according to an embodiment of the present application. As shown in Figure 2 , it is a self-adaptive push-pull matrix circuit schematic diagram according to an embodiment of the present application. In the Figure 1 , the circuit based on closed-loop control includes bus voltage acquisition circuit, FPGA chip and self-adaptive push-pull matrix circuit. Specifically, one end of the bus voltage acquisition circuit is used to connect with the drain of the silicon carbide MOS module, and is used to acquire the real-time bus voltage value, one end of the FPGA chip is connected with the other end of the bus voltage acquisition circuit, one end of the self-adaptive push-pull matrix circuit is connected with the other end of the FPGA chip, and one end is connected with the gate of the silicon carbide MOS module. The self-adaptive push-pull matrix circuit is used to match the resistance value of the real-time bus voltage value according to the acquired real-time bus voltage value, so as to control the silicon carbide MOS module to be in the best running state. In the embodiment, the circuit further includes MCU master chip and isolation circuit, the MCU master chip is used to output continuous and stable PWM wave to drive the silicon carbide MOS module, one end of the isolation circuit is connected with one end of the self-adaptive push-pull matrix circuit, and the other end of the isolation circuit is connected with one end of the MCU master chip. The real-time bus voltage value is acquired by the bus voltage acquisition circuit and transmitted to the FPGA chip, the voltage level is judged, and the corresponding control signal is output to the self-adaptive push-pull matrix circuit according to the result of logical judgment. At the same time, the MCU master chip outputs continuous and stable PWM wave to drive the silicon carbide MOS tube, and the self-adaptive push-pull matrix circuit adaptively matches the resistance value according to the real-time detected electric vehicle battery bus voltage value, so as to ensure that the silicon carbide MOS module can also be in the best running state in the case that the voltage fluctuation caused by the long-time working condition of the electric vehicle battery.

[0070] As shown in Figure 2As shown, in this embodiment, the adaptive push-pull matrix circuit includes a multi-selection switch, one end of which is connected to the other end of the FPGA chip, and one end of which is connected to one end of the isolation circuit. The multi-selection switch includes a first switch S1, a second switch S2, and a third switch S3. It also includes a power supply V+, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first transistor V1, a second transistor V2, a third transistor V3, a fourth transistor V4, a fifth transistor V5, and a sixth transistor V6. Specifically, one end of the first resistor R1 is connected to the positive electrode of the power supply V+, the base of the first transistor V1 is connected to the first switch S1 of the multi-selection switch, the collector of the first transistor V1 is connected to the other end of the first resistor R1, the emitter of the first transistor V1 is connected to the gate of the silicon carbide MOS module, one end of the second resistor R2 is connected to the positive electrode of the power supply V+, the base of the second transistor V2 is connected to the second switch S2 of the multi-selection switch, the collector of the second transistor V2 is connected to the other end of the second resistor R2, the emitter of the second transistor V2 is connected to the gate of the silicon carbide MOS module, one end of the third resistor R3 is connected to the positive electrode of the power supply V+, the base of the third transistor V3 is connected to the third switch S3 of the multi-selection switch, the collector of the third transistor V3 is connected to the other end of the third resistor R3, the emitter of the third transistor V3 is connected to the gate of the silicon carbide MOS module, one end of the fourth resistor R4 is connected to the negative electrode of the power supply V+, the base of the fourth transistor V4 is connected to the first switch S1 of the multi-selection switch, the collector of the fourth transistor V4 is connected to the other end of the fourth resistor R4, the emitter of the fourth transistor V4 is connected to the gate of the silicon carbide MOS module, one end of the fifth resistor R5 is connected to the negative electrode of the power supply V+, the base of the fifth transistor V5 is connected to the second switch S2 of the multi-selection switch, the collector of the fifth transistor V5 is connected to the other end of the fifth resistor R5, the emitter of the fifth transistor V5 is connected to the gate of the silicon carbide MOS module, one end of the sixth resistor R6 is connected to the negative electrode of the power supply V+, the base of the sixth transistor V6 is connected to the third switch S3 of the multi-selection switch, the collector of the sixth transistor V6 is connected to the other end of the sixth resistor R6, and the emitter of the sixth transistor V6 is connected to the gate of the silicon carbide MOS module.

[0071] In this embodiment, the first transistor V1, the second transistor V2, and the third transistor V3 are NPN type transistors, and the fourth transistor V4, the fifth transistor V5, and the sixth transistor V6 are PNP type transistors.

[0072] The current market widely used electric drive 800V working voltage platform is divided into multiple voltage levels: ①A; ②B; ③C; ④D; ⑤E; ⑥F; ⑦G. The real-time bus voltage value measured by the bus voltage acquisition circuit is transmitted to the FPGA chip, and the voltage level interval where the measured bus voltage value is located is judged by the FPGA chip. According to different voltage levels, the state of the multi-way selection switch is controlled to adjust the adaptive push-pull matrix circuit. Therefore, the mode of PWM control triode is as shown in the following table:

[0073] Table 1

[0074] Voltage level Control switch Working triode A S1 V1, V4 B S2 V2, V5 C S3 V3, V6 D S1 & S2 V1, V2, V4, V5 E S1 & S3 V1, V3, V4, V6 F S2 & S3 V2, V3, V5, V6 G S1 & S2 & S3 V1, V2, V3, V4, V5, V6

[0075] On the other hand, the utility model also provides a kind of adaptive push-pull matrix system based on closed-loop control, and the system includes silicon carbide MOS module, bus voltage acquisition circuit, FPGA chip and adaptive push-pull matrix circuit. It can be specifically as shown in Figure 1 And Figure 2 , in the Figure 1 , the circuit based on closed-loop control includes bus voltage acquisition circuit, FPGA chip and adaptive push-pull matrix circuit. Specifically, one end of bus voltage acquisition circuit is used to be connected with the drain of silicon carbide MOS module, and is used to acquire real-time bus voltage value, one end of FPGA chip is connected with the other end of bus voltage acquisition circuit, one end of adaptive push-pull matrix circuit is connected with the other end of FPGA chip, one end is connected with the gate of silicon carbide MOS module, adaptive push-pull matrix circuit is used to match the resistance value of real-time bus voltage value according to the real-time bus voltage value acquired, to control silicon carbide MOS module to be in optimal operating state. In the embodiment, the circuit further includes MCU master chip and isolation circuit, MCU master chip is used to output continuous stable PWM wave to drive silicon carbide MOS module, one end of isolation circuit is connected with one end of adaptive push-pull matrix circuit, the other end of isolation circuit is connected with one end of MCU master chip. Real-time bus voltage value is acquired by bus voltage acquisition circuit and is transmitted to FPGA chip, and voltage level is judged, according to the result of logical judgment, corresponding control signal is output and is transmitted to adaptive push-pull matrix circuit. At the same time, MCU master chip outputs continuous stable PWM wave to drive silicon carbide MOS tube, and adaptive push-pull matrix circuit is adapted to match resistance value according to the electric vehicle battery bus voltage value obtained by real-time detection, to ensure that silicon carbide MOS module can also be in optimal operating state in the case that voltage fluctuation can be caused by long time working condition of electric vehicle battery.

[0076] As Figure 2As shown, in this embodiment, the adaptive push-pull matrix circuit includes a multi-selection switch, one end of the multi-selection switch is connected with the other end of the FPGA chip, one end of the multi-selection switch is connected with one end of the isolation circuit, the multi-selection switch includes a first switch S1, a second switch S2 and a third switch S3. It also includes a power supply V+, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first transistor V1, a second transistor V2, a third transistor V3, a fourth transistor V4, a fifth transistor V5 and a sixth transistor V6. Specifically, one end of the first resistor R1 is connected with the positive electrode of the power supply V+, the base of the first transistor V1 is connected with the first switch S1 of the multi-selection switch, the collector of the first transistor V1 is connected with the other end of the first resistor R1, the emitter of the first transistor V1 is connected with the gate of the silicon carbide MOS module, one end of the second resistor R2 is connected with the positive electrode of the power supply V+, the base of the second transistor V2 is connected with the second switch S2 of the multi-selection switch, the collector of the second transistor V2 is connected with the other end of the second resistor R2, the emitter of the second transistor V2 is connected with the gate of the silicon carbide MOS module, one end of the third resistor R3 is connected with the positive electrode of the power supply V+, the base of the third transistor V3 is connected with the third switch S3 of the multi-selection switch, the collector of the third transistor V3 is connected with the other end of the third resistor R3, the emitter of the third transistor V3 is connected with the gate of the silicon carbide MOS module, one end of the fourth resistor R4 is connected with the negative electrode of the power supply V+, the base of the fourth transistor V4 is connected with the first switch S1 of the multi-selection switch, the collector of the fourth transistor V4 is connected with the other end of the fourth resistor R4, the emitter of the fourth transistor V4 is connected with the gate of the silicon carbide MOS module, one end of the fifth resistor R5 is connected with the negative electrode of the power supply V+, the base of the fifth transistor V5 is connected with the second switch S2 of the multi-selection switch, the collector of the fifth transistor V5 is connected with the other end of the fifth resistor R5, the emitter of the fifth transistor V5 is connected with the gate of the silicon carbide MOS module, one end of the sixth resistor R6 is connected with the negative electrode of the power supply V+, the base of the sixth transistor V6 is connected with the third switch S3 of the multi-selection switch, the collector of the sixth transistor V6 is connected with the other end of the sixth resistor R6, the emitter of the sixth transistor V6 is connected with the gate of the silicon carbide MOS module.

[0077] In this embodiment, the first transistor V1, the second transistor V2 and the third transistor V3 are NPN type transistors, and the fourth transistor V4, the fifth transistor V5 and the sixth transistor V6 are PNP type transistors.

[0078] Through the technical scheme, the utility model provides a kind of circuit and system based on closed loop control, and the real-time bus voltage value is collected by bus voltage acquisition circuit, and one end of bus voltage acquisition circuit is used to connect with the drain of silicon carbide MOS module, one end of FPGA chip is connected with the other end of bus voltage acquisition circuit, one end of adaptive push-pull matrix circuit is connected with the other end of FPGA chip, one end is connected with the gate of silicon carbide MOS module, adaptive push-pull matrix circuit is used to match the resistance of real-time bus voltage value according to the real-time bus voltage value of collection, to control silicon carbide MOS module to be in optimum operating state.The circuit and system can be in the scene of various bus voltage waves by closed loop control, and the resistance of gate drive resistance circuit is adaptively adjusted to provide more adaptive gate drive voltage and current, and by controlling multiplexing switch, it can be applied to a variety of working scenes, and by being connected with FPGA chip, logic judgment of voltage grade is directly carried out in hardware level, and corresponding control signal is output, delay is low and can be customized.

[0079] The preferred embodiments of the utility model are described in detail above in combination with the drawings, but the utility model is not limited to this. Within the technical concept range of the utility model, the technical scheme of the utility model can be subjected to various simple modifications. Various specific technical features are combined in any suitable manner, and in order to avoid unnecessary repetition, the utility model will not be described again for various possible combination manners. However, these simple modifications and combinations should also be regarded as the disclosed content of the utility model, and all belong to the protection range of the utility model.

Claims

1. A circuit based on closed loop control, characterized by The circuit comprises: A bus voltage acquisition circuit, one end of the bus voltage acquisition circuit is used for being connected with a drain of a silicon carbide MOS module, and the bus voltage acquisition circuit is used for acquiring a real-time bus voltage value; An FPGA chip, one end of the FPGA chip is connected with the other end of the bus voltage acquisition circuit; An adaptive push-pull matrix circuit, one end of the adaptive push-pull matrix circuit is connected with the other end of the FPGA chip, and one end of the adaptive push-pull matrix circuit is connected with a gate of the silicon carbide MOS module, and the adaptive push-pull matrix circuit is used for matching a resistance value of the real-time bus voltage value according to the acquired real-time bus voltage value, so as to control the silicon carbide MOS module to be in an optimal operating state.

2. The circuit of claim 1, wherein, The circuit further comprises: An MCU master control chip, which is used for outputting a continuous and stable PWM wave to drive the silicon carbide MOS module; An isolation circuit, one end of the isolation circuit is connected with one end of the adaptive push-pull matrix circuit, and the other end of the isolation circuit is connected with one end of the MCU master control chip.

3. The circuit of claim 2, wherein, The adaptive push-pull matrix circuit comprises a multipath selection switch, one end of the multipath selection switch is connected with the other end of the FPGA chip, and one end of the multipath selection switch is connected with one end of the isolation circuit, and the multipath selection switch comprises a first switch, a second switch and a third switch.

4. The circuit of claim 3, wherein, The adaptive push-pull matrix circuit further comprises: A power supply; A first resistor, one end of the first resistor is connected with a positive electrode of the power supply; A first triode, a base of the first triode is connected with the first switch of the multipath selection switch, a collector of the first triode is connected with the other end of the first resistor, and an emitter of the first triode is connected with the gate of the silicon carbide MOS module; A second resistor, one end of the second resistor is connected with the positive electrode of the power supply; A second triode, a base of the second triode is connected with the second switch of the multipath selection switch, a collector of the second triode is connected with the other end of the second resistor, and an emitter of the second triode is connected with the gate of the silicon carbide MOS module; A third resistor, one end of the third resistor is connected with the positive electrode of the power supply; A third triode, a base of the third triode is connected with the third switch of the multipath selection switch, a collector of the third triode is connected with the other end of the third resistor, and an emitter of the third triode is connected with the gate of the silicon carbide MOS module; A fourth resistor, one end of the fourth resistor is connected with a negative electrode of the power supply; A fourth triode, a base of the fourth triode is connected with the first switch of the multipath selection switch, a collector of the fourth triode is connected with the other end of the fourth resistor, and an emitter of the fourth triode is connected with the gate of the silicon carbide MOS module; A fifth resistor, one end of the fifth resistor is connected with the negative electrode of the power supply; A fifth triode, a base of the fifth triode is connected with the second switch of the multipath selection switch, a collector of the fifth triode is connected with the other end of the fifth resistor, and an emitter of the fifth triode is connected with the gate of the silicon carbide MOS module; A sixth resistor, one end of the sixth resistor is connected with the negative pole of the power supply; A sixth transistor, the base of the sixth transistor is connected with the third switch of the multi-way selection switch, the collector of the sixth transistor is connected with the other end of the sixth resistor, and the emitter of the sixth transistor is connected with the gate of the silicon carbide MOS module.

5. The circuit of claim 4, wherein, The first transistor, the second transistor and the third transistor are NPN type transistors, and the fourth transistor, the fifth transistor and the sixth transistor are PNP type transistors.

6. A system based on closed loop control, characterized by The system comprises: A silicon carbide MOS module, the source of the silicon carbide MOS module is grounded; A bus voltage acquisition circuit, one end of the bus voltage acquisition circuit is used for being connected with the drain of the silicon carbide MOS module, and the bus voltage acquisition circuit is used for acquiring a real-time bus voltage value; An FPGA chip, one end of the FPGA chip is connected with the other end of the bus voltage acquisition circuit; An adaptive push-pull matrix circuit, one end of the adaptive push-pull matrix circuit is connected with the other end of the FPGA chip, and one end of the adaptive push-pull matrix circuit is connected with the gate of the silicon carbide MOS module, and the adaptive push-pull matrix circuit is used for matching the resistance value of the real-time bus voltage value according to the acquired real-time bus voltage value, so that the silicon carbide MOS module is in the best running state.

7. The system of claim 6, wherein, The system further comprises: An MCU master control chip, used for outputting a continuous and stable PWM wave to drive the silicon carbide MOS module; An isolation circuit, one end of the isolation circuit is connected with one end of the adaptive push-pull matrix circuit, and the other end of the isolation circuit is connected with one end of the MCU master control chip.

8. The system of claim 7, wherein, The adaptive push-pull matrix circuit comprises a multi-way selection switch, one end of the multi-way selection switch is connected with the other end of the FPGA chip, and one end of the multi-way selection switch is connected with one end of the isolation circuit, and the multi-way selection switch comprises a first switch, a second switch and a third switch.

9. The system of claim 8, wherein, The adaptive push-pull matrix circuit further comprises: A power supply; A first resistor, one end of the first resistor is connected with the positive pole of the power supply; A first transistor, the base of the first transistor is connected with the first switch of the multi-way selection switch, the collector of the first transistor is connected with the other end of the first resistor, and the emitter of the first transistor is connected with the gate of the silicon carbide MOS module; A second resistor, one end of the second resistor is connected with the positive pole of the power supply; A second transistor, the base of the second transistor is connected with the second switch of the multi-way selection switch, the collector of the second transistor is connected with the other end of the second resistor, and the emitter of the second transistor is connected with the gate of the silicon carbide MOS module; A third resistor, one end of the third resistor is connected with the positive pole of the power supply; A third transistor, the base of the third transistor is connected with the third switch of the multi-way selection switch, the collector of the third transistor is connected with the other end of the third resistor, and the emitter of the third transistor is connected with the gate of the silicon carbide MOS module; A fourth resistor, one end of the fourth resistor is connected with the negative pole of the power supply; A fourth triode, a base of the fourth triode is connected with the first switch of the multi-select switch, a collector of the fourth triode is connected with the other end of the fourth resistor, and an emitter of the fourth triode is connected with the gate of the silicon carbide MOS module; A fifth resistor, one end of the fifth resistor is connected with the negative pole of the power supply; A fifth triode, a base of the fifth triode is connected with the second switch of the multi-select switch, a collector of the fifth triode is connected with the other end of the fifth resistor, and an emitter of the fifth triode is connected with the gate of the silicon carbide MOS module; A sixth resistor, one end of the sixth resistor is connected with the negative pole of the power supply; A sixth triode, a base of the sixth triode is connected with the third switch of the multi-select switch, a collector of the sixth triode is connected with the other end of the sixth resistor, and an emitter of the sixth triode is connected with the gate of the silicon carbide MOS module.

10. The system of claim 9, wherein, The first triode, the second triode and the third triode are NPN type triodes, and the fourth triode, the fifth triode and the sixth triode are PNP type triodes.

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