Diode and electronic equipment
By employing a slanted groove structure and partitioned anode design in GaN diodes, the problem of rapid capacitance changes is solved, achieving stable control and manageability of the capacitance, thereby improving the yield and ease of manufacturing of the diodes.
Patent Information
- Application Number
- CN202423323906.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing GaN diodes cannot be effectively used as varactor diodes because the capacitance of the vertical groove changes rapidly, resulting in poor capacitance controllability.
The anode region is divided into a first region and a second region. The first region is located inside the groove, and the second region is located outside the groove and is attached to the cap layer. Together with the cap layer, they form a continuous and smooth side surface, which modulates the capacitance change and reduces the phenomenon of sudden capacitance change.
This achieves stable control of the capacitor, resulting in smoother capacitor changes, enhanced capacitor controllability, and improved diode yield and manufacturing feasibility.
Smart Images
Figure CN223694217U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of microelectronics, in particular to a diode and an electronic device. BACKGROUND
[0002] As a wide band gap semiconductor material, GaN material has great electrical performance advantages. The AlGaN / GaN heterojunction structure can induce a high concentration of two-dimensional electron gas near the interface on the GaN side due to its strong spontaneous polarization and piezoelectric polarization effect. Since the electrons are confined in the potential well and the impurity doping in this region is very small, the ionized impurity scattering and alloy disorder scattering are small, and the two-dimensional electron gas has extremely high mobility and electron saturation rate. Moreover, due to the wide band gap property of GaN material, the critical breakdown field strength is extremely large, which is suitable for making high-power voltage diodes.
[0003] In order to reduce the capacitance, the existing GaN diode introduces a vertical groove below the anode, and the sidewall and the bottom surface of the vertical groove are perpendicular or close to perpendicular. However, the capacitance of the vertical groove changes rapidly and often drops sharply when the two-dimensional electron gas is depleted, resulting in poor controllability of the capacitance and making it impossible to be used as a varactor diode. CONTENT OF THE UTILITY MODEL
[0004] The present application aims at the deficiencies in the prior art, and provides a diode and an electronic device which can control the capacitance.
[0005] To achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows:
[0006] In a first aspect, the present application provides a diode, comprising: a substrate, a first semiconductor layer, a second semiconductor layer and a cap layer which are sequentially stacked on the substrate, a two-dimensional electron gas is formed at the interface of the first semiconductor layer and the second semiconductor layer, a cathode is further arranged on the second semiconductor layer, and the cap layer wraps the side surface of the cathode; a first groove is arranged on the surface of the cap layer away from the second semiconductor layer, the first groove extends into the first semiconductor layer, and the included angle between the side surface and the bottom surface of the first groove is an obtuse angle; the diode further comprises an anode, the anode comprises a first anode region and a second anode region connected with the first anode region, the first anode region is located in the first groove, and the second anode region is located outside the first groove and is attached to the cap layer.
[0007] Optionally, the first semiconductor layer comprises a buffer layer and a channel layer, one side of the buffer layer is attached to the substrate, and the other side is attached to the channel layer, and the two-dimensional electron gas is formed at the interface of the channel layer and the second semiconductor layer.
[0008] Optionally, the second semiconductor layer comprises a barrier layer, the barrier layer is attached to the channel layer, the barrier layer is used to generate the two-dimensional electron gas, and the two-dimensional electron gas exists at the interface of the channel layer and the barrier layer.
[0009] Optionally, the length of the second anode region is 0.5 μm-50 μm.
[0010] Optionally, the cap layer is a GaN cap layer, and the thickness of the cap layer is 50 nm-500 nm.
[0011] Optionally, the included angle between the side surface and the bottom surface of the first recess is 110°-150°.
[0012] Optionally, the bottom surface of the first recess is located 5 nm-25 nm below the interface between the first semiconductor layer and the second semiconductor layer.
[0013] Optionally, the edge of the surface of the cap layer away from the second semiconductor layer is provided with a second recess, and the second recess extends to the first semiconductor layer.
[0014] Optionally, the buffer layer is a GaN buffer layer or an AlGaN buffer layer or an AlN buffer layer, the channel layer is an unintentionally doped GaN channel layer, and the barrier layer is an AlGaN barrier layer.
[0015] In a second aspect, the embodiment of the present application provides an electronic device comprising the diode according to any one of the above.
[0016] The present application has the following advantages:
[0017] The present application provides a diode, comprising: a substrate, a first semiconductor layer, a second semiconductor layer and a cap layer which are sequentially stacked on the substrate, a two-dimensional electron gas is formed at the interface between the first semiconductor layer and the second semiconductor layer, a cathode is further arranged on the second semiconductor layer, and the cap layer wraps the side surface of the cathode; a first recess is arranged on the surface of the cap layer away from the second semiconductor layer, the first recess extends to the first semiconductor layer, and the included angle between the side surface and the bottom surface of the first recess is an obtuse angle; the diode further comprises an anode, the anode comprises a first anode region and a second anode region connected with the first anode region, the first anode region is located in the first recess, and the second anode region is located outside the first recess and is attached to the cap layer. The diode changes the vertical recess in the prior art into an inclined recess (the first recess), and the main source of the device capacitance is the flat plate capacitance generated by the overlap between the second anode region of the anode and the two-dimensional electron gas. When a negative voltage is applied to the first anode region, the two-dimensional electron gas is gradually depleted as the negative voltage gradually increases, which is equivalent to that the area of the field plate capacitance is gradually reduced, so that the capacitance is stably controlled. The cap layer is beneficial to forming a continuous and smooth side surface when the first recess is manufactured, and can increase the distance between the second anode region and the two-dimensional electron gas, weaken the capacitance mutation phenomenon caused by the rapid depletion of the two-dimensional electron gas, and make the capacitance change more gently. The second anode region and the cap layer jointly act to modulate the change range of the capacitance. The diode has a simple structure, high feasibility, is easy to manufacture, and has a high yield. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.
[0019] Figure 1 The structure schematic diagram of the diode provided for the embodiments of the present application;
[0020] Figure 2 The manufacturing process schematic diagram of the diode provided for the embodiments of the present application;
[0021] Figure 3 The manufacturing process schematic diagram of the diode provided for the embodiments of the present application;
[0022] Figure 4 The manufacturing process schematic diagram of the diode provided for the embodiments of the present application;
[0023] Figure 5 The manufacturing process schematic diagram of the diode provided for the embodiments of the present application.
[0024] Figure: 100-diode; 110-substrate; 120-first semiconductor layer; 121-buffer layer; 122-channel layer; 130-second semiconductor layer; 131-potential barrier layer; 140-cap layer; 150-two-dimensional electron gas; 160-cathode; 170-first recess; 180-anode; 181-first anode area; 182-second anode area; 190-second recess; θ-angle between the side surface and the bottom surface of the first recess; L-length of the second anode area. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.
[0026] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. It should be noted that the various features in the embodiments of the present application can be combined with each other without conflict, and the combined embodiments are still within the protection scope of the present application.
[0027] It should be noted that like reference numerals and characters refer to like elements throughout the following description with like reference numerals and characters referring to like elements throughout the following description and across different drawings indicated to be reference numerals and characters in the drawings and, as a result, once an element is defined in one drawing that draws throughout the following description, it is not necessary to further define and explain it in subsequent drawings.
[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly placed when the product of the application is used, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third", and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0029] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "set", "mount", "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0030] An aspect of an embodiment of the present application, please refer to Figure 1 , a diode 100 is provided, comprising: a substrate 110, a first semiconductor layer 120, a second semiconductor layer 130 and a cap layer 140 which are sequentially stacked on the substrate 110, a two-dimensional electron gas 150 is formed at the interface of the first semiconductor layer 120 and the second semiconductor layer 130, a cathode 160 is further provided on the side of the second semiconductor layer 130 away from the first semiconductor layer 120, and the cap layer 140 wraps the side surface of the cathode 160. The surface of the cap layer 140 away from the second semiconductor layer 130 is provided with a first recess 170, the first recess 170 extends into the first semiconductor layer 120, and the included angle θ between the side surface and the bottom surface of the first recess is an obtuse angle. The diode 100 further comprises an anode 180, the anode 180 comprises a first anode region 181 and a second anode region 182 connected with the first anode region 181, the first anode region 181 is located in the first recess 170, and the second anode region 182 is located outside the first recess 170 and is attached to the cap layer 140.
[0031] It should be noted that the cathode 160 has two opposite surfaces and a side surface connecting the two surfaces, the cathode 160 is embedded in the inside of the cap layer 140, the side surface is wrapped by the cap layer 140, and the two opposite surfaces are exposed to the cap layer 140 respectively. The cathode 160 forms an ohmic contact with the second semiconductor layer 130, and the cathode 160 is mainly composed of a cathode metal, which can be a single-layer metal or a multi-layer stacked metal. The cathode 160 can be a ring, an interdigital structure or an island topology. Preferably, the cathode 160 is a ring.
[0032] The first recess 170 is formed on the surface of the cap layer 140 away from the second semiconductor layer 130, and the opening of the first recess 170 is located on the surface of the cap layer 140 away from the second semiconductor layer 130, and the bottom is located in the first semiconductor layer 120. The side surface of the first recess 170 is inclined, so as to present a shape of wide at the top and narrow at the bottom. The bottom of the first recess 170 can be close to the area where the two-dimensional electron gas 150 is located, or can be located in the area where the two-dimensional electron gas 150 is located. Optionally, the bottom of the first recess 170 is located 5-25 nm below the interface between the first semiconductor layer 120 and the second semiconductor layer 130. In this way, the bottom of the first recess 170 can be located near the two-dimensional electron gas 150.
[0033] The included angle θ between the side surface and the bottom of the first recess is an obtuse angle. Optionally, the included angle θ between the side surface and the bottom of the first recess is 110°-150°. In actual production, the corner between the side surface and the bottom of the first recess 170 is not necessarily a standard geometric corner, but can also be a round corner with a certain arc.
[0034] The anode 180 includes a first anode region 181 and a second anode region 182, the first anode region 181 is located in the first recess 170 and covers the side surface and the bottom of the first recess 170. The edge of the first anode region 181 is connected to the second anode region 182, and the second anode region 182 is laid on the surface of the cap layer 140 away from the second semiconductor layer 130. The anode 180 forms a Schottky contact with the second semiconductor layer 130, and the anode 180 is mainly composed of an anode metal, which can be a single-layer metal or a multi-layer stacked metal. For example, the anode 180 includes a first metal layer and a second metal layer disposed on the first metal layer, the first metal layer is a W metal layer, a Mo metal layer or a Ni metal layer with a thickness of 30-200 nm, and the second metal layer is an Au metal layer with a thickness of 0-200 nm.
[0035] The diode 100 changes the vertical groove in the prior art into an inclined groove (the first groove 170), and the main source of the device capacitance is the flat plate capacitance generated by the overlapping of the second anode region 182 of the anode 180 and the two-dimensional electron gas 150, and the first anode region 181 can form a gradual depletion to the two-dimensional electron gas 150 as the negative voltage gradually increases, which is equivalent to the gradual decrease of the field plate capacitance opposite area, thereby realizing the stable control of the capacitance. The cap layer 140 is beneficial to form a continuous and smooth side surface when the first groove 170 is made, and can increase the distance between the second anode region 182 and the two-dimensional electron gas 150, weaken the capacitance mutation phenomenon caused by the rapid depletion of the two-dimensional electron gas 150, and make the capacitance change more gentle. The second anode region 182 and the cap layer 140 jointly act to modulate the change range of the capacitance. The diode 100 has simple structure, strong feasibility, is easy to manufacture, and has high yield.
[0036] Optionally, the length L of the second anode region is 0.5-50 μm.
[0037] The second anode region 182 with a length of 0.5-50 μm increases the overlapping area of the second anode region 182 and the two-dimensional electron gas 150 below, can increase the maximum value of the capacitance, thereby increasing the variable range of the capacitance, and can also strengthen the control ability of the capacitance.
[0038] Optionally, the cap layer 140 is a GaN cap layer, and the thickness of the cap layer 140 is 50-500 nm.
[0039] The GaN cap layer with a thickness of 50-500 nm can increase the distance between the second anode region 182 and the two-dimensional electron gas 150, weaken the control of the anode 180 to the two-dimensional electron gas 150, reduce the mutation phenomenon of the capacitance, and regulate the change range of the capacitance.
[0040] Optionally, the first semiconductor layer 120 includes a buffer layer 121 and a channel layer 122, one side of the buffer layer 121 is attached to the substrate 110, and the other side is attached to the channel layer 122, and the two-dimensional electron gas 150 is formed at the interface between the channel layer 122 and the second semiconductor layer 130.
[0041] The channel layer 122 is the main channel for electron transmission. Since there is a large lattice mismatch between the channel layer 122 and the substrate 110, in order to avoid generating a large number of defects and dislocations in the channel layer 122, which affects the leakage and breakdown characteristics of the diode 100, the buffer layer 121 is introduced between the channel layer 122 and the substrate 110, which plays a transition role and can reduce defects and dislocations to form a high-quality channel layer 122.
[0042] Optionally, the substrate 110 is a SiN substrate with a thickness of 100-600 μm, a sapphire substrate with a thickness of 100-600 μm, a Si substrate with a thickness of 100-1000 μm, or a GaN substrate with a thickness of 100-600 μm. The buffer layer 121 is a GaN buffer layer with a thickness of 1-6 μm, an AlGaN graded buffer layer with a thickness of 1-6 μm, or an AlN buffer layer with a thickness of 0.2-1 μm. The channel layer 122 is an unintentionally doped GaN channel layer with a thickness of 100-400 nm.
[0043] Optionally, the second semiconductor layer 130 includes a barrier layer 131, the barrier layer 131 is attached to the channel layer 122, and the barrier layer 131 is used to generate a two-dimensional electron gas 150, the two-dimensional electron gas 150 exists at the interface between the channel layer 122 and the barrier layer 131.
[0044] Optionally, the barrier layer 131 is an AlGaN barrier layer.
[0045] Optionally, the edge of the surface of the cap layer 140 away from the second semiconductor layer 130 is provided with a second groove 190, and the second groove 190 extends to the first semiconductor layer 120.
[0046] The second groove 190 is formed at the edge of the surface of the cap layer 140 away from the second semiconductor layer 130, and the groove opening of the second groove 190 is located on the surface of the cap layer 140 away from the second semiconductor layer 130, and the bottom is located in the first semiconductor layer 120. The second groove 190 is used to form device isolation.
[0047] One of the manufacturing steps of the above-mentioned diode 100 is as follows:
[0048] Step 1: Clean the epitaxial wafer, which includes the substrate 110, the buffer layer 121, the channel layer 122, the barrier layer 131, and the cap layer 140.
[0049] Please refer to Figure 2 The epitaxial wafer is first soaked in HF acid solution or HCl acid solution for 30 s, and then sequentially soaked in acetone solution, isopropyl alcohol solution, anhydrous ethanol solution, and deionized water for 5 min each, and then dried with nitrogen.
[0050] Step 2: Make the cathode 160, please refer to Figure 3 .
[0051] (1) On a clean epitaxial wafer, perform glue spreading, glue baking, device cathode area photoetching, and development in sequence, and use an ICP etching machine to etch the cap layer 140 to the surface of the barrier layer 131;
[0052] (2) Use an electron beam evaporation device to deposit a Ti / Al / Ni / Au metal stack on the epitaxial wafer;
[0053] (3) First, immerse the epitaxial wafer on which the Ti / Al / Ni / Au metal stack is deposited in an acetone solution to strip the metal in the photoresist area, then sequentially immerse the epitaxial wafer in acetone, isopropyl alcohol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, dry with nitrogen, and then place it in a rapid annealing furnace for annealing to form the cathode 160.
[0054] Step three: make device isolation (i.e., the second groove 190), please refer to Figure 4 .
[0055] (1) Perform photoresist coating, baking, mesa isolation photolithography, development, and hardening on the epitaxial wafer on which the cathode 160 has been made;
[0056] (2) Use an ICP etching machine to etch the cap layer 140 mesa outer area;
[0057] (3) Sequentially immerse the etched epitaxial wafer in clean acetone, isopropyl alcohol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, and dry with nitrogen to form device isolation.
[0058] Step four: make the first groove 170, please refer to Figure 5 .
[0059] (1) Perform photoresist coating, baking, device anode area photolithography, and development on the epitaxial wafer on which the dielectric has been deposited;
[0060] (2) Use an ICP etching machine to etch at different power and gas ratios, alternating between fast etching and slow etching, to etch to 5-25 nm below the surface of the barrier layer 131 and the channel layer 122, forming a 110°-150° first groove 170, and sequentially immerse it in acetone, isopropyl alcohol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, and dry with nitrogen.
[0061] Step five: make the anode 180, please refer to Figure 1 .
[0062] (1) Perform photoresist coating, baking, device anode area photolithography, and development on the epitaxial wafer on which the first groove 170 has been etched, and use a magnetron sputtering device or an electron beam evaporation device to first deposit a low work function metal Mo or W or Ni with a thickness of 30-200 nm on the epitaxial wafer, and then deposit 0-200 nm of metal Au;
[0063] (2) Immerse the epitaxial wafer after operation (1) in an acetone solution to strip the metal in the photoresist area, forming a second anode area 182 with a length of 0.5-50 μm, and then sequentially immerse the epitaxial wafer in clean acetone, isopropyl alcohol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, and dry with nitrogen.
[0064] Thus far, the fabrication of the diode 100 is completed.
[0065] In another aspect of the embodiments of the present application, an electronic device is provided, which includes the diode 100 according to any one of the above.
[0066] The electronic device includes the same structure and advantages as the diode 100 in the foregoing embodiments. The structure and advantages of the diode 100 have been described in detail in the foregoing embodiments, and will not be described again here.
[0067] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Various modifications and changes can be made by those skilled in the art based on the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A diode, characterized by, The application relates to a diode, comprising: a substrate, a first semiconductor layer, a second semiconductor layer and a cap layer which are sequentially arranged on the substrate, a two-dimensional electron gas is formed at the interface of the first semiconductor layer and the second semiconductor layer, a cathode is further arranged on the second semiconductor layer, and the cap layer wraps the side surface of the cathode; a first groove is arranged on the surface of the cap layer away from the second semiconductor layer, the first groove extends into the first semiconductor layer, and the included angle between the side surface and the bottom surface of the first groove is an obtuse angle; an anode is further arranged, the anode comprises a first anode region and a second anode region connected with the first anode region, the first anode region is arranged in the first groove, and the second anode region is arranged outside the first groove and is attached with the cap layer. The first semiconductor layer comprises a buffer layer and a channel layer, one side of the buffer layer is attached with the substrate, the other side of the buffer layer is attached with the channel layer, and the two-dimensional electron gas is formed at the interface of the channel layer and the second semiconductor layer. The second semiconductor layer comprises a barrier layer, the barrier layer is attached with the channel layer, the barrier layer is used for generating the two-dimensional electron gas, and the two-dimensional electron gas exists at the interface of the channel layer and the barrier layer. The length of the second anode region is 0.5-50 mu m.
2. The diode of claim 1, wherein The cap layer is a GaN cap layer, and the thickness of the cap layer is 50-500 nm.
3. The diode of claim 2, wherein The included angle between the side surface and the bottom surface of the first groove is 110-150 degrees.
4. The diode of claim 1, wherein The bottom surface of the first groove is located below the interface of the first semiconductor layer and the second semiconductor layer by 5-25 nm.
5. The diode of claim 1, wherein An edge of the surface of the cap layer away from the second semiconductor layer is provided with a second groove, and the second groove extends to the first semiconductor layer.
6. The diode of claim 1, wherein The buffer layer is a GaN buffer layer or an AlGaN buffer layer or an AlN buffer layer, the channel layer is an unintentionally doped GaN channel layer, and the barrier layer is an AlGaN barrier layer.
7. The diode of claim 1, wherein The application further relates to a diode comprising any one of the diodes according to claims 1-9.
8. The diode of claim 1, wherein 9. The diode of claim 3, wherein 10. An electronic device, comprising: