Power supply voltage management circuit and electronic detonator detonation controller

Abstract

The utility model discloses a power supply voltage management circuit and an electronic detonator detonation controller, and belongs to the technical field of electronic detonator detonation control. The power supply voltage management circuit comprises a control chip which comprises a high level detection connection pin and a first level output pin; the on-off circuit comprises an on-off control branch circuit, an on-off button is arranged on the on-off control branch circuit, the first end of the on-off button is electrically connected with the power supply, and the second end of the on-off button is electrically connected with the high-level detection connecting pin; the first input end of the first power supply voltage output control circuit is electrically connected with the power supply, the second input end of the first power supply voltage output control circuit is electrically connected with the first level output pin, and the output end of the first power supply voltage output control circuit is used for outputting first power supply voltage. The power supply voltage management circuit provided by the utility model is beneficial to improving the operation stability of the electronic detonator detonation controller.

Description

Technical Field

[0001] This utility model relates to the field of electronic detonator detonation control technology, and in particular to a power supply voltage management circuit and an electronic detonator detonation controller. Background Technology

[0002] Currently, electronic detonators are widely used. In existing detonation systems, the electronic detonator detonator controller interacts with the blasting supervision service center through a data transmission terminal to exchange regulatory data. The electronic detonator detonator controller connects to multiple electronic detonators through a control bus and provides them with working energy and interactive data. After the electronic detonator detonator controller verifies the legitimacy of all parties involved, engineers can use the electronic detonator detonator controller to detect, network, and control the detonation of electronic detonators. This type of blasting operation is widely used in open-pit mines, rock and ore separation, cofferdam demolition, tunnels, urban foundations, mountain modification, and hazard removal demolition blasting scenarios.

[0003] Furthermore, electronic detonator initiation controllers are typically powered by rechargeable batteries. The power supply voltage management circuit is a crucial component of these controllers, playing a vital role in regulating the output voltage and current of the power supply by controlling the switching state of the control switch to ensure stable operation. However, existing electronic detonator initiation controllers suffer from design flaws in their power supply voltage management circuits. The power supply relies on the control switch itself, which is typically designed as a button, leading to potential contact problems and hindering stable operation. Other existing electronic devices powered by rechargeable batteries also exhibit similar issues. Therefore, there is an urgent need for a power supply voltage management circuit that improves the operational stability of electronic detonator initiation controllers. Summary of the Invention

[0004] The purpose of this utility model is to overcome at least one deficiency of the prior art and provide a power supply voltage management circuit that is beneficial to improving the operational stability of the electronic detonator initiation controller; in addition, it also provides an electronic detonator initiation controller.

[0005] The technical solution of this utility model to solve the above-mentioned technical problems is as follows:

[0006] According to one aspect of this application, a power supply voltage management circuit is provided, comprising:

[0007] The control chip includes a high-level detection pin and a first-level output pin.

[0008] A power on / off circuit, comprising a power on / off control branch for controlling power on and power off, and a power on / off control branch having a switch button, the first end of which is electrically connected to the power supply, and the second end of which is electrically connected to the high-level detection pin.

[0009] A first power supply voltage output control circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first power supply voltage output control circuit is electrically connected to the power supply, the second input terminal of the first power supply voltage output control circuit is electrically connected to the first level output pin, and the output terminal of the first power supply voltage output control circuit is used to output a first power supply voltage.

[0010] When the switch button is closed, the control chip detects that the high-level detection connection pin is high. The control chip outputs a first high level through the first level output pin. The first high level output by the first level output pin is input into the first power supply voltage output control circuit, which turns on the first power supply voltage output control circuit and connects the output terminal of the first power supply voltage output control circuit to the power supply and outputs the first power supply voltage.

[0011] The beneficial effects of this utility model are as follows: The power supply voltage management circuit in this embodiment includes a control chip, which comprises a high-level detection connection pin and a first-level output pin. A switch button is placed on the power-on / off control branch. Furthermore, the first input terminal of the first power supply voltage output control circuit is electrically connected to the power supply, and the output terminal of the first power supply voltage output control circuit is used to output the first power supply voltage. Further, when the switch button is closed, the first high-level signal output from the first-level output pin is input into the first power supply voltage output control circuit, causing the output terminal of the first power supply voltage output control circuit to conduct with the power supply and output the first power supply voltage. Thus, the first power supply voltage is directly supplied by the power supply without passing through the switch button. The switch button only controls the opening and closing of the first power supply voltage output control circuit, avoiding any adverse effects on the stability of the power supply. This helps ensure the stability of the first power supply voltage output from the power supply to the output terminal of the first power supply voltage output control circuit. Therefore, placing the power supply voltage management circuit in this embodiment within the electronic detonator initiation controller improves the operational stability of the electronic detonator initiation controller.

[0012] In addition, based on the above technical solution, the present invention can be further improved as follows, and can also have the following additional technical features.

[0013] According to one embodiment of this application, the control chip further includes a second-level output pin and a third-level output pin;

[0014] The power supply voltage management circuit also includes:

[0015] The second power supply voltage output control circuit includes a first switch control branch and a second switch control branch. The input terminal of the first switch control branch is electrically connected to the second level output pin. The second switch control branch includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second switch control branch is electrically connected to the third level output pin. The second input terminal of the second switch control branch is electrically connected to the output terminal of the first switch control branch. The output terminal of the second switch control branch is used to output a control voltage.

[0016] The second power supply voltage output control circuit further includes a third switch control branch, which includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the third switch control branch is electrically connected to the output terminal of the second switch control branch, and the second input terminal of the third switch control branch is electrically connected to the output terminal of the first power supply voltage output control circuit. The output terminal of the third switch control branch is used to output the second power supply voltage.

[0017] Specifically, when the control chip detects that the high-level detection pin is high, the control chip controls the second level output pin to be low, and the output terminal of the first switch control branch outputs a second high level; and when the control chip outputs a third high level through the third level output pin, the second high level input to the output terminal of the first switch control branch and the third high level output by the third level output pin are input into the second switch control branch, and the control voltage output by the second switch control branch is a fourth high level. The fourth high level is input into the third switch control branch, causing the third switch control branch to turn on, and causing the output terminal of the third switch control branch to be connected to the output terminal of the first power supply voltage output control circuit and output the second power supply voltage.

[0018] The control chip in this embodiment also includes a second level output pin and a third level output pin. In addition, this embodiment also includes a second power supply voltage output control circuit, which includes a first switch control branch, a second switch control branch and a third switch control branch. By controlling the third switch control branch to turn on, the output terminal of the third switch control branch is connected to the output terminal of the first power supply voltage output control circuit and outputs the second power supply voltage, thereby providing the second power supply voltage and helping to meet the power supply requirements.

[0019] According to one embodiment of this application, the first switch control branch includes:

[0020] The NAND gate chip includes a first input pin, a second input pin, a power connection pin, a ground connection pin, and a voltage output pin. The first input pin and the second input pin of the NAND gate chip are electrically connected to the second level output pin, the power connection pin of the NAND gate chip is used to input a first power supply voltage, the ground connection pin of the NAND gate chip is grounded, and the voltage output pin of the NAND gate chip is used to output a first logic voltage.

[0021] The second switch control branch includes:

[0022] An AND gate chip includes a first input pin, a second input pin, a power connection pin, a ground connection pin, and a voltage output pin. The first input pin of the AND gate chip is electrically connected to the third-level output pin. The second input pin of the AND gate chip is electrically connected to the output pin of the NAND gate chip. A pull-down resistor is connected to the connection line connecting the first input pin and the third-level output pin of the AND gate chip. One end of the pull-down resistor is electrically connected to the connection line, and the other end of the pull-down resistor is grounded. The power connection pin of the AND gate chip is used to input a second power supply voltage. The ground connection pin of the AND gate chip is grounded. The voltage output pin of the AND gate chip is used to output a second logic voltage.

[0023] The third switch control branch includes:

[0024] The first NMOS transistor has its gate electrically connected to the output pin of the AND gate chip, its source grounded, and its source electrically connected to its gate through a first resistor. The drain of the first NMOS transistor is electrically connected to its source through a first parasitic diode.

[0025] The first PMOS transistor has its gate electrically connected to the drain of the first NMOS transistor, its source electrically connected to the output terminal of the first power supply voltage output control circuit, and its source electrically connected to its gate through a second resistor, and its drain electrically connected to its source through a second parasitic diode.

[0026] When the control chip controls the second level output pin to be low, the first logic voltage output by the voltage output pin of the NAND gate chip is the second high level. When the control chip outputs the third high level through the third level output pin, the second logic voltage output by the voltage output pin of the AND gate chip is the fourth high level. The gate of the first NMOS transistor is high, and the source and drain of the first NMOS transistor are connected. The gate of the first PMOS transistor is high, and the source and drain of the first PMOS transistor are cut off. The output terminal of the third switch control branch is connected to the output terminal of the first power supply voltage output control circuit and outputs the second power supply voltage.

[0027] In this embodiment, the first switch control branch includes a NAND gate chip, the second switch control branch includes an AND gate chip, and the third switch control branch includes a first NMOS transistor and a first PMOS transistor. The NAND gate chip, the AND gate chip, the first NMOS transistor, and the first PMOS transistor all serve as logic switches, which facilitates the control of the output terminal of the third switch control branch and the output terminal of the first power supply voltage output control circuit to be on and off. This facilitates the provision of the second power supply voltage, which is beneficial for meeting power supply requirements and for simplifying the circuit structure.

[0028] According to one embodiment of this application, the power supply voltage management circuit further includes:

[0029] The USB power supply control circuit includes a USB interface, a third resistor, a fourth resistor, and a second PMOS transistor. The USB interface is used to electrically connect to a power supply device via a USB cable. The first end of the third resistor is electrically connected to the USB interface, and the second end of the third resistor is electrically connected to the gate of the second PMOS transistor. The drain of the second PMOS transistor is electrically connected to the gate of the second PMOS transistor via the fourth resistor. The source of the second PMOS transistor is electrically connected to the drain of the second PMOS transistor via a third parasitic diode, and the drain of the second PMOS transistor is grounded. The source of the second PMOS transistor is electrically connected to the second input terminal of the first power supply voltage output control circuit.

[0030] The USB interface is also electrically connected to the output terminal of the first power supply voltage output control circuit via a first diode, wherein the conduction direction of the first diode is from the USB interface to the output terminal of the first power supply voltage output control circuit;

[0031] When the USB cable, which is electrically connected to the power supply device, is plugged into the USB interface and supplies power to the USB interface, the USB power supply control circuit outputs a fifth high level. The fifth high level is input into the first power supply voltage output control circuit, causing the first power supply voltage output control circuit to turn off and disconnecting the output terminal of the first power supply voltage output control circuit from the power supply. The USB cable plugged into the USB interface supplies power to the output terminal of the first power supply voltage output control circuit.

[0032] In this embodiment, a USB power supply control circuit is provided. When the USB cable, which is electrically connected to the power supply device, is plugged into the USB interface and supplies power to the USB interface, the USB power supply control circuit outputs a fifth high level. The fifth high level is input into the first power supply voltage output control circuit, causing the first power supply voltage output control circuit to turn off and disconnecting the output terminal of the first power supply voltage output control circuit from the power supply. The USB cable plugged into the USB interface supplies power to the output terminal of the first power supply voltage output control circuit, thereby realizing power supply and charging through the USB cable, increasing the function of the power supply voltage management circuit, and improving the practicality of the power supply voltage management circuit.

[0033] According to one embodiment of this application, the first power supply voltage output control circuit includes:

[0034] The second NMOS transistor has its gate electrically connected to the high-level detection pin, its source grounded, and its source electrically connected to its gate through a fifth resistor. The drain of the first NMOS transistor is electrically connected to the source of the second NMOS transistor through a fourth parasitic diode.

[0035] The third PMOS transistor has its gate electrically connected to the drain of the second NMOS transistor, its source electrically connected to its gate through a sixth resistor, its drain electrically connected to the power supply, and its drain electrically connected to its source through a fifth parasitic diode.

[0036] The fourth PMOS transistor has its gate electrically connected to the drain of the second NMOS transistor, its source electrically connected to the source of the third PMOS transistor, and its source electrically connected to its gate through the sixth resistor. The drain of the fourth PMOS transistor is electrically connected to the output terminal of the first power supply voltage output control circuit, and its drain is electrically connected to its source through the sixth parasitic diode.

[0037] The first power supply voltage output control circuit in this embodiment includes a second NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The first power supply voltage output control circuit is mainly composed of NMOS transistors and PMOS transistors. NMOS transistors and PMOS transistors are logic switches, which facilitate the control of the first power supply voltage output control circuit to turn on and off by adjusting the level, and improve the stability and reliability of the control of the first power supply voltage output control circuit to turn on and off.

[0038] According to one embodiment of this application, the power supply voltage management circuit further includes:

[0039] USB cable plug-in / plug-out protection circuit, the USB cable plug-in / plug-out protection circuit includes:

[0040] The third NMOS transistor has its gate electrically connected to the high-level detection pin, its source grounded, and its source electrically connected to its gate through a seventh resistor. The drain of the third NMOS transistor is electrically connected to its source through a seventh parasitic diode.

[0041] The fifth PMOS transistor has its gate electrically connected to the drain of the third NMOS transistor, its source electrically connected to the power supply, and its source electrically connected to its gate through an eighth resistor. The drain of the fifth PMOS transistor is electrically connected to its source through an eighth parasitic diode, and its drain is electrically connected to the output terminal of the first power supply voltage output control circuit through a second diode. The conduction direction of the second diode is from the drain of the fifth PMOS transistor to the output terminal of the first power supply voltage output control circuit.

[0042] In this embodiment, a USB cable plug-in / plug-out protection circuit is provided. The USB cable plug-in / plug-out protection circuit includes a third NMOS transistor and a fifth PMOS transistor, which can be easily controlled to turn the USB cable plug-in / plug-out protection circuit on and off by adjusting the level. When the USB cable is unplugged while the device is powered on, the output terminal of the first power supply voltage output control circuit can be powered by the power supply that is electrically connected to the source of the fifth PMOS transistor, ensuring that the output terminal of the first power supply voltage output control circuit can be powered and preventing the module or system powered by the output terminal of the first power supply voltage output control circuit from shutting down. When the USB cable is plugged into the USB interface, the output terminal of the first power supply voltage output control circuit is powered by the USB cable.

[0043] According to one embodiment of this application, the power-on / off circuit further includes:

[0044] The fourth NMOS transistor has its gate electrically connected to the high-level detection pin, its source grounded, and its source electrically connected to its gate through a ninth resistor. The drain of the fourth NMOS transistor is electrically connected to its source through a ninth parasitic diode.

[0045] The sixth PMOS transistor has its gate electrically connected to the drain of the fourth NMOS transistor, its source electrically connected to the power supply, and its source electrically connected to its gate through a tenth resistor. The drain of the sixth PMOS transistor is electrically connected to its source through a tenth parasitic diode. The drain of the sixth PMOS transistor is electrically connected to the second input terminal of the first power supply voltage output control circuit through a series eleventh resistor and a third diode. The conduction direction of the third diode is from the drain of the sixth PMOS transistor towards the second input terminal of the first power supply voltage output control circuit.

[0046] In this embodiment, the power-on / off circuit includes a fourth NMOS transistor and a sixth PMOS transistor. When the switch button is closed, the gate of the fourth NMOS transistor is at a high level, and its source and drain are connected, causing the gate of the sixth PMOS transistor to be at a low level, and its source and drain to be connected. At the initial time when the switch button is pressed, the power supply supplies power to the gate of the second NMOS transistor through the second input terminal of the first power supply voltage output control circuit, causing the gate of the second NMOS transistor to be at a high level, and its source and drain to be connected. This, in turn, causes the gates of the third and fourth PMOS transistors to be at a low level, and their sources and drains to be connected, respectively. This connects the output terminal of the first power supply voltage output control circuit to the power supply and outputs the first power supply voltage. Thus, at the initial time when the switch button is pressed, the output terminal of the first power supply voltage output control circuit is ensured to output the first power supply voltage, shortening the output time of the first power supply voltage.

[0047] According to one embodiment of this application, the power-on / off circuit further includes:

[0048] The anti-shake capacitor has its first terminal electrically connected to the second terminal of the switch button, and its second terminal is grounded.

[0049] In this embodiment, an anti-shake capacitor is provided to reduce switch button bounce by utilizing the characteristics of the anti-shake capacitor itself. Specifically, when the switch button is closed, the anti-shake capacitor charges, and the current changes smoothly to avoid misjudgment due to sudden voltage changes; when the switch button is opened, the capacitor discharges to maintain voltage stability, thereby reducing or preventing switch button bounce.

[0050] According to one embodiment of this application, a twelfth resistor and a fourth diode are connected between the second input terminal of the first power supply voltage output control circuit and the first level output pin. The twelfth resistor and the fourth diode are connected in series. The conduction direction of the fourth diode is from the first level output pin to the second input terminal of the first power supply voltage output control circuit. The second input terminal of the first power supply voltage output control circuit is connected between the third diode and the fourth diode.

[0051] In this embodiment, the twelfth resistor and the fourth diode are connected between the second input terminal and the first level output pin of the first power supply voltage output control circuit, which helps to limit the direction of voltage and current; the second input terminal of the first power supply voltage output control circuit is connected between the third diode and the fourth diode, which helps to ensure that the second input terminal of the first power supply voltage output control circuit has a normal input voltage.

[0052] According to another aspect of this application, an electronic detonator initiation controller is provided, comprising:

[0053] The main body has an installation cavity inside;

[0054] A control module is installed in the mounting cavity, and the control module includes the aforementioned power supply voltage management circuit.

[0055] The control module in the electronic detonator initiation controller of this embodiment includes the aforementioned power supply voltage management circuit, which helps to improve the stability of the electronic detonator initiation controller's operation, and further helps to improve the stability and correctness of the electronic detonator detection, networking, and initiation control through the electronic detonator initiation controller. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a circuit diagram of the power supply voltage management circuit in an embodiment of the present utility model;

[0058] Figure 2 This is a circuit diagram of the second power supply voltage output control circuit in an embodiment of the present invention. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0060] To better understand the above-mentioned objectives, features, and advantages of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0061] Many specific details are set forth in the following description in order to provide a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0062] One aspect of this application provides a power supply voltage management circuit, such as... Figure 1 As shown, it includes:

[0063] Control chip 1 includes a high-level detection connection pin 10 and a first-level output pin 11;

[0064] The power on / off circuit 2 includes a power on / off control branch, which is used to control power on and power off. The power on / off control branch is equipped with a switch button S1. The first end of the switch button S1 is electrically connected to the power supply, and the second end of the switch button S1 is electrically connected to the high-level detection connection pin 10.

[0065] The first power supply voltage output control circuit 3 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first power supply voltage output control circuit 3 is electrically connected to the power supply, the second input terminal of the first power supply voltage output control circuit 3 is electrically connected to the first level output pin 11, and the output terminal of the first power supply voltage output control circuit 3 is used to output the first power supply voltage.

[0066] When the switch button S1 is closed, the control chip 1 detects that the high-level detection connection pin 10 is high. The control chip 1 outputs a first high level through the first level output pin 11. The first high level output by the first level output pin 11 is input into the first power supply voltage output control circuit 3, which turns on the first power supply voltage output control circuit 3 and makes the output terminal of the first power supply voltage output control circuit 3 connected to the power supply and output the first power supply voltage.

[0067] In this embodiment, asFigure 1 As shown, the power supply voltage management circuit in this embodiment includes a control chip 1. The control chip 1 includes a high-level detection connection pin 10 and a first-level output pin 11, and the switch button S1 is set on the power-on / off control branch. In addition, the first input terminal of the first power supply voltage output control circuit 3 is electrically connected to the power supply, and the output terminal of the first power supply voltage output control circuit 3 is used to output the first power supply voltage. Furthermore, when the switch button S1 is closed, the first high-level signal output from the first-level output pin 11 is input into the first power supply voltage output control circuit 3, so that the output terminal of the first power supply voltage output control circuit 3 is connected to the power supply and outputs the first power supply voltage. Thus, the first power supply voltage is directly supplied by the power supply without going through the switch button S1. The switch button S1 only plays the role of controlling the first power supply voltage output control circuit 3 to open and close, avoiding the switch button S1 from having an adverse effect on the stability of the power supply, and thus helping to ensure the stability of the first power supply voltage output by the power supply to the output terminal of the first power supply voltage output control circuit 3. Therefore, setting the power supply voltage management circuit in this embodiment in the electronic detonator initiation controller is beneficial to improving the operational stability of the electronic detonator initiation controller.

[0068] In this embodiment, as Figure 1 As shown, in this embodiment, the power supply outputs the power supply voltage through the VBAT pin, and the first power supply voltage in this embodiment is specifically output through the VBAT1 pin. Furthermore, the power supply voltage output by the VBAT pin in this embodiment is 4.25V. The power supply voltage output by the VBAT pin can also be replaced with other power supplies as needed to achieve other voltage values.

[0069] In this embodiment, as Figure 1 As shown, in the power-on / off circuit 2 of this embodiment, the power-on / off control branch also includes a thirteenth resistor R13. The thirteenth resistor R13 is connected between the switch button S1 and the power supply. When the switch button S1 is not pressed, the thirteenth resistor R13 can pull the level of the pin of the switch button S1 high to the power supply level, ensuring that the pin of the switch button S1 is in a certain high-level state, avoiding unstable level due to the pin of the switch button S1 being floating, resulting in false triggering or logic confusion. In addition, the thirteenth resistor R13 can prevent excessive inrush current from being generated when the switch button S1 is closed, as the voltage of the power supply is directly applied to the power-on / off control branch, which could damage the switch button S1 and the circuit components connected to it.

[0070] In this embodiment, as Figure 1As shown, in this embodiment, the control chip 1 is specifically an MCU chip, the high-level detection connection pin 10 on the MCU chip is specifically the Powkey pin, the first level output pin 11 is specifically the Mcutr pin, the second level output pin 12 is specifically the PowHigh pin, and the third level output pin 13 is specifically the GBWSL_ON pin.

[0071] In this embodiment, as Figure 1 As shown, the output terminal of the first power supply voltage output control circuit 3 is connected to a current-limiting resistor F1. The current-limiting resistor F1 can share part of the power supply voltage, ensuring that the voltage of the first power supply voltage output from the output terminal of the first power supply voltage output control circuit 3 is kept within a suitable range, which is beneficial for the first power supply voltage output control circuit 3 to output a stable voltage.

[0072] It should be noted that the power supply voltage management circuit in this embodiment can be set in the electronic detonator initiation controller to improve the stability of the electronic detonator initiation controller's operation; alternatively, the power supply voltage management circuit in this embodiment can be set in other electronic devices powered by rechargeable batteries to improve the stability of the operation of other electronic devices powered by rechargeable batteries.

[0073] One embodiment of this application, such as Figure 1 As shown, the control chip 1 also includes a second-level output pin 12 and a third-level output pin 13;

[0074] The power supply voltage management circuit also includes:

[0075] The second power supply voltage output control circuit 6 includes a first switch control branch and a second switch control branch. The input terminal of the first switch control branch is electrically connected to the second level output pin 12. The second switch control branch includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second switch control branch is electrically connected to the third level output pin 13. The second input terminal of the second switch control branch is electrically connected to the output terminal of the first switch control branch. The output terminal of the second switch control branch is used to output the control voltage.

[0076] The second power supply voltage output control circuit 6 also includes a third switch control branch. The third switch control branch includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the third switch control branch is electrically connected to the output terminal of the second switch control branch. The second input terminal of the third switch control branch is electrically connected to the output terminal of the first power supply voltage output control circuit 3. The output terminal of the third switch control branch is used to output the second power supply voltage.

[0077] Specifically, when the control chip 1 detects that the high-level detection connection pin 10 is high, the control chip 1 controls the second-level output pin 12 to be low, and the output terminal of the first switch control branch outputs the second high level; and when the control chip 1 outputs the third high level through the third-level output pin 13, the second high level input to the output terminal of the first switch control branch and the third high level output by the third-level output pin 13 are input into the second switch control branch, and the control voltage output by the second switch control branch is the fourth high level. The fourth high level is input into the third switch control branch, which turns on the third switch control branch and makes the output terminal of the third switch control branch connected with the output terminal of the first power supply voltage output control circuit 3 and outputs the second power supply voltage.

[0078] In this embodiment, as Figure 1 As shown, the control chip 1 in this embodiment further includes a second-level output pin 12 and a third-level output pin 13. This embodiment also includes a second power supply voltage output control circuit 6, which comprises a first switch control branch, a second switch control branch, and a third switch control branch. By controlling the third switch control branch to open, the output terminal of the third switch control branch is connected to the output terminal of the first power supply voltage output control circuit 3, thus outputting the second power supply voltage and meeting power supply requirements. Furthermore, in this embodiment, the second power supply voltage is specifically output through the VBAT2 pin.

[0079] One embodiment of this application, such as Figure 1 and Figure 2 As shown, the first switch control branch includes:

[0080] NAND gate chip U1 includes a first input pin, a second input pin, a power connection pin, a ground connection pin, and a voltage output pin. The first input pin and the second input pin of NAND gate chip U1 are electrically connected to the second level output pin 12, respectively. The power connection pin of NAND gate chip U1 is used to input the first power supply voltage. The ground connection pin of NAND gate chip U1 is grounded. The voltage output pin of NAND gate chip U1 is used to output the first logic voltage.

[0081] The second switch control branch includes:

[0082] AND gate chip U2 includes a first input pin, a second input pin, a power connection pin, a ground connection pin, and a voltage output pin. The first input pin of AND gate chip U2 is electrically connected to the third level output pin 13. The second input pin of AND gate chip U2 is electrically connected to the output pin of NAND gate chip U1. A pull-down resistor R14 is connected to the connection line connecting the first input pin of AND gate chip U2 and the third level output pin 13. One end of the pull-down resistor R14 is electrically connected to the connection line, and the other end of the pull-down resistor R14 is grounded. The power connection pin of AND gate chip U2 is used to input a second power supply voltage. The ground connection pin of AND gate chip U2 is grounded. The voltage output pin of AND gate chip U2 is used to output a second logic voltage.

[0083] The third switch control branch includes:

[0084] The first NMOS transistor Q1 has its gate electrically connected to the output pin of the AND gate chip U2, its source grounded, and its source electrically connected to its gate through the first resistor R1. The drain of the first NMOS transistor Q1 is electrically connected to its source through the first parasitic diode.

[0085] The gate of the first PMOS transistor Q2 is electrically connected to the drain of the first NMOS transistor Q1, the source of the first PMOS transistor Q2 is electrically connected to the output terminal of the first power supply voltage output control circuit 3, and the source of the first PMOS transistor Q2 is electrically connected to the gate of the first PMOS transistor Q2 through the second resistor R2, and the drain of the first PMOS transistor Q2 is electrically connected to the source of the first PMOS transistor Q2 through the second parasitic diode.

[0086] When the control chip 1 controls the second level output pin 12 to be low, the first logic voltage output by the voltage output pin of the NAND gate chip U1 is the second high level. When the control chip 1 outputs the third high level through the third level output pin 13, the second logic voltage output by the voltage output pin of the AND gate chip U2 is the fourth high level. The gate of the first NMOS transistor Q1 is high, and the source and drain of the first NMOS transistor Q1 are connected. The gate of the first PMOS transistor Q2 is high, and the source and drain of the first PMOS transistor Q2 are cut off. The output terminal of the third switch control branch is connected to the output terminal of the first power supply voltage output control circuit 3 and outputs the second power supply voltage.

[0087] In this embodiment, as Figure 1 and Figure 2As shown, in this embodiment, the first switch control branch includes a NAND gate chip U1, the second switch control branch includes an AND gate chip U2, and the third switch control branch includes a first NMOS transistor Q1 and a first PMOS transistor Q2. The NAND gate chip U1, the AND gate chip U2, the first NMOS transistor Q1, and the first PMOS transistor Q2 all serve as logic switches, which facilitates the control of the output terminal of the third switch control branch and the output terminal of the first power supply voltage output control circuit 3 to be on and off. This facilitates the provision of the second power supply voltage, which is beneficial to meeting power supply requirements and simplifies the circuit structure.

[0088] In this embodiment, as Figure 2 As shown, in this embodiment, the power supply pin of the NAND gate chip U1 is used to input a 3.3V voltage. This 3.3V voltage is provided by parallel power supply capacitors C2, C3, and C4. Similarly, in this embodiment, the power supply pin of the AND gate chip U2 is also used to input a 3.3V voltage, which is also provided by parallel power supply capacitors C2, C3, and C4. Furthermore, in this embodiment, a pull-down resistor R14 is connected to the connection line between the first input pin and the third level output pin 13 of the AND gate chip U2. This can change the input / output characteristics of the logic gate, which is beneficial for implementing logical operations.

[0089] One embodiment of this application, such as Figure 1 As shown, the power supply voltage management circuit also includes:

[0090] USB power supply control circuit 4 includes a USB interface, a third resistor R3, a fourth resistor R4, and a second PMOS transistor Q3. The USB interface is used to electrically connect to the power supply device via a USB cable. The first end of the third resistor R3 is electrically connected to the USB interface, and the second end of the third resistor R3 is electrically connected to the gate of the second PMOS transistor Q3. The drain of the second PMOS transistor Q3 is electrically connected to the gate of the second PMOS transistor Q3 through the fourth resistor R4. The source of the second PMOS transistor Q3 is electrically connected to the drain of the second PMOS transistor Q3 through the third parasitic diode, and the drain of the second PMOS transistor Q3 is grounded. The source of the second PMOS transistor Q3 is electrically connected to the second input terminal of the first power supply voltage output control circuit 3.

[0091] The USB interface is also electrically connected to the output terminal of the first power supply voltage output control circuit 3 through the first diode D1. The conduction direction of the first diode D1 is from the USB interface to the output terminal of the first power supply voltage output control circuit 3.

[0092] When the USB cable, which is electrically connected to the power supply device, is plugged into the USB interface and supplies power to the USB interface, the USB power supply control circuit 4 outputs a fifth high level. The fifth high level is input into the first power supply voltage output control circuit 3, which turns off the first power supply voltage output control circuit 3 and cuts off the connection between the output terminal of the first power supply voltage output control circuit 3 and the power supply. The USB cable plugged into the USB interface supplies power to the output terminal of the first power supply voltage output control circuit 3.

[0093] In this embodiment, as Figure 1 As shown, in this embodiment, a USB power supply control circuit 4 is provided. When the USB cable, which is electrically connected to the power supply device, is plugged into the USB interface and supplies power to the USB interface, the USB power supply control circuit 4 outputs a fifth high level. The fifth high level is input into the first power supply voltage output control circuit 3, causing the first power supply voltage output control circuit 3 to turn off and cut off the connection between the output terminal of the first power supply voltage output control circuit 3 and the power supply. The USB cable plugged into the USB interface supplies power to the output terminal of the first power supply voltage output control circuit 3, thereby realizing power supply and charging through the USB cable, increasing the function of the power supply voltage management circuit, and improving the practicality of the power supply voltage management circuit.

[0094] In this embodiment, when the power supply voltage management circuit is applied to the electronic detonator initiation controller, the voltage supplied by the USB cable to the output terminal of the first power supply voltage output control circuit 3 is 5V; in addition, when the power supply voltage management circuit is applied to other electronic devices powered by rechargeable batteries, a USB cable and power supply device that can provide a matching voltage are selected according to the power supply voltage requirements of the electronic device powered by rechargeable batteries.

[0095] One embodiment of this application, such as Figure 1 As shown, the first power supply voltage output control circuit 3 includes:

[0096] The gate of the second NMOS transistor Q4 is electrically connected to the high-level detection pin 10. The source of the second NMOS transistor Q4 is grounded, and the source of the second NMOS transistor Q4 is electrically connected to the gate of the second NMOS transistor Q4 through the fifth resistor R5. The drain of the first NMOS transistor Q1 is electrically connected to the source of the second NMOS transistor Q4 through the fourth parasitic diode.

[0097] The gate of the third PMOS transistor Q5 is electrically connected to the drain of the second NMOS transistor Q4. The source of the third PMOS transistor Q5 is electrically connected to the gate of the third PMOS transistor Q5 through the sixth resistor R6. The drain of the third PMOS transistor Q5 is electrically connected to the power supply. The drain of the third PMOS transistor Q5 is also electrically connected to the source of the third PMOS transistor Q5 through the fifth parasitic diode.

[0098] The gate of the fourth PMOS transistor Q6 is electrically connected to the drain of the second NMOS transistor Q4, the source of the fourth PMOS transistor Q6 is electrically connected to the source of the third PMOS transistor Q5, and the source of the fourth PMOS transistor Q6 is electrically connected to the gate of the fourth PMOS transistor Q6 through the sixth resistor R6. The drain of the fourth PMOS transistor Q6 is electrically connected to the output terminal of the first power supply voltage output control circuit 3, and the drain of the fourth PMOS transistor Q6 is electrically connected to the source of the fourth PMOS transistor Q6 through the sixth parasitic diode.

[0099] In this embodiment, as Figure 1 As shown, the first power supply voltage output control circuit 3 in this embodiment includes a second NMOS transistor Q4, a third PMOS transistor Q5, and a fourth PMOS transistor Q6. The first power supply voltage output control circuit 3 is mainly composed of NMOS transistors and PMOS transistors. NMOS transistors and PMOS transistors are logic switches, which facilitates the control of the first power supply voltage output control circuit 3 to turn on and off by adjusting the level, and improves the stability and reliability of the control of the first power supply voltage output control circuit 3 to turn on and off.

[0100] One embodiment of this application, such as Figure 1 As shown, the power supply voltage management circuit also includes:

[0101] USB cable plug-in / plug-out protection circuit 5, which includes:

[0102] The gate of the third NMOS transistor Q7 is electrically connected to the high-level detection pin 10. The source of the third NMOS transistor Q7 is grounded, and the source of the third NMOS transistor Q7 is electrically connected to the gate of the third NMOS transistor Q7 through the seventh resistor R7. The drain of the third NMOS transistor Q7 is electrically connected to the source of the third NMOS transistor Q7 through the seventh parasitic diode.

[0103] The gate of the fifth PMOS transistor Q8 is electrically connected to the drain of the third NMOS transistor Q7. The source of the fifth PMOS transistor Q8 is electrically connected to the power supply. The source of the fifth PMOS transistor Q8 is electrically connected to the gate of the fifth PMOS transistor Q8 through the eighth resistor R8. The drain of the fifth PMOS transistor Q8 is electrically connected to the source of the fifth PMOS transistor Q8 through the eighth parasitic diode. The drain of the fifth PMOS transistor Q8 is electrically connected to the output terminal of the first power supply voltage output control circuit 3 through the second diode D2. The conduction direction of the second diode D2 is from the drain of the fifth PMOS transistor Q8 to the output terminal of the first power supply voltage output control circuit 3.

[0104] In this embodiment, as Figure 1As shown, this embodiment includes a USB cable plug-in / plug-out protection circuit 5, which comprises a third NMOS transistor Q7 and a fifth PMOS transistor Q8. This allows for easy control of the USB cable plug-in / plug-out protection circuit 5's activation and deactivation by adjusting its voltage levels. When the USB cable is unplugged while the device is powered on, the output of the first power supply voltage output control circuit 3 is powered by a power supply electrically connected to the source of the fifth PMOS transistor Q8, ensuring that the output of the first power supply voltage output control circuit 3 is powered and preventing the module or system powered by the first power supply voltage output control circuit 3 from shutting down. When the USB cable is plugged into the USB interface, the output of the first power supply voltage output control circuit 3 is powered by the USB cable.

[0105] One embodiment of this application, such as Figure 1 As shown, the power-on / off circuit 2 also includes:

[0106] The fourth NMOS transistor Q9 has its gate electrically connected to the high-level detection pin 10, its source grounded, and its source electrically connected to its gate through the ninth resistor R9. The drain of the fourth NMOS transistor Q9 is electrically connected to its source through the ninth parasitic diode.

[0107] The gate of the sixth PMOS transistor Q10 is electrically connected to the drain of the fourth NMOS transistor Q9. The source of the sixth PMOS transistor Q10 is electrically connected to the power supply. The source of the sixth PMOS transistor Q10 is electrically connected to the gate of the sixth PMOS transistor Q10 through the tenth resistor R10. The drain of the sixth PMOS transistor Q10 is electrically connected to the source of the sixth PMOS transistor Q10 through the tenth parasitic diode. The drain of the sixth PMOS transistor Q10 is electrically connected to the second input terminal of the first power supply voltage output control circuit 3 through the eleventh resistor R11 and the third diode D3 connected in series. The conduction direction of the third diode D3 is from the drain of the sixth PMOS transistor Q10 to the second input terminal of the first power supply voltage output control circuit 3.

[0108] In this embodiment, as Figure 1As shown, the power-on / off circuit 2 in this embodiment includes a fourth NMOS transistor Q9 and a sixth PMOS transistor Q10. When the switch button S1 is closed, the gate of the fourth NMOS transistor Q9 is at a high level, and the source and drain of the fourth NMOS transistor Q9 are connected, causing the gate of the sixth PMOS transistor Q10 to be at a low level, and the source and drain of the sixth PMOS transistor Q10 to be connected. At the initial time when the switch button S1 is pressed, the power supply supplies power to the gate of the second NMOS transistor Q4 through the second input terminal of the first power supply voltage output control circuit 3, causing the second NMOS transistor Q4 to be at a low level. When the gate of the OS transistor Q4 is at a high level, the source and drain of the second NMOS transistor Q4 are connected, which in turn makes the gates of the third PMOS transistor Q5 and the fourth PMOS transistor Q6 at a low level. The source and drain of the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are connected respectively, so that the output terminal of the first power supply voltage output control circuit 3 is connected to the power supply and outputs the first power supply voltage. Thus, at the initial time of pressing the switch button S1, the output terminal of the first power supply voltage output control circuit 3 is ensured to output the first power supply voltage, shortening the output time of the first power supply voltage.

[0109] In this embodiment, when the USB cable is plugged into the USB interface, the input voltage of the USB cable is 5V, the output voltage of the USB cable plugging and unplugging protection circuit 5 is 4.25V, and the output of the first power supply voltage output control circuit 3 is powered by the USB cable. When the USB cable is unplugged, the power supply is supplied through the VBAT pin, the fifth PMOS transistor Q8, and the second diode D2. Then, the gate of the fourth NMOS transistor Q9 returns to a high level, and the fourth NMOS transistor Q9 is turned on. The gates of the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are at low levels, and the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are turned on. Since the voltage drop of the power supply voltage output from the VBAT pin after passing through the third PMOS transistor Q5 and the fourth PMOS transistor Q6 is less than the voltage drop of the power supply voltage output from the VBAT pin after passing through the fifth PMOS transistor Q8 and the second diode D2, the power supply voltage output from the VBAT pin is normally supplied through the third PMOS transistor Q5 and the fourth PMOS transistor Q6.

[0110] One embodiment of this application, such as Figure 1 As shown, the power-on / off circuit 2 also includes:

[0111] Anti-shake capacitor C1, the first terminal of anti-shake capacitor C1 is electrically connected to the second terminal of switch button S1, and the second terminal of anti-shake capacitor C1 is grounded.

[0112] In this embodiment, as Figure 1As shown, in this embodiment, an anti-shake capacitor C1 is provided to reduce the jitter of the switch button S1 by utilizing the characteristics of the anti-shake capacitor C1 itself. Specifically, at the moment the switch button S1 is closed, the anti-shake capacitor C1 is charged, and the current changes smoothly to avoid misjudgment due to sudden voltage changes; at the moment the switch button S1 is opened, the capacitor discharges to maintain voltage stability, thereby reducing or preventing the jitter of the switch button S1.

[0113] One embodiment of this application, such as Figure 1 As shown, a twelfth resistor R12 and a fourth diode D4 are connected between the second input terminal of the first power supply voltage output control circuit 3 and the first level output pin 11. The twelfth resistor R12 and the fourth diode D4 are connected in series. The conduction direction of the fourth diode D4 is from the first level output pin 11 to the second input terminal of the first power supply voltage output control circuit 3. The second input terminal of the first power supply voltage output control circuit 3 is connected between the third diode D3 and the fourth diode D4.

[0114] In this embodiment, as Figure 1 As shown, in this embodiment, the twelfth resistor R12 and the fourth diode D4 are connected between the second input terminal of the first power supply voltage output control circuit 3 and the first level output pin 11, which helps to limit the direction of voltage and current; the second input terminal of the first power supply voltage output control circuit 3 is connected between the third diode D3 and the fourth diode D4, which helps to ensure that the second input terminal of the first power supply voltage output control circuit 3 has a normal input voltage.

[0115] It should be noted that the power supply in this application is specifically a power battery. The voltage that the power battery can provide can be selected according to the appropriate specifications of the power battery as needed. In this embodiment, the power supply can also be a mobile power supply. Furthermore, the resistance values ​​of the first resistor R1 to the thirteenth resistor R13 and the pull-down resistor R14 in this embodiment can be reasonably selected based on the voltage value that the power supply can provide, the voltage value of the first power supply voltage output from the output terminal of the first power supply voltage output control circuit 3, the voltage value of the second power supply voltage, and the overall circuit. The specific specifications and types of other electronic components in this application can also be selected. Based on the technical solution disclosed in this application, adjustments can be made according to the power supply voltage requirements of different electronic devices to meet the power supply requirements. The specifications and types of each electronic component will not be listed one by one in this application.

[0116] Another aspect of this application provides an electronic detonator initiation controller, comprising:

[0117] The main body has an installation cavity inside;

[0118] The control module is installed inside the mounting cavity, and the control module includes the aforementioned power supply voltage management circuit.

[0119] In this embodiment, the control module of the electronic detonator initiation controller includes the aforementioned power supply voltage management circuit, which is beneficial to improving the operational stability of the electronic detonator initiation controller. This, in turn, improves the stability and accuracy of the electronic detonator detection, networking, and initiation control via the electronic detonator initiation controller. Furthermore, other components of the control module in this embodiment can be referenced from existing electronic detonator control modules, and will not be described in detail here. Additionally, the electronic detonator initiation controller is not illustrated in this embodiment; its specific structure and other components can be referenced from existing technologies in the field.

[0120] Furthermore, in this embodiment, when the control module includes circuit board one and circuit board two, power can be supplied to circuit board one through a first power supply voltage and to circuit board two through a second power supply voltage.

[0121] In addition to the technical solutions disclosed in this embodiment, other components of the control chip 1, PMOS transistor, NMOS transistor, NAND gate chip U1, AND gate chip U2, capacitor, control module, electronic detonator initiation controller, and their working principles can be referred to conventional technical solutions in this technical field. However, these conventional technical solutions are not the focus of this utility model, and will not be described in detail here.

[0122] In this utility model, the term "multiple" refers to two or more unless otherwise explicitly defined. The terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0123] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0124] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A power supply voltage management circuit, characterized in that, include: The control chip includes a high-level detection pin and a first-level output pin. A power on / off circuit, comprising a power on / off control branch for controlling power on and power off, and a power on / off control branch having a switch button, the first end of which is electrically connected to the power supply, and the second end of which is electrically connected to the high-level detection pin. A first power supply voltage output control circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first power supply voltage output control circuit is electrically connected to the power supply, the second input terminal of the first power supply voltage output control circuit is electrically connected to the first level output pin, and the output terminal of the first power supply voltage output control circuit is used to output a first power supply voltage. When the switch button is closed, the control chip detects that the high-level detection connection pin is high. The control chip outputs a first high level through the first level output pin. The first high level output by the first level output pin is input into the first power supply voltage output control circuit, which turns on the first power supply voltage output control circuit and connects the output terminal of the first power supply voltage output control circuit to the power supply and outputs the first power supply voltage.

2. The power supply voltage management circuit according to claim 1, characterized in that, The control chip also includes a second-level output pin and a third-level output pin; Also includes: The second power supply voltage output control circuit includes a first switch control branch and a second switch control branch. The input terminal of the first switch control branch is electrically connected to the second level output pin. The second switch control branch includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second switch control branch is electrically connected to the third level output pin. The second input terminal of the second switch control branch is electrically connected to the output terminal of the first switch control branch. The output terminal of the second switch control branch is used to output a control voltage. The second power supply voltage output control circuit further includes a third switch control branch, which includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the third switch control branch is electrically connected to the output terminal of the second switch control branch, and the second input terminal of the third switch control branch is electrically connected to the output terminal of the first power supply voltage output control circuit. The output terminal of the third switch control branch is used to output the second power supply voltage. Specifically, when the control chip detects that the high-level detection pin is high, the control chip controls the second level output pin to be low, and the output terminal of the first switch control branch outputs a second high level; and when the control chip outputs a third high level through the third level output pin, the second high level input to the output terminal of the first switch control branch and the third high level output by the third level output pin are input into the second switch control branch, and the control voltage output by the second switch control branch is a fourth high level. The fourth high level is input into the third switch control branch, causing the third switch control branch to turn on, and causing the output terminal of the third switch control branch to be connected to the output terminal of the first power supply voltage output control circuit and output the second power supply voltage.

3. The power supply voltage management circuit according to claim 2, characterized in that, The first switch control branch includes: The NAND gate chip includes a first input pin, a second input pin, a power connection pin, a ground connection pin, and a voltage output pin. The first input pin and the second input pin of the NAND gate chip are electrically connected to the second level output pin, the power connection pin of the NAND gate chip is used to input a first power supply voltage, the ground connection pin of the NAND gate chip is grounded, and the voltage output pin of the NAND gate chip is used to output a first logic voltage. The second switch control branch includes: An AND gate chip includes a first input pin, a second input pin, a power connection pin, a ground connection pin, and a voltage output pin. The first input pin of the AND gate chip is electrically connected to the third-level output pin. The second input pin of the AND gate chip is electrically connected to the output pin of the NAND gate chip. A pull-down resistor is connected to the connection line connecting the first input pin and the third-level output pin of the AND gate chip. One end of the pull-down resistor is electrically connected to the connection line, and the other end of the pull-down resistor is grounded. The power connection pin of the AND gate chip is used to input a second power supply voltage. The ground connection pin of the AND gate chip is grounded. The voltage output pin of the AND gate chip is used to output a second logic voltage. The third switch control branch includes: The first NMOS transistor has its gate electrically connected to the output pin of the AND gate chip, its source grounded, and its source electrically connected to its gate through a first resistor. The drain of the first NMOS transistor is electrically connected to its source through a first parasitic diode. The first PMOS transistor has its gate electrically connected to the drain of the first NMOS transistor, its source electrically connected to the output terminal of the first power supply voltage output control circuit, and its source electrically connected to its gate through a second resistor, and its drain electrically connected to its source through a second parasitic diode. When the control chip controls the second level output pin to be low, the first logic voltage output by the voltage output pin of the NAND gate chip is the second high level. When the control chip outputs the third high level through the third level output pin, the second logic voltage output by the voltage output pin of the AND gate chip is the fourth high level. The gate of the first NMOS transistor is high, and the source and drain of the first NMOS transistor are connected. The gate of the first PMOS transistor is high, and the source and drain of the first PMOS transistor are cut off. The output terminal of the third switch control branch is connected to the output terminal of the first power supply voltage output control circuit and outputs the second power supply voltage.

4. The power supply voltage management circuit according to claim 2, characterized in that, Also includes: The USB power supply control circuit includes a USB interface, a third resistor, a fourth resistor, and a second PMOS transistor. The USB interface is used to electrically connect to a power supply device via a USB cable. The first end of the third resistor is electrically connected to the USB interface, and the second end of the third resistor is electrically connected to the gate of the second PMOS transistor. The drain of the second PMOS transistor is electrically connected to the gate of the second PMOS transistor via the fourth resistor. The source of the second PMOS transistor is electrically connected to the drain of the second PMOS transistor via a third parasitic diode, and the drain of the second PMOS transistor is grounded. The source of the second PMOS transistor is electrically connected to the second input terminal of the first power supply voltage output control circuit. The USB interface is also electrically connected to the output terminal of the first power supply voltage output control circuit via a first diode, wherein the conduction direction of the first diode is from the USB interface to the output terminal of the first power supply voltage output control circuit; When the USB cable, which is electrically connected to the power supply device, is plugged into the USB interface and supplies power to the USB interface, the USB power supply control circuit outputs a fifth high level. The fifth high level is input into the first power supply voltage output control circuit, causing the first power supply voltage output control circuit to turn off and disconnecting the output terminal of the first power supply voltage output control circuit from the power supply. The USB cable plugged into the USB interface supplies power to the output terminal of the first power supply voltage output control circuit.

5. The power supply voltage management circuit according to claim 4, characterized in that, The first power supply voltage output control circuit includes: The second NMOS transistor has its gate electrically connected to the high-level detection pin, its source grounded, and its source electrically connected to its gate through a fifth resistor. The drain of the first NMOS transistor is electrically connected to the source of the second NMOS transistor through a fourth parasitic diode. The third PMOS transistor has its gate electrically connected to the drain of the second NMOS transistor, its source electrically connected to its gate through a sixth resistor, its drain electrically connected to the power supply, and its drain electrically connected to its source through a fifth parasitic diode. The fourth PMOS transistor has its gate electrically connected to the drain of the second NMOS transistor, its source electrically connected to the source of the third PMOS transistor, and its source electrically connected to its gate through the sixth resistor. The drain of the fourth PMOS transistor is electrically connected to the output terminal of the first power supply voltage output control circuit, and its drain is electrically connected to its source through the sixth parasitic diode.

6. The power supply voltage management circuit according to claim 4, characterized in that, Also includes: USB cable plug-in / plug-out protection circuit, the USB cable plug-in / plug-out protection circuit includes: The third NMOS transistor has its gate electrically connected to the high-level detection pin, its source grounded, and its source electrically connected to its gate through a seventh resistor. The drain of the third NMOS transistor is electrically connected to its source through a seventh parasitic diode. The fifth PMOS transistor has its gate electrically connected to the drain of the third NMOS transistor, its source electrically connected to the power supply, and its source electrically connected to its gate through an eighth resistor. The drain of the fifth PMOS transistor is electrically connected to its source through an eighth parasitic diode, and its drain is electrically connected to the output terminal of the first power supply voltage output control circuit through a second diode. The conduction direction of the second diode is from the drain of the fifth PMOS transistor to the output terminal of the first power supply voltage output control circuit.

7. The power supply voltage management circuit according to any one of claims 1 to 6, characterized in that, The power-on / off circuit also includes: The fourth NMOS transistor has its gate electrically connected to the high-level detection pin, its source grounded, and its source electrically connected to its gate through a ninth resistor. The drain of the fourth NMOS transistor is electrically connected to its source through a ninth parasitic diode. The sixth PMOS transistor has its gate electrically connected to the drain of the fourth NMOS transistor, its source electrically connected to the power supply, and its source electrically connected to its gate through a tenth resistor. The drain of the sixth PMOS transistor is electrically connected to its source through a tenth parasitic diode. The drain of the sixth PMOS transistor is electrically connected to the second input terminal of the first power supply voltage output control circuit through a series eleventh resistor and a third diode. The conduction direction of the third diode is from the drain of the sixth PMOS transistor towards the second input terminal of the first power supply voltage output control circuit.

8. The power supply voltage management circuit according to claim 7, characterized in that, The power-on / off circuit also includes: The anti-shake capacitor has its first terminal electrically connected to the second terminal of the switch button, and its second terminal is grounded.

9. The power supply voltage management circuit according to claim 7, characterized in that, A twelfth resistor and a fourth diode are connected between the second input terminal of the first power supply voltage output control circuit and the first level output pin. The twelfth resistor and the fourth diode are connected in series. The conduction direction of the fourth diode is from the first level output pin to the second input terminal of the first power supply voltage output control circuit. The second input terminal of the first power supply voltage output control circuit is connected between the third diode and the fourth diode.

10. An electronic detonator initiation controller, characterized in that, include: The main body has an installation cavity inside; A control module is installed in the mounting cavity, and the control module includes the power supply voltage management circuit as described in any one of claims 1 to 9.

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