Harmonic measuring device
By controlling the sampling frequency of the harmonic measurement device through hardware circuitry, the problems of high MCU resource consumption and error were solved, achieving accuracy and synchronization in harmonic calculation and reducing MCU resource usage.
Patent Information
- Application Number
- CN202422336727.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2034-09-25
AI Technical Summary
In existing technologies, MCUs consume a lot of resources and may produce errors when controlling the sampling frequency of ADCs, resulting in inaccurate harmonic calculations.
The system employs a combination of MCU control unit, analog sampling unit, frequency conversion unit and pulse width modulation unit, and utilizes phase-locked loop chip and binary frequency divider chip to achieve frequency following. The sampling frequency is controlled by hardware circuitry to make it change synchronously with the input signal frequency, thus avoiding MCU resource occupation.
It achieves accuracy and synchronization in harmonic calculation, reduces MCU resource consumption, and ensures accurate and error-free sampling frequency.
Smart Images
Figure CN223711708U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of harmonic measurement technology, specifically relating to a harmonic measurement device that does not occupy MCU resources. Background Technology
[0002] With the widespread application of various power electronic devices, harmonic pollution in public power grids has become increasingly serious. Harmonics cause additional harmonic losses in components of public power grids, reducing the efficiency of power generation, transmission and consumption equipment. Various faults and accidents caused by harmonics are also constantly occurring.
[0003] Strictly speaking, harmonics refer to the electrical quantities in an electric current whose frequencies are integer multiples of the fundamental frequency. Generally, they refer to the electrical quantities generated by currents with frequencies higher than the fundamental frequency after performing Fourier series decomposition on periodic non-sinusoidal electrical quantities. A common method for calculating harmonics is to use the Fast Fourier Transform (FFT), which involves substituting the sampled points of the input signal into the FFT formula to obtain the content values of each harmonic.
[0004] To obtain accurate FFT harmonic calculation results, the number of sampling points must be an integer power of 2. This requires the sampling frequency to be an integer power of 2 of the input signal frequency. Currently, the common practice is to acquire the input signal frequency and then modify the sampling frequency of the ADC (analog-to-digital converter) through an MCU (microcontroller or microprocessor) to make the sampling frequency reach an integer power of 2 of the input signal frequency.
[0005] When using an MCU to modify the sampling frequency of an ADC, the MCU must wait for the calculation to complete before the corresponding input signal frequency can be modified. Therefore, the MCU's control over the sampling frequency has a significant lag, and the frequency of the external input signal may keep changing. This causes the MCU to consume a lot of resources to modify the input signal frequency and may also introduce errors in the sampling frequency calculation. Summary of the Invention
[0006] To solve the aforementioned technical problems and achieve accurate measurement of harmonic content in input signals, this invention provides a harmonic measurement device that does not occupy MCU resources. The technical solution adopted by this invention is as follows:
[0007] A harmonic measurement device includes: an MCU control unit, an analog sampling unit, a frequency conversion unit, and a pulse width modulation unit. The analog sampling unit is electrically connected to the MCU control unit, the frequency conversion unit, and the pulse width modulation unit, respectively. The frequency conversion unit is electrically connected to the pulse width modulation unit. The frequency conversion unit includes a phase-locked loop chip U5 and a binary frequency divider chip U6, which are electrically connected. The pulse width modulation unit includes a D flip-flop U8, a D flip-flop U9, and a NAND gate U7. The D flip-flop U8 is electrically connected to the D flip-flop U9 and the NAND gate U7, respectively. The D flip-flop U9 is electrically connected to the NAND gate U7.
[0008] Preferably, pin 4 of the phase-locked loop chip U5 is electrically connected to pin 10 of the binary frequency divider chip U6, and pin 3 of the phase-locked loop chip U5 is electrically connected to pin 14 of the binary frequency divider chip U6.
[0009] Preferably, pin 10 of the binary frequency divider chip U6 is electrically connected to pin 3 of the D flip-flop U8, pin 4 of the D flip-flop U8 is electrically connected to pin 3 of the D flip-flop U9 and pin 1 of the NAND gate U7, pin 4 of the D flip-flop U9 is electrically connected to pin 12 of the NAND gate U7, and pin 2 of the NAND gate U7 is electrically connected to pin 11 of the NAND gate U7.
[0010] The beneficial effects of this utility model are:
[0011] This invention does not occupy MCU resources for sampling frequency calculation. The MCU does not need to control the sampling frequency, enabling synchronous testing. Even if the input signal fluctuates continuously, the hardware circuit can still follow the frequency. This ensures that the sampling frequency and the input signal frequency change synchronously, resulting in more accurate data acquisition and more precise harmonic calculation. Attached Figure Description
[0012] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings:
[0013] Figure 1 This is a schematic diagram of the overall structure of the harmonic measurement device according to an embodiment of the present invention;
[0014] Figure 2 This is a schematic diagram of the circuit structure of the analog sampling unit according to an embodiment of the present invention;
[0015] Figure 3 This is a schematic diagram of the circuit structure of the frequency conversion unit and the pulse width modulation unit according to an embodiment of the present invention;
[0016] Figure 4 This is a schematic diagram of the data interaction relationship between the modules in an embodiment of this utility model;
[0017] Figure 5 This is a feedback model diagram of the phase-locked loop module according to an embodiment of the present invention. Detailed Implementation
[0018] The technical solution of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments.
[0019] like Figure 1 As shown, a harmonic measurement device includes: an MCU control unit, an analog sampling unit, a frequency conversion unit, and a pulse width modulation unit. The analog sampling unit is electrically connected to the MCU control unit, the frequency conversion unit, and the pulse width modulation unit, respectively. The frequency conversion unit is electrically connected to the pulse width modulation unit.
[0020] The MCU control unit includes an MCU chip, and the MCU control unit contains a computing module M1. The computing module M1 is responsible for receiving data transmitted by the analog sampling unit and performing harmonic calculations.
[0021] like Figure 2 As shown, the analog sampling unit mainly includes: a frequency calculation module F1, which is mainly used to calculate the frequency of the input signal. This frequency calculation module F1 consists of an operational amplifier U1 and a hysteresis comparator U4; and an ADC data sampling module F2, which mainly consists of an operational amplifier U1, a single-ended to differential ADC driver U2, an analog-to-digital converter (ADC) chip U3, and peripheral circuitry. The ADC data sampling module F2 mainly collects data, converts the analog signal into a digital signal, and sends the digital signal to the MCU control unit. The conversion speed of the ADC data sampling module F2 is controlled by the CNV pin of the ADC chip U3. The circuit structure of this analog sampling unit is existing technology.
[0022] like Figure 3 As shown, the frequency conversion unit includes a phase-locked loop (PLL) module P1, which consists of a PLL chip U5 and a binary frequency divider chip U6. Pin 4 of the PLL chip U5 is electrically connected to pin 10 of the binary frequency divider chip U6, and pin 3 of the PLL chip U5 is electrically connected to pin 14 of the binary frequency divider chip U6. The binary frequency divider chip U6 can reduce the frequency of the input signal to 1 / N of its original value. DIV1024 in the diagram refers to a 1024-fold frequency divider, meaning the input signal frequency is reduced to 1 / 1024 of its original value. The PLL module P1 receives the frequency signal from the analog sampling unit and modifies the frequency to multiply the input signal frequency, resulting in an output frequency of f. pllThe pulse width modulation unit includes a duty cycle adjustment module C1, which consists of D flip-flops U8 and U9, and a NAND gate U7. Pin 10 of the binary frequency divider chip U6 is electrically connected to pin 3 of the D flip-flop U8. Pin 4 of the D flip-flop U8 is electrically connected to pin 3 of the D flip-flop U9 and pin 1 of the NAND gate U7. Pin 4 of the D flip-flop U9 is electrically connected to pin 12 of the NAND gate U7, and pin 2 of the NAND gate U7 is electrically connected to pin 11 of the NAND gate U7. The main function of the pulse width modulation unit is to receive the square wave signal sent by the frequency converter unit, change the duty cycle of the square wave signal, and send the changed signal to the ADC data sampling module F2, or more specifically, to the CNV pin of the analog-to-digital converter (ADC) chip U3.
[0023] like Figure 4 , 5 As shown in the figure, the working principle of the harmonic measurement device provided in this embodiment of the present invention is as follows:
[0024] ① The input signal under test is connected to the frequency calculation module F1. Taking voltage signal acquisition as an example, the input signal enters the voltage sampling circuit through the voltage input terminal J1 (U input). After passing through the inverting amplifier circuit composed of resistors R1 and R2 and operational amplifier U1, it is split into two paths. One path enters the single-ended to differential AD driver U2, and then directly enters the analog-to-digital converter (ADC) chip U3; the other path enters the hysteresis comparator U4, which extracts the AC signal, converts it into a square wave signal, and enters the MCU control unit. The MCU control unit obtains the number of zero-crossing points (num) and the time (t) used in the current calculation cycle through a counter. The current input signal frequency f0 is obtained by dividing num by t. Figure 2 As shown. It should be noted that the calculation of the input signal frequency is not the focus of this utility model. Since related hardware (such as phase-locked loops) often have requirements on the frequency range, the calculation of the input signal frequency is mainly used to determine whether the device can work normally.
[0025] ② The square wave signal after passing through the hysteresis comparator U4 is transmitted to the phase-locked loop module P1. The frequency of this square wave signal is f0. Figure 3 As shown, a square wave signal with frequency f0 is input to the phase-locked loop (PLL) chip U5. The main working principle of the PLL module is as follows: Figure 5 As shown, the phase-locked loop (PLL) chip SIGin receives a square wave signal with a frequency of f0, and the PLL chip outputs a signal VCOout (corresponding to...). Figure 5 The output of the medium-voltage controlled oscillator is connected to the binary frequency divider chip U6 (corresponding to...). Figure 5 The clock signal terminal CLK of the frequency divider is used by the binary frequency divider chip U6, which divides the frequency by 1024 times. The divided signal is then input to the comparator terminal COMPin of the phase-locked loop chip U5 (corresponding to...). Figure 5(Intermediate frequency phase detector). At this time, if Figure 2 The signal frequency transmitted from the hysteresis comparator U4 to the phase-locked loop (PLL) module P1 differs from the signal frequency received by COMPin. Therefore, the PLL module P1 will quickly correct the output signal frequency to match the input frequency. This achieves frequency multiplication of the signal (1024 times in the diagram) through the feedback of the PLL, thus multiplying the input signal frequency to an integer power of 2. pll .
[0026] ③ After the phase-locked loop module P1 completes its processing, the processed frequency f is... pll The sampled signal is transmitted to the pulse width modulation unit, which consists of a NAND gate U7, a D flip-flop U8, and a D flip-flop U9. When the rising pulse of the CLK (clock signal) of D flip-flops U8 and U9 arrives, the Q terminal latches the level of the D pin input. The diagram uses two D flip-flops, and the Q output of the front end is connected to the D pin of the back end, thus generating a frequency f after frequency multiplication by the phase-locked loop. pll The square wave signal, after being output by D flip-flop U9, achieves phase delay, with the delay period being exactly 1 / CLK. U7 is a NAND gate circuit; in this embodiment, it performs two NAND operations: the first inverts the waveform, and the second performs a NAND operation on the two waveforms. Performing a NAND operation on two waveforms with different phases results in a new waveform with the same frequency f. pll However, the duty cycle was modified. Because the ADC has requirements regarding the high-level duration of the CNV signal, the signal multiplied by the phase-locked loop cannot be directly used by the ADC. Figure 3 The sampling frequency signal adjusted by the circuit shown can be directly connected to the ADC data sampling module F2 of the analog sampling unit to control the sampling frequency of the analog sampling unit.
[0027] ④ADC (ADC sampling circuit, such as...) Figure 2 As shown in step ①, the data sampling module F2 transmits the acquired data to the calculation module M1 at this new sampling frequency. Since this sampling frequency can be controlled relatively accurately at multiples of 2 of the input signal under test, the harmonic data calculated by the calculation module M1 is relatively accurate, and synchronous calculation is achieved.
[0028] The harmonic measurement device provided in this embodiment of the invention controls the sampling frequency of harmonic acquisition entirely by hardware circuitry throughout the process, thus saving MCU resources.
[0029] In this embodiment of the utility model, all technical features not described in detail are existing technologies or conventional technical means, and will not be repeated here.
[0030] Finally, it should be noted that the above embodiments are merely specific implementations of this utility model, used to illustrate the technical solution of this utility model, and not to limit it. The protection scope of this utility model is not limited thereto. Those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this utility model; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be covered within the protection scope of this utility model.
Claims
1. A harmonic measurement device, characterized in that, include: The system comprises an MCU control unit, an analog sampling unit, a frequency conversion unit, and a pulse width modulation unit. The analog sampling unit is electrically connected to the MCU control unit, the frequency conversion unit, and the pulse width modulation unit, respectively. The frequency conversion unit is electrically connected to the pulse width modulation unit. The frequency conversion unit includes a phase-locked loop chip U5 and a binary frequency divider chip U6, which are electrically connected. The pulse width modulation unit includes D flip-flops U8 and U9 and a NAND gate U7. The D flip-flops U8 are electrically connected to the D flip-flops U9 and U7, respectively. The D flip-flops U9 are electrically connected to the NAND gate U7.