Memory and electronic equipment
By setting interface circuits on the memory chip and combining them with digital circuit design, the process migration challenge of three-dimensional stacked memory was solved, enabling faster iteration and higher storage performance.
Patent Information
- Application Number
- CN202520176198.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-27
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2035-01-27
AI Technical Summary
Existing 3D stacked memories face challenges in interface circuit design due to difficulties in process migration and high design complexity, which limits the speed of iterative updates.
By placing the interface circuitry on the memory chip instead of the logic chip and using a standard memory interface, process migration can be avoided. In conjunction with digital circuit design, some control circuitry can be removed to reduce area footprint.
It reduces design complexity and difficulty, increases the speed of architecture iteration, and does not significantly affect storage density and performance.
Smart Images
Figure CN223712431U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a chip technical field, specifically relates to a kind of memory and electronic equipment. BACKGROUND
[0002] A complete storage device can be divided into two main parts: interface circuit and other circuits that implement control, storage, computing and other non-interface functions. In traditional two-dimensional memory, since the interface circuit and other circuits are integrated on the same chip, the same manufacturing process is usually used. However, as the demand for storage performance of computing systems grows, traditional two-dimensional memory gradually encounters bottlenecks in storage density, data bandwidth and other performance. To improve these problems, three-dimensional stacked memory technology has emerged. This technology integrates different functional chips or structures by stacking multiple chips or structures in the vertical direction, improving the integration of memory and significantly improving storage performance.
[0003] According to the functional composition of the chip, there are two architectures of three-dimensional stacked memory: one is a three-dimensional stacked memory of all storage chips, such as 3D NAND Flash memory; the other is a hybrid stack of storage chips and logic chips, such as Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM). These hybrid stacked memories vertically connect storage chips and logic chips through advanced packaging technology, shorten the data transmission distance, and achieve higher internal bandwidth and lower latency of storage chips.
[0004] Although three-dimensional stacked memory technology brings significant performance improvement, it faces new challenges in the design of interface circuits. In existing solutions, for memory using hybrid stack architecture, the number of storage chips can be single or multiple, which are vertically connected through advanced packaging technology and communicate with the outside through the interface circuit located on the logic chip. However, storage chips and logic chips usually use different manufacturing processes, among which the logic chip process is often more advanced. Therefore, in order to meet the functional requirements of three-dimensional stacked memory, three-dimensional stacked memory with hybrid stack architecture needs to migrate the interface circuit originally located on the storage chip in the traditional memory. This means that the interface circuit needs to be redesigned and customized under the manufacturing process framework of the logic chip to ensure the performance and compatibility of the entire three-dimensional stacked memory system. This greatly increases the design complexity of such three-dimensional stacked memory Figure 1 )
[0005] In order to realize effective chip management, these storage chips are usually vertically stacked by using advanced packaging technology, and finally communicate with external systems through interface circuits on logic chips. Since storage chips and logic chips are often based on different manufacturing processes, we need to migrate the interface circuits originally integrated on the storage chips in the design of three-dimensional stacked memory.
[0006] The interface circuit is responsible for processing high-speed communication between the memory and the external system. In order to ensure the integrity and transmission efficiency of the signal, it usually contains complex analog circuits. Therefore, the circuit process migration of the interface is not code migration or simple circuit copying in the design process of similar digital circuits, but needs to redesign and customize circuits with the same function according to the characteristics of the interface circuit under the original storage chip process within the manufacturing process framework of the logic chip. This significantly increases the design difficulty and design complexity, and also limits the development speed of iterative updates of three-dimensional stacked memory. Figure 2
[0007] Therefore, it is necessary to improve the existing memory. Invention content
[0008] In view of the above problems, the utility model provides a kind of memory, including storage chip and logic chip, the storage chip with the logic chip uses the process packaging of three-dimensional packaging, the memory further include interface circuit, the interface circuit is used to realize the communication between the memory and external system, the interface circuit is set to the storage chip.
[0009] Optionally, the logic chip includes a storage chip control circuit, the storage chip control circuit is connected with the interface circuit, can send corresponding operation instruction based on the control instruction of external system, control the operation of the storage chip.
[0010] Optionally, the storage chip includes a plurality of storage circuits and a control circuit corresponding to each storage circuit; the storage chip control circuit includes a control logic circuit and a plurality of storage controllers corresponding to the storage circuit, the control logic circuit is configured to be connected with the interface circuit, receive the control instruction sent by the external system, and convert it into the operation instruction of the storage chip and send it to each storage controller; a plurality of storage controllers are connected in series and connected with the control logic circuit, each storage controller is connected with the corresponding control circuit through IO interface, can send operation instruction to the corresponding control circuit, and the control circuit can drive the corresponding storage circuit based on the operation instruction.
[0011] Optionally, the storage chip is a Flash storage chip, a DRAM storage chip, a SRAM storage chip, an MRAM chip or an RRAM storage chip.
[0012] Optionally, the storage chip control circuit part is disposed on the logic chip.
[0013] Optionally, the storage chip control circuit comprises a first control circuit and a second control circuit, the first control circuit is capable of being realized by digital circuit design and disposed on the logic chip, and the second control circuit is disposed on the storage chip.
[0014] Optionally, the first control circuit comprises a command parser and an address decoder.
[0015] Optionally, the second control circuit comprises a refresh controller and an error correction and checker.
[0016] Compared with the prior art three-dimensional stacked memory in which the interface circuit is disposed on the logic chip, the interface circuit is disposed on the storage chip in the utility model, which occupies part of the storage chip area. In order to eliminate the influence of the area occupation on the storage density, part of the control circuit disposed on the storage chip in the prior art is migrated to the logic chip in the form of digital flow. Therefore, although the storage chip adds the interface circuit, part of the control circuit is also removed synchronously, so that the storage chip area and the storage density and other indicators are not greatly affected.
[0017] In order to achieve the above-mentioned utility model purposes, the application provides a control method of a memory, the memory comprising a logic chip and a storage chip, comprising the steps of:
[0018] receiving a control instruction of an external system through the interface circuit disposed on the storage chip;
[0019] converting the control instruction into an operation instruction of the storage chip through the storage chip control circuit disposed on the logic chip; and
[0020] the storage chip executes the operation instruction.
[0021] In order to achieve the above-mentioned utility model purposes, the application provides an electronic device, which applies the memory described above.
[0022] In summary, compared with the implementation mode in which the interface circuit is usually disposed on the logic chip in the prior art, the memory provided by the application disposes the interface circuit on the storage chip. Since the interface circuit is a standard memory interface, it does not need process migration based on the design of the storage chip, can avoid the design complexity and design difficulty caused by process migration of the interface circuit, and greatly improves the architecture iteration speed. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 is a schematic diagram of a three-dimensional packaged memory architecture in the prior art.
[0024] Figure 2 is a schematic diagram of a process migration of a memory interface circuit from two-dimensional packaging to three-dimensional packaging in the prior art.
[0025] Figure 3 is a schematic diagram of a memory architecture provided in an embodiment of the present application.
[0026] Figure 4 is a schematic diagram of a memory architecture provided in an embodiment of the present application.
[0027] Figure 5 is a schematic diagram of a memory architecture provided in an embodiment of the present application.
[0028] Figure 6 is a schematic diagram of a data read-write flow of a memory provided in an embodiment of the present application.
[0029] Figure 7 is a schematic diagram of a step of a control method of a memory provided in an embodiment of the present application. DETAILED DESCRIPTION
[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.
[0031] As shown in FIG. 1, Figure 3 The present embodiment provides a memory, which includes a storage chip 100 and a logic chip 200 packaged in a three-dimensional packaging process, and further includes an interface circuit 300 for communication between the memory and an external system, the interface circuit 300 being disposed on the storage chip 100.
[0032] Compared with the implementation in the prior art in which the interface circuit is disposed on the logic chip 200, disposing the interface circuit 300 on the storage chip 100 can avoid the design complexity and difficulty caused by process migration of the interface circuit 300, since the interface circuit 300 is a standard memory interface and does not need process migration based on the design of the storage chip 100, and can greatly improve the architecture iteration speed.
[0033] Specifically, the interface circuit is generally a SerDes (Serialization / Deserialization) circuit, which is a high-speed serial / parallel and parallel / serial data conversion interface circuit. The implementation of the interface circuit needs to use an analog circuit process, including circuit design, circuit netlist simulation, layout design, parasitic parameter extraction and post-simulation, chip back-chip testing and other complex design and testing processes, in order to ensure the correctness of the function. This means that if the interface circuit is migrated from one process to another process, the above processes need to be reworked, which brings huge and complex workload and cannot guarantee reliability. The memory architecture provided by the embodiment sets the interface circuit on the storage chip, and does not need to perform process migration of the interface circuit from the storage chip process to the logic chip process, thereby greatly reducing the design complexity and difficulty of the three-dimensional stacked memory, and greatly improving the architecture iteration speed of such memory.
[0034] Optionally, the logic chip 200 includes a storage chip control circuit 210, which is connected with the interface circuit 300 and can issue corresponding operation instructions based on the control instructions sent by the external system to control the operation of the storage chip 100.
[0035] Optionally, as shown in Figure 4 The storage chip 100 includes a plurality of storage circuits 110 and a control circuit 120 corresponding to each storage circuit 110; the storage chip control circuit 210 includes a control logic circuit 211 and a plurality of storage controllers 212 corresponding to the storage circuits 110, the control logic circuit 211 is configured to be connected with the interface circuit 300, receive the control instructions sent by the external system, and convert them into operation instructions of the storage chip 100 and send them to each storage controller 212; the plurality of storage controllers 212 are connected in series and connected with the control logic circuit 211, each storage controller 212 is connected with the corresponding control circuit 120 through the IO package formed by the connection line between the IO interfaces respectively arranged on the storage chip 100 and the logic chip 200 and the interface, and can send the operation instructions to the corresponding control circuit 120, and the control circuit 120 can drive the corresponding storage circuit 110 based on the operation instructions.
[0036] Optionally, the logic chip 200 further includes a functional circuit 220, which can be a logic operation circuit and can perform addition, multiplication and other calculations.
[0037] Optionally, when there are multiple storage chips 100, they are stacked in a three-dimensional package above the logic circuit 200, and the upper storage chips 100 are connected with the bottom storage chips 100 through IO of the advanced packaging interface, and are controlled by the storage controller 212 of the logic chip 200. For example, when a certain storage controller 212 on the logic chip 200 is working, it simultaneously accesses the storage circuit 110 corresponding to the storage controller 212 on each storage chip 100.
[0038] Optionally, when there are multiple storage chips 100, all or at least part of the storage chips 100 are provided with the interface circuit 300 to communicate with the external system.
[0039] Optionally, as shown in the embodiment, the storage chip control circuit 210 is further defined as a first control circuit 213 and a second control circuit 214. The first control circuit 213 is a control circuit that can be realized by digital circuit design, and the second control circuit 214 is a control circuit other than the first control circuit 213. Further, the first control circuit 213 is arranged on the logic chip 200, and the second control circuit 214 is arranged on the storage chip 100. In this way, the circuit configuration and process are matched, and the influence of the interface circuit arranged on the storage chip on the area and storage density of the storage chip is effectively alleviated or even eliminated. Figure 5
[0040] The principle of the storage provided by the embodiment to realize the above technical effects is described in detail as follows: Taking a DRAM storage chip as an example, its control circuit usually includes a command parser, an address decoder, a refresh controller, an error correction and checker, etc. In the embodiment, if the storage chip is realized by DRAM, its command parser, address decoder, etc. can be realized on a more advanced logic chip through a digital design process. Compared with the control circuit realized by storage process, these control circuits realized on the logic chip have higher performance and faster decoding and decoding speed, and can be integrated into the first control circuit 213 described above. The refresh controller, error correction and checker are closely related to the storage circuit, so they are still arranged on the storage chip, and can be integrated into the second control circuit 214 described above. When the storage chip is realized by other storage devices, its control circuit can also be arranged on the logic chip or the storage chip according to the feasibility of the digital implementation process, the degree of contact with the storage circuit, etc.
[0041] Compared with the prior art of arranging the interface circuit on the three-dimensional stacked memory of the logic chip, the interface circuit is arranged on the storage chip in the embodiment, which occupies part of the storage chip area. In order to eliminate the influence of the area occupation on the storage density, part of the control circuit arranged on the storage chip in the prior art is migrated and arranged on the logic chip in the form of a digital flow in the embodiment. Therefore, although the storage chip adds the interface circuit, part of the control circuit is removed at the same time, so that the storage chip area and the storage density and other indicators will not be greatly affected.
[0042] Optionally, as shown in Figure 6 The working flow of the three-dimensional stacked memory architecture provided by the embodiment is as follows:
[0043] When the external system inputs a read data operation signal to the interface circuit of the storage chip, the interface circuit receives the related data and transmits the signal to the storage chip control circuit located on the logic chip. The storage chip control circuit analyzes and translates the signal into a storage chip read operation instruction and sends it to the storage chip. Then, the storage chip executes the operation according to the input instruction and operation information, reads the data to the interface circuit and outputs it.
[0044] Optionally, in the embodiment, the three-dimensional packaging of the memory applies TSV technology or Hybrid bonding technology for wiring.
[0045] Optionally, the interface circuit 300 arranged on the storage chip 100 is configured to receive any signal or combination of the following signals: address input signal, data input / output signal, word or byte selection input signal, hardware reset / sector protection unlock signal, output enable signal, command lane signal, address lane signal, Ready / Busy indication signal, differential clock signal, clock enable signal, chip select signal, row address strobe signal, column address strobe signal, write enable signal, data read / write clock signal, BANK address signal, data mask signal, termination resistance signal, calibration signal, command address signal, and data bus signal.
[0046] Optionally, the storage chip 100 is a Flash storage chip, a DRAM storage chip, an SRAM storage chip, an MRAM storage chip, or an RRAM storage chip.
[0047] Optionally, as shown in Figure 7 The embodiment provides a control method of a memory, the memory comprising a logic chip and a storage chip, and the control method comprises the following steps:
[0048] receiving a control instruction of an external system through the interface circuit arranged on the storage chip;
[0049] The control instruction is converted into an operation instruction of the storage chip by a storage chip control circuit arranged in the logic chip.
[0050] The storage chip executes the operation instruction.
[0051] Optionally, the embodiment further provides an electronic device, and the electronic device can be a computer by using the storage device.
[0052] The technical scheme of the utility model has been described in combination with the drawings. However, it is easy for those skilled in the art to understand that the protection scope of the utility model is obviously not limited to the above-mentioned specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without deviating from the principles of the utility model, and the technical schemes after the changes or replacements will all fall within the protection scope of the utility model.
Claims
1. A memory, comprising: The memory includes a storage chip and a logic chip, the storage chip and the logic chip are packaged by a three-dimensional packaging process, the memory further includes an interface circuit, the interface circuit is configured to realize communication between the memory and an external system, and the interface circuit is arranged on the storage chip.
2. The memory of claim 1, wherein, The logic chip includes a storage chip control circuit, the storage chip control circuit is connected with the interface circuit, and the storage chip control circuit is capable of sending corresponding operation instructions based on a control instruction of the external system to control operation of the storage chip.
3. The memory of claim 2, wherein, The storage chip includes a plurality of storage circuits and a control circuit corresponding to each of the storage circuits, the storage chip control circuit includes a control logic circuit and a plurality of storage controllers corresponding to the storage circuits, the control logic circuit is configured to be connected with the interface circuit, receive a control instruction sent by the external system, and convert the control instruction into operation instructions of the storage chip and send the operation instructions to each of the storage controllers, and each of the storage controllers is connected with the control logic circuit in series, each of the storage controllers is connected with the corresponding control circuit through an IO interface, and each of the storage controllers is capable of sending operation instructions to the corresponding control circuit, and the control circuit is capable of driving the corresponding storage circuit based on the operation instructions.
4. The memory of any one of claims 1-3, wherein, The storage chip is a Flash storage chip, a DRAM storage chip, an SRAM storage chip, an MRAM chip, or an RRAM storage chip.
5. The memory of claim 2 or 3, wherein, The control circuit is partially arranged on the logic chip.
6. The memory of claim 5, wherein, The control circuit includes a first control circuit and a second control circuit, the first control circuit is capable of being realized by digital circuit design and is arranged on the logic chip, and the second control circuit is arranged on the storage chip.
7. The memory of claim 6, wherein, The first control circuit includes a command parser and an address decoder.
8. The memory of claim 6, wherein, The second control circuit includes a refresh controller and an error correction and check device.
9. An electronic device, comprising: The memory is applied to any one of claims 1-8.