High-speed multichannel sampling circuit based on FPGA

Abstract

The utility model discloses an FPGA-based high-speed multichannel sampling circuit, which comprises a first ADC chip, a second ADC chip, a third ADC chip, an FPGA chip, a filtering and amplifying circuit, a CPU power supply module and a clock management module, the input end of the filtering and amplifying circuit 5 receives a signal to be filtered, the input end of the first ADC chip is electrically connected with the output end of the filtering and amplifying circuit, and the input end of the third ADC chip is electrically connected with the output end of the CPU power supply module. The output end of the first ADC chip, the output end of the second ADC chip, the output end of the third ADC chip and the output end of the CPU power module are electrically connected with the input end of the FPGA chip, the input end of the clock management module 7 receives input clock signals, and the output end of the clock management module 7 is electrically connected with the input ends of the first ADC chip 1, the second ADC chip 2, the third ADC chip 3 and the FPGA chip 4. According to the utility model, the technical problems that the requirements of hardware resources are obviously increased under the condition of high sampling rate of the existing circuit adopting the parallel sampling technology, the circuit design is more complicated, and the application range of the circuit is limited can be solved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to digital circuit technical field, more specifically, it relates to a kind of high-speed multi-channel sampling circuit based on FPGA. BACKGROUND

[0002] With the increasing popularity of electronic devices and the increasing demand for high-speed data processing, multi-channel high-speed sampling circuits have emerged. Multi-channel high-speed sampling circuits can collect multiple signals in parallel in a short time, which has important application value in modern communication, radar, medical imaging and other fields. This circuit can realize the synchronous sampling of different channel signals, improving the efficiency and accuracy of data acquisition. Through continuous research and development of high-speed sampling technology, designers can meet the increasingly complex signal processing requirements, thereby supporting large-scale data processing and real-time monitoring system requirements, and promoting technological progress in various fields.

[0003] The existing multi-channel high-speed sampling circuit mainly has three implementation methods, including parallel sampling technology, time division multiplexing technology and multi-point synchronous sampling technology: parallel sampling technology configures multiple independent sampling channels, so that each channel can collect input signals simultaneously, thereby significantly improving the sampling rate of the system. This method can effectively reduce the delay of signals when processing high-frequency signals or rapidly changing signals, ensuring efficient real-time data acquisition, which makes this technology particularly important in dynamic signal detection and high-speed signal analysis, and can meet the requirements of time accuracy; Time division multiplexing technology uses clock control to sample multiple signals sequentially in different time periods. This method significantly reduces hardware resource consumption by slicing signals in the time domain. Since it does not need to set up independent sampling devices for each signal, this method is cost-effective in a multi-signal environment, especially suitable for applications that need to process multiple signals and are sensitive to resource constraints; Multi-point synchronous sampling technology precisely controls multiple ADC chips to sample data at the same time, achieving high-precision synchronous acquisition. This method is particularly suitable for signal processing that requires high time consistency and phase accuracy.

[0004] However, the above three existing multi-channel high-speed sampling circuits have some non-negligible defects:

[0005] First, circuits using parallel sampling technology often require high power consumption and cost, especially in high sampling rate cases, the demand for hardware resources increases significantly, making circuit design more complex and limiting the application range of the circuit;

[0006] Second, circuits using parallel sampling technology may be disturbed by other channels when multiple ADC chips work in parallel, affecting signal quality;

[0007] Third, although the circuit using time division multiplexing technology can reduce the hardware cost, it is easy to cause sampling distortion when sampling the signal, which is particularly fatal in real-time monitoring and high-precision fields;

[0008] Fourth, the circuit of the multi-point synchronous sampling technology will certainly reduce the signal-to-noise ratio due to the jitter of the sampling clock. If the sampling clock produces jitter, the performance of the entire circuit will be poor, thereby causing the signal-to-noise ratio and the number of effective bits to deteriorate;

[0009] Fifth, the circuit of the multi-point synchronous sampling technology has multiple ADC chips, and requires multiple ADC chips to sample at the same time, so there may be time delay synchronization, thereby causing the sampling signals to be inconsistent. Practical new type content

[0010] In view of the above defects or improvement needs of the prior art, the utility model provides a kind of high-speed multi-channel sampling circuit based on FPGA, its purpose is to solve the technical problems that the circuit of existing parallel sampling technology needs higher power consumption and cost, especially in the case of high sampling rate, the demand of hardware resource increases significantly, lead to the design of circuit becomes more complex, and it will limit the application range of the circuit, and the technical problems that the circuit of existing time division multiplexing technology is easy to cause sampling distortion when sampling signal, and the technical problems that the circuit of existing multi-point synchronous sampling technology has multiple ADC chips, and requires multiple ADC chips to sample at the same time, so there may be time delay synchronization, thereby causing the sampling signals to be inconsistent.

[0011] To achieve the above purpose, according to one aspect of the utility model, a kind of high-speed multi-channel sampling circuit based on FPGA is provided, including first ADC chip, second ADC chip, third ADC chip, FPGA chip, filter amplification circuit, CPU power module and clock management module, the input end of filter amplification circuit receives the signal to be filtered and processed, the input end of first ADC chip is electrically connected with the output end of filter amplification circuit, the output end of first ADC chip and the output end of second ADC chip, third ADC chip and CPU power module are electrically connected with the input end of FPGA chip, the input end of clock management module receives input clock signal, the output end of clock management module is electrically connected with the input end of first ADC chip, second ADC chip, third ADC chip and FPGA chip.

[0012] Preferably, the first ADC chip, the second ADC chip and the third ADC chip all use the ADC chip of model AD7606.

[0013] Preferably, the FPGA chip adopts an FPGA chip with a model of XC7VX330T-3FFG1761C.

[0014] Preferably, the filter-amplification circuit comprises a first resistor, a second resistor, a first capacitor, a third resistor, a voltage transformer and an operational amplifier.

[0015] One end of the first resistor is connected with an analog ground wire signal, and the other end is electrically connected with the second resistor, the first capacitor and the non-inverting input terminal of the operational amplifier.

[0016] The inverting input terminal of the operational amplifier is electrically connected with the output terminal.

[0017] The output terminal of the operational amplifier is further electrically connected with the third resistor, the voltage transformer and the input terminal of the first ADC chip.

[0018] Preferably, the RC filter composed of the second resistor and the first capacitor filters the received signal to be filtered.

[0019] The operational amplifier amplifies the filtered signal.

[0020] Preferably, the resistance value of the first resistor is 1000 kΩ.

[0021] The resistance value of the second resistor is 10 kΩ, and the resistance value of the third resistor is 1 kΩ.

[0022] The capacitance value of the first capacitor is 0.01 μF.

[0023] The operational amplifier adopts an operational amplifier with a model of TLO64.

[0024] Preferably, the CPU power module adopts a dual-channel low-dropout power regulator with a model of TPS765D301.

[0025] Preferably, the clock management module adopts a clock management chip with a model of AD9517.

[0026] Overall, compared with the prior art, the above technical scheme conceived by the utility model can achieve the following beneficial effects:

[0027] (1) The utility model adopts the FPGA chip, the ADC chip, the CPU power module and the filter-amplification circuit, all of which are low-cost and low-power integrated components, thereby solving the technical problem that the circuit using the parallel sampling technology needs high power consumption and cost, especially in the case of high sampling rate, the demand for hardware resources significantly increases, which makes the circuit design more complex and limits the application range of the circuit.

[0028] (2)The utility model discloses a filter amplification circuit and ADC chip are connected, and its filter amplification circuit can effectively remove high frequency noise and interference signal, guarantee the quality of input signal. Especially low pass filter can delete high frequency interference, prevent its influence ADC's accuracy when sampling. Therefore can solve the technical problem that the circuit of adopting parallel sampling technique in the prior art can be interfered from other channels when multiple ADC chips work in parallel, and the quality of signal is influenced.

[0029] (3)The utility model discloses a FPGA chip and ADC chip are connected and controlled, can carry out signal sampling through the high speed operation and logic processing capacity of FPGA chip, thereby greatly reduce the distortion introduced in the sampling process, therefore can solve the technical problem that the circuit of adopting time division multiplexing technique in the prior art can reduce hardware cost, but it is easy to cause sampling distortion when signal sampling.

[0030] (4)The utility model discloses a clock management chip AD9517 of ADRON semiconductor technology limited, and it can realize 8 -way clock's simultaneous output, maximum for 1.6GHz, in addition, it still possesses many characteristics such as low phase noise, low jitter, can obviously improve the clock performance of ADC chip, therefore can solve the technical problem that the circuit of adopting multiple point synchronous sampling technique in the prior art will bring the reduction of signal -to -noise ratio because of the jitter of sampling clock. If the jitter of sampling clock is produced, the performance of whole circuit will be poor, thereby leading to the deterioration of signal -to -noise ratio and effective bit number parameter.

[0031] (5)The utility model discloses a clock management module and ADC chip are connected, and its clock management module can ensure that the input signal of ADC chip is balanced with the input signal of other channels, thereby can ensure the data consistency of multiple channels, therefore can solve the technical problem that the multiple point synchronous sampling technique in the prior art can exist time delay synchronization between multiple ADC chips, thereby leading to the inconsistency of sampling signal. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is the circuit diagram of the utility model's high -speed multichannel sampling circuit based on FPGA;

[0033] Figure 2 It is the circuit schematic diagram of filter amplification circuit in the utility model's high -speed multichannel sampling circuit;

[0034] Figure 3 It is the structure schematic diagram of ADC chip in the utility model's high -speed multichannel sampling circuit;

[0035] Figure 4 It is the circuit schematic diagram of CPU power module in the utility model's high -speed multichannel sampling circuit. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the utility model more clearly, the following will be further described in detail in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the utility model, and are not used to limit the utility model. In addition, the technical features involved in each embodiment of the utility model described below can be combined with each other as long as they do not conflict with each other.

[0037] As shown in Figure 1 The utility model provides a kind of high-speed multi-channel sampling circuit based on FPGA, including first ADC chip 1, second ADC chip 2, third ADC chip 3, FPGA chip 4, filter amplification circuit 5, CPU power module 6 and clock management module 7, the input of filter amplification circuit 5 receives the signal to be filtered and processed, the input of first ADC chip 1 is electrically connected with the output of filter amplification circuit 5, the output of first ADC chip 1 and the output of second ADC chip 2, third ADC chip 3 and CPU power module 6 are electrically connected with the input of FPGA chip 4, the input of clock management module 7 receives input clock signal, the output of clock management module 7 is electrically connected with the input of first ADC chip 1, second ADC chip 2, third ADC chip 3 and FPGA chip 4.

[0038] As shown in Figure 3 First ADC chip 1, second ADC chip 2 and third ADC chip 3 adopt the ADC chip of AD7606 of Yadian Semiconductor Technology Co., Ltd. and model.

[0039] FPGA chip 4 adopts the FPGA chip of XC7VX330T-3FFG1761C of Xilinx Co. and model.

[0040] As shown in Figure 2 Filter amplification circuit 5 includes first resistance R120, second resistance R152, first capacitor C117, third resistance R184, voltage transformer TV9 and operational amplifier TLO64.

[0041] RC filter formed by second resistance R152 and first capacitor C117 filters and processes the signal to be filtered and processed, and operational amplifier TLO64 amplifies the filtered signal.

[0042] One end of the first resistor R120 is connected with the analog ground signal AGND, and the other end is electrically connected with the second resistor R152, the first capacitor C117 and the non-inverting input terminal of the operational amplifier TLO64; the inverting input terminal of the operational amplifier TLO64 is electrically connected with the output terminal; and the output terminal of the operational amplifier TLO64 is further electrically connected with the third resistor R184, the voltage transformer TV9 and the input terminal of the first ADC chip 1.

[0043] The resistance value of the first resistor R120 is 1000kΩ, the resistance value of the second resistor R152 is 10kΩ, the resistance value of the third resistor R184 is 1kΩ, the capacitance value of the first capacitor C117 is 0.01μF, and the operational amplifier TLO64 is an operational amplifier with the model number TLO64 manufactured by Texas Instruments.

[0044] As shown in Figure 4 The CPU power module 6 is a two-way low-dropout power regulator with the model number TPS765D301 manufactured by Texas Instruments.

[0045] The clock management module 7 is a clock management chip with the model number AD9517 manufactured by Analog Devices.

[0046] The working principle of the utility model is as follows:

[0047] The sampling process of the multi-channel sampling circuit samples 18 signals through the input end of the filter amplification circuit 5, the input end of the second ADC chip 2 and the input end of the third ADC chip 3, wherein the signals requiring filtering are first input into the circuit through the input end of the filter amplification circuit 5, in the filter amplification circuit 5, the first resistor R120 is used to increase the input impedance of the input end of the filter amplification circuit 5 to avoid generating signal output load. At the same time, the first resistor R120 also helps to provide a DC bias point for the subsequent circuit, thereby ensuring that the operational amplifier TLO64 can process positive and negative signals without causing clipping. Then, the RC filter composed of the second resistor R152 and the first capacitor C117 in the filter amplification circuit 5 filters the received signals to remove interference signals, and then enters the operational amplifier TLO64 to amplify the signals. The third resistor R184 is usually used for output current limiting to prevent excessive output current from damaging the subsequent circuit, and at the same time adjusts the gain of the operational amplifier TLO64. The voltage transformer TV9 is used to protect the subsequent circuit from transient voltage or overvoltage impact. When the voltage exceeds the design specification, the diode of the voltage transformer TV9 will be turned on to guide the overvoltage to the ground to protect the sensitive elements. Finally, the signals after filtering and amplification are input into the first ADC chip 1 through the output end of the filter amplification circuit 5 for digital-to-analog conversion processing. The remaining information without filtering is input into the second ADC chip 2 and the third ADC chip 3 through the input end of the second ADC chip 2 and the input end of the third ADC chip 3 for direct digital-to-analog conversion processing. The signals after digital-to-analog conversion are input into the FPGA chip 4 through the output end of the first ADC chip 1, the output end of the second ADC chip 2 and the output end of the third ADC chip 3, and 18 signals are sampled. In this process, the input clock signal of a specific frequency is selected, enters the AD9517 clock management chip through the input end of the clock management module 7, is converted into a differential clock, and is output through the output end of the clock management module 7 to output 4 low-voltage positive electrode coupling logic clocks to the ADC chip 1, the ADC chip 2, the ADC chip 3 and the FPGA chip 4 for signal sampling. The output end of the CPU power supply module 6 is electrically connected with the input end of the FPGA chip 4 for continuous power supply. The multi-channel sampling can be realized by expanding the connection circuit to collect multiple signals.

[0048] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An FPGA-based high-speed multi-channel sampling circuit, comprising a first ADC chip, a second ADC chip, a third ADC chip, an FPGA chip, a filter-amplifier circuit, a CPU power module, and a clock management module, characterized in that: the input end of the filter-amplifier circuit receives a signal to be filtered; the output end of the filter-amplifier circuit is electrically connected to the input end of the first ADC chip; the output end of the first ADC chip and the output ends of the second ADC chip, the third ADC chip, and the CPU power module are electrically connected to the input end of the FPGA chip; the input end of the clock management module receives an input clock signal, and the output end of the clock management module is electrically connected to the input ends of the first ADC chip, the second ADC chip, the third ADC chip, and the FPGA chip.

2. The FPGA-based high-speed multi-channel sampling circuit of claim 1, wherein, The first ADC chip, the second ADC chip, and the third ADC chip all use an ADC chip of model AD7606.

3. The FPGA-based high-speed multi-channel sampling circuit of claim 1, wherein, The FPGA chip uses an FPGA chip of model XC7VX330T-3FFG1761C.

4. The FPGA-based high-speed multi-channel sampling circuit of claim 1, characterized in that: the filter-amplifier circuit comprises a first resistor, a second resistor, a first capacitor, a third resistor, a voltage transformer, and an operational amplifier; one end of the first resistor is connected to an analog ground signal, and the other end is electrically connected to the second resistor, the first capacitor, and the non-inverting input end of the operational amplifier; the inverting input end of the operational amplifier is electrically connected to the output end; the output end of the operational amplifier is also electrically connected to the third resistor, the voltage transformer, and the input end of the first ADC chip.

5. The FPGA-based high-speed multi-channel sampling circuit of claim 4, characterized in that: the RC filter composed of the second resistor and the first capacitor filters the received signal to be filtered; the operational amplifier amplifies the filtered signal.

6. The FPGA-based high-speed multi-channel sampling circuit of claim 5, characterized in that: the resistance value of the first resistor is 1000 kΩ; the resistance value of the second resistor is 10 kΩ; and the resistance value of the third resistor is 1 kΩ; the capacitance value of the first capacitor is 0.01 μF; the operational amplifier uses an operational amplifier of model TLO64.

7. The FPGA-based high-speed multi-channel sampling circuit of claim 6, wherein, The CPU power module uses a dual low-dropout power regulator of model TPS765D301.

8. The FPGA-based high-speed multi-channel sampling circuit of claim 7, wherein, The clock management module uses a clock management chip of model AD9517.

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