Sigma-Delta modulator capable of ensuring stability
By introducing a cascaded delay-integration module and an instability detector into the Sigma-Delta modulator, the stability problem of high-order SDMs is solved and the adaptive stability of the system is achieved by detecting and reducing the number of delay-integration module stages.
Patent Information
- Application Number
- CN202421164802.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-24
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2034-05-24
AI Technical Summary
Existing second-order and higher Sigma-Delta modulators have stability issues, especially linearity problems caused by multi-bit comparators and harmonic generation in the spectrum. Current technology cannot fully guarantee the stability of SDM.
Design a Sigma-Delta modulator comprising at least three cascaded delay-integral modules and an instability detector. The stability of the control loop is detected by the instability detector. If instability is detected, the number of stages of the effectively cascaded delay-integral modules is reduced until the system stabilizes.
It effectively solves the stability problem of second-order and higher-order SDMs, avoids system instability caused by external factors, and maintains the integrity of system functions.
Smart Images
Figure CN223713976U_ABST
Abstract
Description
[Technical Field]
[0001] This utility model relates to the field of circuit design technology, and in particular to a Sigma-Delta modulator (i.e., ΣΔ modulator) that can guarantee stability. [Background Technology]
[0002] Second-order and higher-order SDMs (Sigma-Delta modulators) are prone to instability. This instability may be due to defects in circuit design. It could also be caused by excessively large input signal amplitude, leading to saturation of the integrator output and attenuation of the comparator gain, thus causing a shift in the poles of the SDM's transfer function.
[0003] To address these stability issues, past technologies often involved:
[0004] 1. When designing, make the poles as close as possible to the center of the unit circle.
[0005] 2. Alternatively, a multi-bit comparator can be used, because multi-bit comparators have more stable gain and less quantization noise, which reduces the risk of integrator saturation and comparator gain loss. As a result, the poles are more fixed, and the system is more stable.
[0006] However, neither of the above methods can completely guarantee the stability of SDM, especially the second one. Multi-bit SDM often generates a large number of harmonics in the spectrum due to linearity problems caused by mismatch.
[0007] Therefore, it is necessary to propose a new technical solution to address the above problems. [Utility Model Content]
[0008] One of the objectives of this invention is to provide a Sigma-Delta modulator that can guarantee stability, which can solve the stability problem of second-order and higher-order SDMs.
[0009] According to one aspect of the present invention, a Sigma-Delta modulator is provided, comprising: a quantizer; at least three cascaded delay integration modules, wherein the input terminal of the first delay integration module receives an input signal, the output terminal of the last delay integration module is connected to the input terminal of the quantizer, and in two adjacent delay integration modules, the output terminal of the preceding delay integration module is connected to the input terminal of the following delay integration module; and an instability detector connected to the input terminal of the quantizer, which determines whether the control loop of the Sigma-Delta modulator is stable based on the input signal of the quantizer, and if unstable, reduces the number of stages of the effectively cascaded delay integration modules.
[0010] Compared with existing technologies, this invention can solve the stability problem of second-order and higher-order SDMs. [Attached Image Description]
[0011] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Among them:
[0012] Figure 1 This is a circuit diagram of a Sigma-Delta modulator in one embodiment of the present invention;
[0013] Figure 2 In one embodiment of this utility model, as Figure 1 The circuit diagram of the unstable detector is shown.
[0014] Figure 3 In one embodiment of this utility model, as Figure 1 The circuit diagram shown is of the Sigma-Delta modulator after it has been reduced from 3rd order to 2nd order.
Detailed Implementation Methods
[0015] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0016] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, terms such as coupling, connection, linking, and interconnection used herein to indicate electrical connection mean direct or indirect connection. For example, A being connected to B includes both a direct electrical connection between A and B and a connection between A and B via electrical components or circuits.
[0017] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "back", "positive", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0018] Please refer to Figure 1 As shown, it is a circuit diagram of the Sigma-Delta modulator in one embodiment of the present invention. Figure 1 The Sigma-Delta modulator shown is a 3rd-order SDM, comprising a quantizer 110, an unstable detector 120, and cascaded first delay integration modules 130, second delay integration modules 140, and third delay integration modules 150. The input of the first delay integration module 130 receives the input signal Vin; the output of the first delay integration module 130 is connected to the input of the second delay integration module 140; the output of the second delay integration module 140 is connected to the input of the third delay integration module 150; and the output of the third delay integration module 150 is connected to the input of the quantizer 110. An instability detector 120 is connected to the input of quantizer 110. Based on the input signal of the quantizer, it determines whether the control loop of the Sigma-Delta modulator (SDM) is stable. If unstable, it reduces the order (or number of stages) of the effectively cascaded delay integration modules until the control loop is stable or the order of the effectively cascaded delay integration modules becomes 1. If stable, it maintains the number of stages of the cascaded delay integration modules. The quantizer 110 outputs a bitstream signal through its output. It is important to note that the order of the effectively cascaded delay integration modules is equal to the order of the SDM.
[0019] exist Figure 1 In the Sigma-Delta modulator (SDM) shown, there can be 4, 5 or more cascaded delay integration modules, that is, there are at least 3 cascaded delay integration modules. The input terminal of the first delay integration module receives the input signal Vin, and the output terminal of the last delay integration module is connected to the input terminal of the quantizer 110. In two adjacent delay integration modules, the output terminal of the previous delay integration module is connected to the input terminal of the subsequent delay integration module.
[0020] In one embodiment of this invention, the number of stages of the effectively cascaded delay integration modules is maximized during Sigma-Delta modulator initialization; or the number of stages of the effectively cascaded delay integration modules is determined as needed during Sigma-Delta modulator initialization.
[0021] exist Figure 1 In the illustrated embodiment, the instability detector 120 detects whether the differential amplitude of the input signal of the quantizer 110 exceeds a predetermined amplitude range. If the differential amplitude of the input signal of the quantizer 110 exceeds the predetermined amplitude range and the duration exceeds a predetermined duration, the control loop of the SDM is considered unstable; otherwise, the control loop of the SDM is considered unstable.
[0022] exist Figure 1 and Figure 3 In the specific embodiment shown, each delay integration module includes a subtractor 131 and a delay integrator 132. One end of the subtractor is connected to the input of delay integration modules 130, 140, and 150, and the other end of the subtractor is connected to the output of quantizer 110, Bitstream_out. The output of the subtractor is connected to the input of delay integrator 132. The output of each delay integrator 132 serves as the output of delay integration modules 130, 140, and 150.
[0023] It is important to note that Figure 1 One of the signal lines actually includes two differential signal lines. For simplicity, Figure 1 Only one is shown in the diagram. For example, the input signal Vin includes a first differential input signal and a second differential input signal, and the input terminals of each delay integrator include a positive phase input terminal and a negative phase input terminal (i.e., two differential input terminals), etc. Such simplification is well known to those skilled in the art and will not be elaborated here.
[0024] Please refer to Figure 2 As shown, this is one embodiment of the present invention. Figure 1 The circuit diagram of the unstable detector is shown. Figure 2 The unstable detector shown includes a differential comparator 122 and an output logic circuit 124.
[0025] Differential comparator 122 is a 4-input comparator. Two input terminals of differential comparator 122 are connected to two differential input signals inp and inn in the input signals of quantizer 110, respectively. The other two input terminals of differential comparator 122 are connected to the highest amplitude threshold (e.g., the highest amplitude threshold is Vdd-0.2) and the lowest amplitude threshold (e.g., the lowest amplitude threshold is 0.2) of a predetermined amplitude range, respectively. If the difference between the two differential input signals inp and inn is greater than the highest amplitude threshold (e.g., Vdd-0.2) or less than the lowest amplitude threshold (e.g., 0.2), the output terminal Comp_out of differential comparator 122 outputs an unstable comparison signal; otherwise, the output represents a stable comparison signal.
[0026] The input terminal of the output logic circuit 124 is connected to the output terminal Comp_out of the differential comparator 122. The output logic circuit 124 receives the comparison signal output by the differential comparator 122, and when the comparison signal is unstable and continues for more than a predetermined time, it outputs an unstable detection signal through its output terminal detector_out; otherwise, it outputs a stable detection signal.
[0027] exist Figure 2 In the illustrated embodiment, the output logic circuit 124 includes a logic unit 1242 and cascaded first D flip-flops (DFFs) 1243, second D flip-flops 1244, third D flip-flops 1245, and fourth D flip-flops 1246. The input of the first D flip-flop 1243 is connected to the output of the differential comparator 122 (Comp_out); the output (Q) of the first D flip-flop 1243 is connected to the input of the second D flip-flop 1244; the output (Q) of the second D flip-flop 1244 is connected to the input of the third D flip-flop 1245; the output (Q) of the third D flip-flop 1245 is connected to the input of the fourth D flip-flop 1246; the output of the fourth D flip-flop 1246 is connected to the first input of the logic unit 1242; the second input of the logic unit 1242 is connected to the output (Comp_out) of the differential comparator 122; and the output of the logic unit 1242 is connected to the output (detector_out) of the unstable detector 120. In this configuration, the clock inputs of the first D flip-flop 1243, the second D flip-flop 1244, the third D flip-flop 1245, and the fourth D flip-flop 1246 are all connected to the clock signal CLK. Figure 2 In the specific embodiment shown, logic unit 1242 is an AND gate.
[0028] exist Figure 2In the unstable detector shown, there can be 2, 3, 5 or more cascaded D flip-flops, that is, multiple cascaded D flip-flops. The input of the first D flip-flop is connected to the output Comp_out of the differential comparator 122; the output of the last D flip-flop is connected to the first input of the logic unit 1242; in two adjacent D flip-flops, the output Q of the preceding D flip-flop is connected to the input of the following D flip-flop; the clock input of each D flip-flop is connected to the clock signal CLK; the second input of the logic unit 1242 is connected to the output Comp_out of the differential comparator 122; and the output of the logic unit 1242 is connected to the output detector_out of the unstable detector 120.
[0029] For ease of understanding, the following is based on Figure 2 Detailed introduction Figure 1 The working principle of the Sigma-Delta modulator shown.
[0030] exist Figure 1 In the specific embodiment shown, during the initialization of the Sigma-Delta modulator, the number of stages of the effectively cascaded delay integration modules is the highest level of 3, that is, the cascaded first delay integration module 130, second delay integration module 140 and third delay integration module 150 are connected between the input signal Vin and the input terminal of the quantizer 110.
[0031] When the Sigma-Delta modulator in this invention is a 3rd order (or 3rd stage) Sigma-Delta modulator (e.g.) Figure 1 When the differential output amplitude of the third delay integration module 150 (i.e., the difference between the two differential input signals inp and inn in the input signal of the quantizer 110) is greater than Vdd – 0.2 (Vdd is the power supply voltage value, the highest amplitude threshold) or less than 0.2 (the lowest amplitude threshold), the output terminal Comp_out of the differential comparator 122 will output state 1 (which represents an unstable comparison signal). To avoid misjudgment, four D flip-flops 1243, 1244, 1245, and 1246 are used to determine the duration of state 1. If the duration of state 1 is greater than four CLK cycles (four CLK cycles is the predetermined duration), then the final output logic circuit 124 will output state 1 (which represents an unstable detection signal). At this time, the Sigma-Delta modulator will be downgraded by one order, that is, the number of stages of the effectively cascaded delay integration modules will be reduced by 1. And the output terminal detector_out of the unstable detector 120 will be set to a flag bit to tell the system that the SDM has been downgraded and is in a second-order state. Please refer to Figure 3 As shown, this is one embodiment of the present invention. Figure 1The diagram shows the circuit after the Sigma-Delta modulator is reduced from a 3rd-order (i.e., 3rd) SDM to a 2nd-order (i.e., 2nd) SDM. Specifically, by directly connecting the input terminal of the third delay integration module 150 (which can be called the target delay integration module at this time) to the output terminal of the third delay integration module 150 through switch S1, the third delay integration module 150 is no longer cascaded with the first delay integration module 130 and the second delay integration module 140, thereby reducing the number of stages of the effectively cascaded delay integration modules from 3 to 2. At this time, the third delay integration module 150 is not effectively cascaded.
[0032] When the Sigma-Delta modulator in this utility model is a 3rd order Sigma-Delta modulator (e.g., Figure 1 When the differential output amplitude of the third delay integration module 150 (i.e., the difference between the two differential input signals inp and inn in the input signal of the quantizer 110) is between Vdd – 0.2 and 0.2, the output terminal Comp_out of the differential comparator 122 will output state 0 (which represents a stable comparison signal), and the final output logic circuit 124 will output state 0 (which represents a stable detection signal), so the Sigma-Delta modulator will maintain the current order.
[0033] Similarly, when the Sigma-Delta modulator in this invention is a second-order Sigma-Delta modulator (such as...), Figure 3 When the differential output amplitude of the second delay integration module 140 (i.e., the difference between the two differential input signals inp and inn in the input signal of the quantizer 110) is greater than Vdd – 0.2 or less than 0.2, the output terminal Comp_out of the differential comparator 122 will output state 1 (which indicates an unstable comparison signal). If this state 1 is maintained for more than 4 CLK cycles (4 CLK cycles is the predetermined duration), then the final output logic circuit 124 will output state 1 (which indicates an unstable detection signal). At this time, the Sigma-Delta modulator will be downgraded by one order, that is, the number of stages of the effectively cascaded delay integration modules will be reduced by 1. And the output terminal detector_out of the unstable detector 120 will be set to a flag bit to tell the system that the SDM has been downgraded and is in a first-order state. Specifically, by using switch S2, the input terminal of the second delay integration module 140 (which can be called the target delay integration module) is directly connected to the output terminal of the second delay integration module 140, so that the second delay integration module 140 is no longer cascaded with the first delay integration module 130, thereby reducing the order of the effectively cascaded delay integration modules from 2nd order to 1st order. At this time, the second and third delay integration modules 140 and 150 are not effectively cascaded.
[0034] When the Sigma-Delta modulator in this utility model is a second-order Sigma-Delta modulator (such as...) Figure 3 When the differential output amplitude of the second delay integration module 140 (i.e., the difference between the two differential input signals inp and inn in the input signal of the quantizer 110) is between Vdd – 0.2 and 0.2, the output terminal Comp_out of the differential comparator 122 will output state 0 (which represents a stable comparison signal), and the final output logic circuit 124 will output state 0 (which represents a stable detection signal), so the Sigma-Delta modulator will maintain the current order.
[0035] In summary, if the instability detector 120 detects instability in the SDM's control loop, it reduces the order of the effectively cascaded delay integration modules by 1. This is achieved by directly connecting the input and output of the target delay integration module, preventing it from being cascaded with other delay integration modules, thus reducing the order of the effectively cascaded delay integration modules by 1. The target delay integration module is one of the cascaded delay integration modules; for example, it could be the second or third delay integration module. This allows the higher-order SDM to automatically downgrade its order after the entire system becomes unstable due to external factors, preventing the SDM from completely losing its functionality.
[0036] It is important to note that, since the target delayed integral module has two input terminals (one positive and one negative, i.e., two differential input terminals) and two output terminals (one positive and one negative, i.e., two differential output terminals), when directly connecting the input terminals of the target delayed integral module to the output terminals, the positive input terminal of the target delayed integral module should be directly connected to the negative output terminal of the target delayed integral module, and the negative input terminal should be directly connected to the positive output terminal of the target delayed integral module. This ensures that the entire system can form negative feedback. Similarly, Figure 1 and 3 Each switch S1, S2 in the system actually includes two switch units.
[0037] exist Figure 3 In the illustrated embodiment, the target delayed integration module is the third delayed integration module 150. When the input terminal of the third delayed integration module 150 is directly connected to the output terminal of the third delayed integration module 150, it means that the positive phase input terminal of the third delayed integration module 150 is directly connected to the negative phase output terminal of the third delayed integration module 150, and the negative phase input terminal of the third delayed integration module 150 is directly connected to the positive phase output terminal of the third delayed integration module 150.
[0038] In summary, this invention provides a Sigma-Delta modulator, comprising: a quantizer 110; at least three cascaded delay-integration modules 130, 140, and 150, wherein the input terminal of the first delay-integration module 130 receives the input signal Vin, the output terminal of the last delay-integration module is connected to the input terminal of the quantizer 110, and in adjacent delay-integration modules, the output terminal of the preceding delay-integration module is connected to the input terminal of the following delay-integration module; and an instability detector 120, which detects whether the control loop of the SDM is stable based on the input signal of the quantizer 110. If unstable, the number of stages of the effectively cascaded delay-integration modules is reduced until the control loop of the SDM is stable or the number of stages of the effectively cascaded delay-integration modules becomes 1. This solves the stability problem of 3rd-order and higher-order SDMs.
[0039] In this utility model, words such as “connection,” “linked,” “connected,” and “joined” that indicate electrical connection, unless otherwise specified, indicate direct or indirect electrical connection.
[0040] The above description is only a preferred embodiment of the present utility model. The protection scope of the present utility model is not limited to the above embodiments. Any equivalent modifications or changes made by those skilled in the art based on the disclosure of the present utility model should be included in the protection scope recorded in the claims.
Claims
1. A Sigma-Delta modulator with guaranteed stability, characterized in that, It includes: Quantizer; At least three cascaded delay integration modules, wherein the input terminal of the first delay integration module receives the input signal, the output terminal of the last delay integration module is connected to the input terminal of the quantizer, and in two adjacent delay integration modules, the output terminal of the preceding delay integration module is connected to the input terminal of the following delay integration module. An instability detector, connected to the input of the quantizer, determines whether the control loop of the Sigma-Delta modulator is stable based on the input signal of the quantizer. If it is unstable, the number of stages of the effectively cascaded delay integration module is reduced.
2. The Sigma-Delta modulator according to claim 1, characterized in that, If the unstable detector determines that the control loop is stable based on the input signal of the quantizer, then the number of stages of the effectively cascaded delay integration module is maintained. If the unstable detector determines that the control loop is unstable, the number of stages of the effectively cascaded delay integration modules is reduced until the control loop is stable or the number of stages of the effectively cascaded delay integration modules becomes 1.
3. The Sigma-Delta modulator according to claim 1, characterized in that, If the instability detector detects instability in the control loop, the number of stages in the effectively cascaded delay integration module is reduced by 1: By directly connecting the input terminal of the target delay integration module to the output terminal of the target delay integration module, the target delay integration module is no longer cascaded with other delay integration modules, thereby reducing the number of stages of the effectively cascaded delay integration modules by 1. The target delay integration module is one of the cascaded delay integration modules.
4. The Sigma-Delta modulator according to claim 3, characterized in that, When the input terminal of the target delayed integration module is directly connected to the output terminal of the target delayed integration module, the positive phase input terminal of the target delayed integration module is directly connected to the negative phase output terminal of the target delayed integration module, and the negative phase input terminal of the target delayed integration module is directly connected to the positive phase output terminal of the target delayed integration module.
5. The Sigma-Delta modulator according to claim 1, characterized in that, Each delayed integration module includes a subtractor and a delayed integrator. One end of the subtractor serves as the input of the delay integrator module, the other end of the subtractor is connected to the output of the quantizer, and the output of the subtractor is connected to the input of the delay integrator. The output of the delay integrator serves as the output of the delay integration module.