Processor pin array
By using an equilateral triangle arrangement and partitioned layout of the processor pin array, the problems of high density and signal crosstalk in traditional designs are solved, achieving efficient pin arrangement and improved signal quality.
Patent Information
- Application Number
- CN202423235407.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2034-12-26
AI Technical Summary
Traditional processor pin arrangement designs cannot simultaneously achieve high density and good signal integrity, especially with the continuous increase in the number of I/Os and package size, resulting in serious signal crosstalk problems.
The processor pin array is designed using an equilateral triangle arrangement, with equal spacing between pins in each row and staggered pins in adjacent rows to form a 60° angle. The spacing is determined according to the motherboard manufacturing process and wiring method. Different types of pins are arranged in zones, including DDR signals, GND and power pins. Crosstalk is reduced by differential pair interleaving and GND isolation.
This achieves high-density pin arrangement for the processor, reduces signal crosstalk, improves signal quality, and optimizes package area utilization.
Smart Images
Figure CN223714258U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the chip layout and design field especially relates to a processor pin array. BACKGROUND
[0002] Semiconductor chips need to be packaged. For chips with relatively complex functions, especially processors, common packaging forms include ball grid array BGA, lattice array LGA, and pin grid array PGA. Regardless of the packaging form, the arrangement of pins needs to be considered during design. Different processors have different I / O quantities, rates, and packaging sizes, and thus have different pin arrangement methods. With the development of processor performance and specifications, the number of processor I / O pins is increasing, and the number of I / O interfaces is also increasing. Traditional pin arrangement design cannot simultaneously consider maximizing pin arrangement density and reducing crosstalk between pins to improve signal integrity (SI) performance. SUMMARY
[0003] Therefore, the utility model provides a processor pin array, which aims to realize high-density pins while ensuring signal quality.
[0004] The processor pin array provided by the utility model comprises multiple rows of pins in the horizontal direction, the distance between pins in each row of pins is equal, the distance between each pin and the closest pin in the adjacent row is equal to the distance, and the adjacent two rows of pins are arranged in a staggered manner, so that the included angle between the straight line passing through each pin and the closest pin in the adjacent row and the horizontal direction is 60°.
[0005] Preferably, the pin array is provided with DDR signal pins, high-speed differential signal pins, GND pins, and power supply pins.
[0006] Preferably, the distance is determined based on the manufacturing process of the mainboard and the wire outlet mode on the mainboard.
[0007] Preferably, the distance is determined according to the solder ball radius, the wire-to-pad distance, the wire distance, and the wire thickness.
[0008] Preferably, the distance is:
[0009] D=R1*2+d1*2+d2+w*2;
[0010] wherein D is the distance, R1 is the solder ball radius, d1 is the wire-to-pad distance, d2 is the wire distance, and w is the wire thickness.
[0011] Preferably, the processor pin array has a first sub-region and a second sub-region for placing DDR signal pins, GND pins and power supply pins, wherein the DDR signals in the first sub-region and the second sub-region are respectively fanned out to the left or to the right on the mainboard, and each DDR channel occupies a separate trace layer.
[0012] Preferably, the DDR signals include data signals and command and address signals, wherein the data signals are composed of multiple bytes, and each byte contains 8 DQ signals and two groups of DQS differential signals.
[0013] Preferably, each DQ signal in the same byte is adjacent to only one DQ signal, the DQ signals in the same byte are adjacent to the differential pairs of DQS signals, the adjacent DQS+ and DQS- signals are simultaneously adjacent to the DQ signals in the same byte, the different byte signals in the same DDR channel are adjacent in the vertical direction, the different bytes in the same DDR channel are isolated by GND, and the bytes of different DDR channels are adjacent in the horizontal direction.
[0014] Preferably, the processor pin array has a third sub-region and a fourth sub-region for placing high-speed differential signal pins, GND pins and power supply pins, the high-speed differential signals are routed in the inner layer and are respectively fanned out upward or downward in the third sub-region and the fourth sub-region, and the high-speed differential signals are high-speed serial computer expansion bus standards PCIE.
[0015] Preferably, the differential pairs of the same row of the high-speed differential signal pins are adjacent in a diagonal and horizontal staggered manner, the differential pairs of different rows are staggered by one differential pair position, each signal of the differential pair is adjacent to two power supplies, and the power supplies are of the same type.
[0016] Preferably, the processor pin array has a fifth sub-region for placing power supply pins and GND pins used for backflow, and the power supply pins and the GND pins are respectively routed in the power supply layer and the GND layer on the mainboard.
[0017] Preferably, the processor pin array has a sixth sub-region and a seventh sub-region for placing low-speed signal pins, and the low-speed signals are routed in the surface layer and are respectively fanned out upward or downward on the mainboard.
[0018] It can be seen that the processor pin array provided by the utility model realizes pin arrangement in the Haiguang processor, efficiently utilizes pins and packaging area, and ensures signal quality. BRIEF DESCRIPTION OF DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and all of the other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.
[0020] Figure 1a And Figure 1b It is a global and local schematic diagram of the processor pin array according to the present application.
[0021] Figure 2 It is a pin center distance schematic diagram according to the present application.
[0022] Figure 3 It is a pin function partition schematic diagram according to the present application.
[0023] Figure 4 It is a DDR data signal pin arrangement mode schematic diagram according to the present application.
[0024] Figure 5 It is a PCIE signal pin arrangement mode schematic diagram according to the present application. DETAILED DESCRIPTION
[0025] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the drawings in the specification and specific embodiments.
[0026] It should be clear that the described embodiments are only some of the embodiments of the present application, not all the embodiments. In order to more clearly illustrate the present application, numerous technical details are described in the following specific embodiments. Those skilled in the art should understand that the present application can be implemented without some of the details. In addition, in order to highlight the invention of the present application, some methods, means, components and their applications known to those skilled in the art are not described in detail, but this does not affect the implementation of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application.
[0027] As described above, different processor pin functions and quantities are different, and their arrangement is also different. In order to realize the arrangement of processor pins and at the same time improve the pin density and reduce signal crosstalk, the present application provides a processor pin array. The present application designs a pin arrangement mode for Hikvision processor, which meets the requirements of processor pin arrangement density and signal rate.
[0028] Figure 1a The partial schematic diagram of the processor pin array is shown in the figure. Figure 1b The pin array includes multiple rows of pins in horizontal direction, the distance between every two adjacent pins is the same, the distance between adjacent pins in each row is equal, the distance from each pin to the nearest pin in the adjacent row is equal to the distance between the two adjacent pins in the row, so that any three pins adjacent to each other form an equilateral triangle, and one side of the equilateral triangle is in horizontal direction.
[0029] The length of the side of the equilateral triangle is denoted as D, the horizontal center distance between the pins is D, and the vertical center distance is D*sin60=0.866*D. In the preferred embodiment, the value of D is selected according to the manufacturing process of the mainboard and the wire-out mode on the mainboard.
[0030] In the optional embodiment, based on the equilateral triangle, slight adjustment can be made in actual design. For example, if the wire design in vertical direction and the wire design in horizontal direction are not equal in line width and line distance, it can also not be an equilateral triangle.
[0031] Figure 2 In the figure, the circle represents the solder ball on the mainboard connected with the CPU, and the gray long strip is the PCB wiring between the two solder balls on the mainboard, generally two, so that:
[0032] D=R1*2+d1*2+d2+w*2;
[0033] Wherein R1 is the solder ball radius, d1 is the distance between the wire and the pad, d2 is the wire spacing, and w is the wire thickness.
[0034] According to the different functions of the pins, the pin array can be divided into Figure 3 7 subareas as shown in the figure. The first and second subareas are used to place the DDR signal pins, the GND pins for signal isolation and reference, and the power supply pins, wherein the DDR signals in the first and second subareas are respectively fanned out to the left or right on the mainboard, and each DDR channel occupies a separate wire layer, so that good isolation can be achieved between the DDR channels and between the DDR and other signals, and they do not interfere with each other.
[0035] The sixth and seventh subareas are used to place low-speed signal pins, a small amount of GND pins for signal reference, and a small amount of power supply pins, and the low-speed signals on the mainboard are routed on the surface layer and fanned out upward or downward.
[0036] The third and fourth subareas are used to place high-speed serial computer expansion bus standard PCIE and other high-speed differential signal pins, GND pins for signal isolation and reference, and power supply pins, and the high-speed differential signals on the mainboard are routed on the inner layer and respectively fanned out upward or downward, without being disturbed by external low-speed signals.
[0037] Partition 5 is used to place power supply pins and GND pins for backflow. The power supply and GND on the mainboard are routed on the dedicated power supply layer and GND layer respectively.
[0038] The high-speed interfaces of the Haiguang processor are various, and the single-ended signal with the highest rate is the DDR signal, and the differential signal with the highest rate is, for example, the PCIE. In the above description, the power supply pins are arranged in the partitions 1, 2, 3, and 4 where the high-speed signals such as the DDR signal and the PCIE signal are located, so as to improve the pin utilization rate. In an optional implementation, if all the power supply pins can be placed in the partition 5, the power supply pins do not need to be placed in the high-speed signal area.
[0039] For the arrangement mode of the DDR signal, the DDR signal can be divided into data (data) signals and command / address (command / address) signals according to functions, wherein the data is composed of multiple bytes, and each byte includes eight data signals (DQ) and two groups of data trigger signals (DQS) differential signals.
[0040] Figure 4 For the arrangement mode of the DDR data signal, 1+ / 1-, 2+ / 2-, and 3+ / 3- in the figure are different DQS differential pairs in different bytes, 1d, 2d, and 3d are DQ signals in different bytes, VCC is a power supply, and the unmarked pins are GND. Two groups of 1+ / 1- and eight 1d constitute a byte byte1, two groups of 2+ / 2- and eight 2d constitute a byte byte2, and two groups of 3+ / 3- and eight 3d constitute a byte byte3. Byte1 and byte2 are different bytes of the same DDR channel, and byte3 is a byte of another DDR channel.
[0041] The DDR data arrangement mode has the following characteristics:
[0042] Each DQ signal in the same byte is adjacent to only one DQ, which can minimize the interference between the DQs;
[0043] When the DQ signals in the same byte are adjacent to the DQS differential pairs, the + and - of the DQS differential pairs are adjacent, so that the interference of the DQS+ and DQS- signals on the DQ can be largely offset, and the interference of the DQ on the DQS is common-mode interference, which can be eliminated at the receiving end of the differential signal;
[0044] Different byte signals of the same DDR channel are adjacent in the vertical direction, which is consistent with the relationship between the bytes on the memory slot, and facilitates the routing of the mainboard;
[0045] The GND isolation between different bytes of the same DDR channel can reduce the crosstalk between the bytes;
[0046] The bytes of different DDR channels are adjacent in the horizontal direction, so that the different channels located in different layers can save the PCB wiring space;
[0047] The GND isolation between different DDR channels can reduce the crosstalk between the channels;
[0048] The bytes of different DDR channels are staggered by three rows in the vertical direction, so that the pin utilization rate can be maximized;
[0049] For the arrangement mode of the PCIE signal pin, for example, Figure 5 A partial view of the arrangement of the PCIE high-speed differential signal pin is shown, wherein 1+, 1- are a pair of differential pairs, 2+, 2- are a pair of differential pairs, and so on.
[0050] For convenience of description, the differential pairs 1, 2, 3, 4 and 5 can be considered to be located in the same row, and the differential pairs 6, 7, 8 and 9 are located in another row.
[0051] The arrangement mode has the following characteristics:
[0052] Firstly, the differential pairs in the same row are staggered and adjacent in the diagonal direction (such as the differential pair 1) and the horizontal direction (such as the differential pair 2), so that the interference of 1+, 1- to 2+ can be partially offset, thereby reducing the interference between the adjacent differential pairs in the same row.
[0053] Secondly, the differential pairs between different rows are staggered by one differential pair position, for example, 1+, 1- are in the diagonal direction, and the adjacent row below is 6+, 6- in the horizontal direction, so that the pin utilization rate can be improved while the interference between the rows is reduced.
[0054] Thirdly, the number of adjacent power supplies for each signal of the differential pair is two, and the power supply types are the same, so that the interference of the power supply to each differential pair is common-mode interference, which can be well eliminated.
[0055] It can be seen that the above technical scheme of the utility model provides a processor pin array, realizes the pin arrangement in the Haiguang processor, efficiently utilizes the pin and the packaging area, and ensures the signal quality.
[0056] The above describes a plurality of embodiment schemes provided by the utility model, and the optional modes introduced in each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending a plurality of possible embodiment schemes, which can be considered as the embodiment schemes disclosed and disclosed by the utility model embodiments.
[0057] Although the utility model discloses the above, but the utility model is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the utility model, can make various changes and modifications, therefore the protection scope of the utility model should be limited to the range defined by the claims.
Claims
1. A processor pin array, comprising: It includes multiple rows of pins in the horizontal direction, with equal spacing between pins in each row. The distance from each pin to the nearest pin in the adjacent row is equal to the spacing. Adjacent rows of pins are staggered, such that the angle between the straight line passing through each pin to the nearest pin in the adjacent row and the horizontal direction is 60°.
2. The processor pin array according to claim 1, characterized in that, The pin array is provided with DDR signal pins, high-speed differential signal pins, GND pins, and power supply pins.
3. The processor pin array according to claim 1, characterized in that, The spacing value is based on the motherboard's manufacturing process and the wiring configuration on the motherboard.
4. The processor pin array according to claim 1, characterized in that, The spacing is determined based on the solder ball radius, the distance between the trace and the pad, the trace spacing, and the trace thickness.
5. The processor pin array according to claim 1, characterized in that, The spacing is: D = R1*2 + d1*2 + d2 + w*2; Where D is the pitch, R1 is the solder ball radius, d1 is the distance between the trace and the pad, d2 is the trace pitch, and w is the trace thickness.
6. The processor pin array according to claim 1, characterized in that, The processor pin array has a first partition and a second partition for placing DDR signal pins, GND pins and power pins. The DDR signals in the first partition and the second partition are fanned out to the left or right on the motherboard, respectively, and each DDR channel occupies a separate trace layer.
7. The processor pin array according to claim 6, characterized in that, DDR signals include data signals and command and address signals. The data signals consist of multiple bytes, each byte containing 8 DQ signals and two sets of DQS differential signals.
8. The processor pin array according to claim 7, characterized in that, Within the same byte, each DQ signal is adjacent to only one DQ signal. When the DQ signals within the same byte are adjacent to DQS differential pairs, they are also adjacent to DQS+ and DQS- signals. Signals of different bytes in the same DDR channel are adjacent in the vertical direction. Different bytes in the same DDR channel are isolated by GND, and bytes in different DDR channels are adjacent in the horizontal direction.
9. The processor pin array according to claim 1, characterized in that, The processor pin array has a third partition and a fourth partition for placing high-speed differential signal pins, GND pins, and power pins. The high-speed differential signals are routed in the inner layer and fan out upwards or downwards in the third and fourth partitions, respectively. The high-speed differential signals are the high-speed serial computer expansion bus standard PCIe.
10. The processor pin array according to claim 9, characterized in that, The differential pairs of the high-speed differential signal pins in the same row are arranged diagonally and horizontally in an alternating manner. The differential pairs in different rows are staggered by one differential pair. Each signal in a differential pair is adjacent to two power supplies of the same type.
11. The processor pin array according to claim 1, characterized in that, The processor pin array has a fifth partition for placing power pins and GND pins for return current, which are respectively routed on the power layer and GND layer of the motherboard.
12. The processor pin array according to claim 1, characterized in that, The processor pin array has a sixth and a seventh partition for placing low-speed signal pins. The low-speed signals are routed on the surface layer and fan out upwards or downwards on the motherboard.