Circuit and test system for detecting via degradation

Abstract

A circuit and a test system for detecting via degradation are provided. A circuit for detecting degradation of vias includes a current source configured to deliver a constant supply of current to a plurality of vias of a device under test. The circuit further includes a plurality of switches configured to connect a current source to the plurality of vias; and an analog-to-digital converter (ADC) configured to be connected to the plurality of vias via a first wiring via the plurality of switches, the first wiring being connected to a first input of the ADC. A plurality of switches configured to connect one of the plurality of vias to a current source and a first wiring at a time; and the ADC is configured to output a signal representative of a resistance of a via connected to the ADC and the current source.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of circuit and system, in particular to a kind of circuit and test system for detecting via hole degradation. BACKGROUND

[0002] The trend of continuous miniaturization in the semiconductor industry has led to smaller, faster devices with improved power consumption. A key development in this trend has been the development of various features such as through-silicon-via (TSV), which is an electrically conductive interconnect that extends in a vertical direction through a substrate, enabling stacked packaging of semiconductor devices. Modern semiconductor packages can include thousands of such beneficial features, such as TSVs that interconnect components across multiple levels. SUMMARY

[0003] A circuit for detecting via hole degradation includes a current source, a plurality of switches, and an analog-to-digital converter (ADC). The current source is configured to deliver a constant current supply to a plurality of via holes of a device under test. The switches are configured to connect the current source to the plurality of via holes. The analog-to-digital converter (ADC) is configured to be connected to the plurality of via holes via a first wiring by the plurality of switches, wherein the first wiring is connected to a first input of the analog-to-digital converter. The plurality of switches are configured to connect one of the plurality of via holes to the current source and the first wiring at a time. The analog-to-digital converter is configured to output a signal representing a resistance of a via hole connected to the analog-to-digital converter and the current source.

[0004] A test system includes a device under test and a circuit. The device under test includes a substrate, a plurality of via holes, a device and wiring layers, and a backside wiring layer. The substrate includes a first surface and a second surface opposite the first surface. The plurality of via holes are disposed within the substrate and extend between the first surface and the second surface. The device and wiring layers are disposed on the substrate. The backside wiring layer is disposed below the substrate. The circuit includes an analog-to-digital converter (ADC) and at least one second wiring. The analog-to-digital converter (ADC) is disposed in the device and wiring layers and has a first input connected to a first wiring, wherein the first wiring is configured to be connected to the plurality of via holes by a plurality of switches. The at least one second wiring is disposed in the backside wiring layer and connected to at least one of the plurality of via holes on a bottom side of the at least one via hole. The analog-to-digital converter is configured to output a signal representing resistance values of the plurality of via holes. BRIEF DESCRIPTION OF DRAWINGS

[0005] The various aspects of the present application will be best understood by reading the following detailed description, taken in conjunction with the accompanying drawings, in which: It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of clarity. It should be noted that, for the sake of clarity, the drawings are not necessarily drawn to scale.

[0006] Figure 1 A diagram of a circuit for measuring resistance of a via according to an embodiment is shown.

[0007] Figure 2A and Figure 2B A diagram of a circuit for measuring resistance of a plurality of vias according to an embodiment and a plot of output signals of the circuit are shown.

[0008] Figure 3A and Figure 3B A schematic diagram of a semiconductor device including a plurality of vias in an embodiment is shown.

[0009] Figure 4 A diagram of a circuit for measuring resistance of a plurality of vias within a semiconductor device according to an embodiment is shown.

[0010] Figure 5 A diagram of a circuit for measuring resistance of a plurality of vias according to an embodiment is shown.

[0011] Figure 6 A diagram of a circuit for measuring resistance of a plurality of vias according to another embodiment is shown.

[0012] Figure 7 A diagram of a circuit for measuring resistance of a plurality of vias according to another embodiment is shown.

[0013] Figure 8A , Figure 8B and Figure 8C A plot of example measurement values from a circuit for measuring resistance of a plurality of vias according to an embodiment is shown.

[0014] Figure 9 A flowchart of a method of testing a semiconductor device according to an embodiment is shown.

[0015] Unless otherwise indicated, corresponding reference numbers and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0016] The following disclosure provides different embodiments or examples to implement various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description of a second feature over or on a first feature can include embodiments in which the first feature is formed directly on the second feature, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be directly on each other. In addition, the present disclosure can repeat reference numerals and / or letters in some various examples. This repetition is for the purpose of simplification and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0017] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] Embodiments of the present disclosure are described. Additional operations can be provided before, during, and / or after the described embodiments. The order of various operations can be changed. Additional features can be added to the described embodiments. Various embodiments can omit, subsume, add to, subtract from, or modify other features described in the following disclosure.

[0019] As described above, features such as TSVs are becoming more prevalent in semiconductor devices. Over time, one or more TSVs within a package can deteriorate, thereby causing the resistance of the via to undesirably increase. While this can substantially increase the resistance of the individual TSV, in modern devices that include hundreds or even thousands of TSVs, it can be difficult to detect and locate deteriorated vias. Some modern devices can also incorporate super power rails (SPRs), which are another form of via that can be smaller than traditional TSVs while providing backside power delivery to the device. Similar challenges to detecting and locating TSVs are faced in detecting and locating deteriorated SPRs.

[0020] For example, the resistance of a TSV or SPR can be on the order of one-tenth of an ohm, while the capacitance on each end of a via can be on the order of a femtofarad (10"15). Thus, the resistance-capacitance (RC) characteristics of an individual via are typically so small that it is difficult to detect outliers. By placing all of the TSVs in a package in series and plotting the measured resistance, a statistical model can typically be used to detect a deteriorated TSV. However, such a test can not be precise enough to capture such small changes in resistance. Alternatively, a deteriorated via can be detected by measuring the delay caused by each via in a package; however, in modern devices of small scale, even if the resistance of a deteriorated via is increased by a factor of 10,000, the difference in delay can be only on the order of 10 picoseconds, which can also be difficult to detect.

[0021] To overcome these problems, embodiments set forth herein can use four-wire sensing (e.g., Kelvin sensing) to measure the resistance across each TSV of a device or package. Four-wire sensing is a technique that uses two pairs of wires (for a total of four wires) to accurately measure the resistance of a component. The first pair of wires supplies current through the component, while the second pair of wires measures the voltage across the component. The resistance can then be determined from the input current and the measured voltage. Four-wire sensing is intended to eliminate the resistance of the wires in the circuit, thereby allowing more accurate measurements of low resistance values.

[0022] For example, Figure 1 A diagram of a circuit for measuring the resistance across a via according to an embodiment is shown. Figure 1 Only the measurement across a single via 110 is shown, but embodiments set forth herein can be capable of evaluating hundreds or thousands of vias or more in a package or device. In an embodiment, a circuit for measuring the resistance across a via can receive a device under testing (DUT) 100. The device under testing can include a substrate 105 and a via 110 configured to carry a signal between a component located below the substrate and a component located above the substrate. The via 110 can extend from a bottom surface 105B of the substrate to a top surface 105A of the substrate. The via 110 can include a TSV or SPR as described above. The substrate 105 can also include interconnects and metallization layers (not shown) that connect the via 110 to components located on or in the substrate 105.

[0023] To measure the resistance of the via 110, a four-wire sensing approach can be employed. To this end, the circuit can include four wires (in Figure 1The four wires can be connected to an electrical path from one side of the via 110 to the other, labeled 1 to 4. The circuit can further include a current source 111, a switch 113, a voltage measurement device 115, and a digital controller 117. The digital controller 117 can control the switch 113. When the switch 113 is closed, the via 110 is connected to the current source 111 and sensing can occur. As explained in more detail below with respect to FIG. 2, the switch 113 and the digital controller 117 can enable one via at a time to be connected to the current source 111, thereby enabling the measurement process to determine which via is producing an output signal at a given time.

[0024] When the switch 113 is closed, the external wire 1 and the external wire 4 can form a current path that carries a known current supplied by the current source 111 through the via 110. The internal wire 2 and the internal wire 3 are each connected to a current path that is adjacent to the via 110 and on opposite sides of the via 110. The wires 2 and 3 create a sensing path for the voltage measurement device 115 that includes measuring the voltage drop across the via 110. The voltage measurement device 115 can send a signal to the digital controller 117 reporting the measured data. Using Ohm’s law, the resistance of the via 110 can be calculated from the measured voltage and the known current.

[0025] In an embodiment, the voltage measurement device 115 can be an analog-to-digital converter (ADC). An ADC is an electronic component that takes a continuous analog signal as input and outputs a discrete digital signal. For example, an ADC functioning as the voltage measurement device 115 can monitor the voltage across a TSV as an input signal and output a digital representation of the signal over time.

[0026] The output signal can be a binary signal that outputs a “1” (high) or a “0” (low) based on the measured voltage. The ADC can be configured to switch from low to high or from high to low at a particular input threshold voltage. This threshold voltage can be set so that it corresponds to a resistance of the via 110 that indicates a deteriorating via. Thus, the circuit can measure whether a via 110 is deteriorating based on whether the ADC outputs a high signal or a low signal. In an embodiment that includes multiple vias, an ADC can be connected to each via of the package, and the digital controller can toggle the switch on and off in a particular order, thereby connecting different vias to the ADC one at a time. In this type of circuit, the output of the ADC represents the voltage measurement of each via in a sequence. By monitoring the output of the ADC, the presence and location of a deteriorating via can be determined. More detail about this type of circuit is explained below with respect to FIG. 2. Figure 2A and Figure 2B This type of circuit is explained in more detail.

[0027] Figure 2A A diagram of a circuit for measuring the resistance of a plurality of vias 210 is shown, according to an embodiment. Figure 2A The illustrated circuit can measure the resistance of a plurality of vias within a device or package and can provide a means for determining the location of any degraded via. For example, the plurality of vias 210 can be part of a device connected to the circuit for testing. In an embodiment, the plurality of vias 210 can include via 210-A, via 210-B, via 210-C, and via 210-D. The vias can include TSVs and / or SPRs, as described above. Although only four vias are shown in the diagram, it should be understood that the circuit can be connected to hundreds or even thousands of vias.

[0028] The plurality of vias 210 can be connected to a four-wire sensing arrangement in a similar manner as described above with respect to Figure 1 The circuit can further include a current source 211, an ADC 215 for voltage measurement, and a digital controller 217, according to an embodiment. The digital controller can control a plurality of switches arranged in correspondence with the plurality of vias 210-A to 210-D.

[0029] To complete the four-wire sensing arrangement, the vias 210-A to 210-D can be connected to the ADC 215 on both the top side and the bottom side of each via. On the top side, each via can be connected to a conductive trace 271 connected to a first input of the ADC 215. This connection can be made by a switch controlled by the digital controller 217. The manner in which the switches are turned on and off will be described in more detail below. On the bottom side, each via can be connected to a second conductive trace 272 connected to a second input of the ADC 215. In an embodiment, the ADC 215 can be located in the device and wiring layer on the top side of the plurality of vias. Thus, to connect the trace 272 to the second input of the ADC 215, the trace 272 must pass through the substrate back to the wiring via a return via 219. The return via 219 can include one or more vias specifically configured to make this connection.

[0030] The plurality of switches can include a first switch 213-A, a second switch 213-B1 and a second switch 213-B2, a third switch 213-C, and a fourth switch 213-D. More switches can be provided for each via that is connected to the circuit and undergoes measurement and testing, in the same manner as shown. Each via is connected to a set of two switches, one of which connects the via to the current source 211, and the other of which connects the via to the conductive wiring 271, which is further connected to the first input of the ADC 215. FIG. 2 shows the switches 213-A, 213-C, and 213-D in an open position in which the corresponding via 210-A, 210-C, and 210-D are not connected to the ADC 215. However, the switches 213-B1 and 213-B2 are in the closed position, thereby connecting the via 210-B to the ADC 215, enabling the voltage across the via to be measured, and thus the resistance of the via to be measured.

[0031] The switches 213-A through 213-D can be controlled by a digital controller 217, which opens and closes the switches to connect and disconnect the vias 210-A through 210-D to and from the ADC 215. The digital controller 217 can do this in a predetermined order. Since the output of the ADC 215 measures the resistance across each via, by connecting the vias in a particular order, the output of the ADC can indicate exactly which of the hundreds or thousands of vias in the array have deteriorated.

[0032] For example, when testing the reliability of multiple vias in a package or chip, the digital controller 217 can first connect via 210-A to ADC 215 using switch 213-A while other switches are open. The ADC can then output a first reading corresponding to the voltage across (and thus the resistance of) via 210-A. Next, the digital controller 217 can disconnect via 210-A from ADC 215 and can close switches 213-B1 and 213-B2 to connect via 210-B to ADC 215, resulting in a second reading corresponding to the voltage across (and thus the resistance of) via 210-B. Thereafter, the digital controller 217 can disconnect via 210-B from ADC 215 and connect via 210-C to the ADC using switch 213-C, resulting in a third reading corresponding to the voltage and resistance associated with via 210-C. The digital controller can then disconnect via 210-D and connect via 210-D to ADC 215 using switch 213-D, resulting in a fourth reading corresponding to the voltage and resistance associated with via 210-D. Although only four pairs of vias and switches are shown, this process can continue for any number of cycles to obtain readings for each via in the package.

[0033] In the above example, via 210-C can represent a degraded via. As such, when measuring across via 210-C, the output of ADC 215 can be different than the output of normally functioning vias 210-A, 210-B, and 210-D. Figure 2B A graph showing example output of ADC 215 is shown in accordance with an embodiment. The graph plots ADC signal output versus time. The signal can vary between 0 and 1 depending on the voltage and resistance of the via being measured. The vertical dashed lines in the graph show the timing of the measurement of each of 210-A, 210-B, 210-C, and 210-D.

[0034] In an embodiment, the ADC can be tuned to have a threshold voltage set to indicate the level at which a via being measured is degraded. This voltage can vary depending on the design and the level of sensitivity required. According to Ohm’s Law (V = IR), at a constant supply current, when the resistance of the measured via is within the normal operating range, the measured voltage will also be within the normal operating range. This voltage can be below the threshold voltage of the ADC and result in a “0” output signal. Figure 2BThe measurement performed on 210-A (at time T210-A) and 210-B (at time T210-B) causes this output signal. When a measurement is performed across the degraded via 210-C, the measured voltage exceeds the ADC's threshold voltage, resulting in a "1" output signal at time T210-C. When the measurement proceeds to 210-D, the output signal returns to "0" at time T210-D. In this configuration, any degraded via will cause a "1" output. Therefore, the output signal can be compared with the predetermined order in which the vias are connected to the ADC to determine the location of any degraded via.

[0035] Figure 3A and Figure 3B A schematic diagram of a semiconductor device including multiple through-holes is shown. Figure 3A and Figure 3B The apparatus shown can be connected to the circuit described above to measure the resistance across the plurality of vias of the apparatus. In an embodiment, the apparatus can be a device under test (DUT) connected to circuitry for detecting via degradation to form a test system.

[0036] Figure 3A The illustrated device may include multiple TSVs 310. The TSVs 310 may provide connections via the substrate 300 and device and wiring layer 322 to the top die 324 via pads or other interconnects. Components of the measurement circuitry (e.g., current sources or ADCs) may also be located within the device and wiring layer 322; such devices can be easily connected to the circuitry as a DUT to detect any degradation of the TSVs 310. As mentioned above, this may require the measurement circuitry to include return vias connecting the bottoms of the multiple TSVs 310 back to the device and wiring layer 322 via the substrate 300.

[0037] Figure 3B The apparatus shown may include a plurality of SPRs 311. Each SPR 311 may have a relatively... Figure 3A The TSV shown has a small diameter. In an embodiment, an SPR can be formed through the substrate 300 to connect the rear wiring layer 320 to the device and wiring layer 322. The SPR may terminate at the top surface of the substrate and not extend further into the device and wiring layer 322. Figure 3A Similar to the apparatus described herein, an apparatus comprising multiple SPRs can be connected to circuitry for measuring the resistance of the multiple SPRs. Components of this circuitry may be disposed within the apparatus and wiring layer 322 and rear wiring layer 320. In some embodiments, the apparatus may include a combination of TSV 310 and SPR 311.

[0038] Figure 4 A diagram of a circuit for measuring the resistance of a plurality of through-holes within a semiconductor device, according to an embodiment, is shown. This circuit can be used...Figure 4 The circuit shown in FIG. 1 1 1 measures the multiple vias of the semiconductor device as described above with respect to Figure 3A and Figure 3B The multiple vias of the semiconductor device as described above with respect to Figure 4 FIG. 1 1 1 shows the positioning of some components within the device (e.g., some components are shown in the device and wiring layers, while the bottom side wiring is shown in the backside wiring layer).

[0039] Figure 4 The components of the circuit in FIG. 1 1 1 can be similar to those described above with respect to Figure 2A For example, the multiple vias 410 can be connected to a four-wire sensing scheme using multiple switches 413. The multiple switches 413 can connect the multiple vias 410 of the device under test to the current source 41 1 and the ADC 415 via the first wiring 471 and disconnect the multiple vias 410 of the device under test from the current source 41 1 and the ADC 415. The other side of the multiple vias 410 can be connected to the other input of the ADC 415 via the second wiring 472 and the return via 419.

[0040] The digital controller 417 can control the multiple switches 413 and receive the output signal from the ADC 415. In an embodiment, the components on the top side of the multiple vias can be in the device and wiring layers, while the components on the bottom side of the multiple vias can be in the backside wiring layer. By connecting the vias 410 to the current source 41 1 and the ADC 415 in this manner, accurate measurements of the voltage across each via and the resistance of each via can be made, enabling the accurate location of any degraded vias to be detected.

[0041] Figure 5 A diagram of a circuit for measuring the resistance of multiple vias according to an embodiment is shown. The components of the circuit can be similar to those described above with respect to Figure 2A and Figure 4 For example, the multiple vias 510 can be connected to a four-wire sensing scheme to determine the voltage across each via and the resistance of each via. This scheme can include multiple switches 513 controlled by a digital controller 517 to connect the multiple vias 510 to the current source 51 1 and the ADC 515 and disconnect the multiple vias 510 from the current source 51 1 and the ADC 515. On the top side of the vias, the switches connect each via to the ADC 515 via the first wiring 571.

[0042] In this example, the bottom of each via of the plurality of vias 510 is connected to a respective wire located in the backside wiring layer. The first via can be connected to a second wire 573, the second via can be connected to a third wire 574, the third via can be connected to a fourth wire 575, and the fourth via can be connected to a fifth wire 576. This plurality of wires can be connected to the second input of the ADC 515 via the return via 519. In this way, a wire located on the bottom side of the plurality of vias 510 can be provided in one-to-one correspondence with the plurality of vias. Additionally, there can be a one-to-one correspondence between the via that makes up the return via 519, the plurality of vias 510, and the plurality of wires located on the bottom side of the plurality of vias. The second input of the ADC 515 can be connected to a switch also controlled by the digital controller 517 to connect to a corresponding return via of the return vias 519. In this embodiment, each via is also associated with a respective return via. In this way, connecting the vias can reduce the risk of circuit failure when a return via degrades. This type of connection scheme can ensure that a degraded return via only affects the measurement of one via to be measured, rather than causing multiple measurements to be affected by a degraded return via.

[0043] Figure 6 A diagram of a circuit for measuring the resistance of a plurality of vias according to another embodiment is shown. Figure 6 The components in FIG. 6 can be similar to the components in the above examples. For example, the plurality of vias 610 can be connected to a four-wire sensing scheme to determine the voltage across each via and the resistance of each via. This scheme can include a plurality of switches 613 controlled by the digital controller 617 to connect the plurality of vias 610 to the current source 611 and the ADC 615 and to disconnect the plurality of vias 610 from the current source 611 and the ADC 615. On the top side of the vias, the switches can connect each via to a first input of the ADC 615 via a first wire 671.

[0044] In this example, each via of the plurality of vias 610 can be connected to a single second wire 672.

[0045] The resistance of the second wire 672 can be greater than the resistance of the path between the plurality of vias and the ground voltage GND.

[0046] The second wiring 672 can provide a connection between the bottom side of the plurality of vias and a second input of the ADC 615. This connection can pass through a return via 619. The return via can include two TSVs that share the signal routing between the bottom side of the plurality of vias and the second input of the ADC 615. By providing two vias connected to the second wiring 672 to complete this backside wiring, a circuit failure due to a single return TSV degradation can be avoided. Such a configuration can also occupy less space and include a greater number of devices under test (DUTs) in a given area.

[0047] Figure 7 A diagram of a circuit for measuring resistance of a plurality of vias is shown, according to another embodiment. Figure 7 The components in can be similar to those in the above examples, but rather than connecting the bottom side of each via of the plurality of vias 710 to a second input of the ADC 715, the second input of the ADC can be connected to a reference voltage VREF 725. In embodiments, the ADC 715 can be a comparator having a first input connected to a first wiring 771 connected to the top side of the plurality of vias 710.

[0048] In operation, the ADC 715 can compare the voltage of the first input to the reference voltage 725. The reference voltage can be set to recognize a degraded via. For example, at a high resistance caused by a degraded via, the voltage measured at the first input will correspondingly be high, and the comparator will output a signal indicating that the voltage at the first input is higher than the reference voltage 725. By comparing the output of the comparator to a predetermined order of the plurality of vias connected, the location of a particular degraded via can be determined. Using a reference voltage as the second input of the ADC can enable more precise tuning of the sensing window of the circuit, as described below with respect to Figure 8A to Figure 8C is described in more detail.

[0049] Figure 8A , Figure 8B and Figure 8C is a diagram showing how the sensing window of a circuit for measuring resistance of a plurality of vias can be tuned. Figure 8A A diagram of a circuit for measuring resistance of a plurality of vias is shown. Figure 8B and Figure 8C is a diagram showing a plot of the output of a circuit under different operating conditions.

[0050] Figure 8ACircuit 800 is shown that can have similar components to those set forth in the above examples. The circuit can be designed to measure the resistance of a plurality of vias including via 810-A, via 810-B, via 810-C, and via 810-D to determine the presence and location of any degraded via. Circuit 800 can take the form of any of the embodiments described above. For example, FIG. 8 shows dashed lines connecting to the bottom of each of the plurality of vias. This indicates that circuit 800 can have a connection scheme as shown in Figure 5 , Figure 6 or Figure 7 .

[0051] The sensing window of the circuit can be tuned by adjusting the characteristics of the ADC, the value of VREF, and / or the current supplied by the current source. For example, the level of degradation to be screened for can be easily selected by setting these parameters. Figure 8A Example values of the supplied current, the voltage across each of the plurality of vias, and the measured via resistance are shown. Figure 8B and Figure 8C A graph showing how the tuning of these parameters can change the determination based on the level of resistance sought to be screened for is shown.

[0052] In an example, current source 811 can supply a constant current of 4 milliamps (mA). A first via of the plurality of vias 810-A can have a resistance of 0.13 ohms that causes a voltage drop of 0.5 millivolts (mV), a second via of the plurality of vias 810-B can have a resistance of 2 ohms that causes a voltage drop of 8 mV, a third via of the plurality of vias 810-C can have a resistance of 1000 ohms that causes a voltage drop of 4000 mV, and a fourth via of the plurality of vias 810-D can have a resistance of 20 ohms that causes a voltage drop of 80 mV.

[0053] In an embodiment, the first resistance can be in a normal operating condition and indicate that via 810-A is not degraded. In contrast, the resistance of via 810-C and the resistance of via 810-D can be higher than the normal operating condition and indicate that both vias have degraded beyond an acceptable amount. However, second via 810-B can be at an acceptable level in some cases and at an unacceptable level in other cases. By tuning the circuit parameters (ADC characteristics, VREF, current supply as described above), different screening levels can be achieved such that 810-B is flagged as degraded in some implementations and shown to be within the normal operating condition in other implementations.

[0054] Figure 8B The difference is shown in Figure 8C Figure 8B ​In one embodiment, the parameters of the circuit can be set such that the voltage level at which the "0" output from the ADC 815 changes to a "1" output occurs at 7 millivolts. This voltage can be considered the threshold voltage (VTH) of the ADC 815. In such an embodiment, when the characteristics of the via 810-B are measured, the ADC 815 triggers a "1" signal, which indicates that the via has deteriorated beyond acceptable tolerance. In Figure 8C In another embodiment, the parameters of the circuit can be different, and the threshold voltage of the ADC 815 can be set at 70 millivolts. In such an embodiment, when the characteristics of 810-B are measured, the ADC 815 can maintain a "0" signal, which indicates that the via is still operating within acceptable limits based on the needs of the particular design.

[0055] As in the example above, the plurality of vias can be measured in a predetermined order and disconnected such that it can be determined which particular via corresponds to a "1" output signal and thus has deteriorated by analyzing the output of the ADC 815. By providing a measurement circuit as set forth in the above embodiments, a defect parasitic resistance that is approximately fifty times the nominal parasitic resistance can be detected. This can represent a measurement that is twenty times more sensitive than a circuit that measures RC delay to identify defects.

[0056] Figure 9 A flowchart of a method of testing a semiconductor device is shown. The method of testing can use the circuit described above for measuring the resistance across a plurality of vias to determine whether any of the vias of the device have deteriorated. The method can first be performed 901 by receiving a semiconductor device that includes a circuit for measuring the resistance of a plurality of vias. The semiconductor device can include a plurality of vias extending through a substrate.

[0057] The semiconductor device can be similar to the semiconductor devices described above with respect to Figure 3A or Figure 3B The plurality of vias can include a plurality of TSVs, a plurality of SPRs, or a combination thereof. The circuit for measuring the resistance of the plurality of vias can be the circuit described above in the embodiments. For example, the circuit can include Figure 4 the circuit shown. The circuit can be formed as part of the semiconductor device and disposed at least partially within the device and wiring layers on the top side of the plurality of vias and the backside wiring layers on the bottom side of the plurality of vias. In other embodiments, the semiconductor device can be externally connected to the circuit. The device can be tested using a wafer probing method.

[0058] At 903, a first via of the plurality of vias is connected to a current source of the circuit and a first input of an ADC of the circuit. As described above, such a connection can be made by a plurality of switches controlled by a digital controller. For example, the plurality of vias can comprise the plurality of vias 410, and the digital controller 417 can control the plurality of switches 413 to connect one via at a time to the current source 411 and to a first wire 471 that is also connected to a first input of the ADC 415. The plurality of vias can also be connected to a second input of the ADC 415 via a second wire 472. However, as described above with reference to Figure 7 In other embodiments, the second input of the ADC can be connected to a reference voltage.

[0059] At 905, the resistance of the first via 410-A can be measured. Such a measurement can include a reading corresponding to an output signal of the ADC 415. In embodiments, the ADC 415 measures the voltage across the via using a four-wire sensing scheme and outputs a signal indicating whether the measured voltage is above or below a threshold voltage, which represents a level of degradation that is not within an acceptable range. Since the supplied current is constant, the measured voltage also corresponds to the resistance of the via. Thus, the output signal of the ADC indicates whether the resistance of the via being measured is above or below an acceptable resistance amount.

[0060] At 907, the first via can be disconnected from the current source and the ADC. In embodiments, this can also be controlled by a signal from the digital controller 417. As indicated at 909, the method can then return to 903, in which another via of the plurality of vias is connected to the current source and the ADC and the resistance of the other via is measured. In Figure 4 In the illustrated example, 410-A can be disconnected, while 410-B can be connected and measured.

[0061] As shown at 909, this process can be repeated any number of times until all vias of the device have been measured. In a device having N (which can be a number in the hundreds or thousands) vias, the process can be repeated N times. Finally, after the resistance of all vias has been measured, the method can end at 911. The readings of the ADC output can then show the measured values across all vias of the device and any degraded vias within the device can be located.

[0062] Circuits, methods, and systems are set forth herein. In an example circuit for detecting degradation of a via, a current source configured to supply a constant current is connected to a plurality of vias of a device under test. A plurality of switches configured to connect the current source to the plurality of vias and an analog-to-digital converter (ADC) configured to be connected to the plurality of vias by the plurality of switches via a first wiring are provided. The plurality of switches are configured to connect one of the plurality of vias to the current source and the ADC at a time, and the ADC is configured to output a signal indicative of a resistance of the via connected to the ADC and the current source.

[0063] In some embodiments, the plurality of vias described above comprises a plurality of through silicon vias (TSVs).

[0064] In some embodiments, the plurality of vias described above comprises a plurality of super power rail strips (SPRs).

[0065] In some embodiments, the plurality of vias described above comprises both through silicon vias and super power rail strips.

[0066] In some embodiments, the circuit described above further comprises a plurality of second wirings each connected to one of the plurality of vias; and a plurality of return vias each corresponding to one of the plurality of second wirings and one of the plurality of vias.

[0067] In some embodiments, the circuit described above further comprises a second wiring connected to each of the plurality of vias, wherein the second wiring is configured to connect the plurality of vias to a second input of the analog-to-digital converter.

[0068] In some embodiments, the analog-to-digital converter described above comprises a second input connected to a reference voltage.

[0069] In some embodiments, the analog-to-digital converter described above measures a voltage across the via connected to the analog-to-digital converter and the current source, and is configured to output a signal indicative of whether the voltage is above or below a threshold voltage; and the threshold voltage corresponds to a resistance level of a degraded via.

[0070] In some embodiments, the circuit described above further comprises a digital controller, wherein the digital controller is configured to control the plurality of switches to connect the plurality of vias to the current source and the analog-to-digital converter in a predetermined order.

[0071] In some embodiments, the analog-to-digital converter described above comprises a comparator.

[0072] An example method of testing a plurality of vias includes providing a circuit including a current source, a plurality of switches, and an analog-to-digital converter (ADC). The circuit is connected to a device under test including a plurality of vias. A first via of the plurality of vias is connected to the current source using a first switch of the plurality of switches and to a first wire using a second switch of the plurality of switches, where the first wire is connected to a first input of the ADC. A resistance of the first via is measured using the ADC. The first via is disconnected from the current source and the first wire. A second via of the plurality of vias is connected to the current source using a third switch of the plurality of switches and to the first wire using a fourth switch of the plurality of switches. A resistance of the second via is measured using the ADC.

[0073] In some embodiments, the plurality of vias includes N vias; and the method includes measuring resistances of the N vias.

[0074] In some embodiments, the connecting the first via, the disconnecting the first via, the connecting the second via, and the disconnecting the second via are controlled by a digital controller.

[0075] In some embodiments, the plurality of vias is configured to be connected to a second input of the analog-to-digital converter via a plurality of second wires, the plurality of second wires corresponding one-to-one to the plurality of vias.

[0076] In some embodiments, each of the plurality of vias is connected to a second wire configured to connect the plurality of vias to a second input of the analog-to-digital converter.

[0077] In some embodiments, the analog-to-digital converter includes a second input connected to a reference voltage; and the measuring the resistance of the first via and the measuring the resistance of the second via includes comparing a voltage measured at the first input to the reference voltage.

[0078] An example test system includes a device under test and circuitry. The device under test includes a substrate including a first surface and a second surface opposite the first surface, a plurality of vias disposed within the substrate and extending between the first surface and the second surface. The device also includes a device and wiring layer disposed on the substrate and a backside wiring layer disposed below the substrate. The circuitry includes an analog-to-digital converter (ADC) located in the device and wiring layer and having a first input connected to a first wire, where the first wire is configured to be connected to the plurality of vias by a plurality of switches. The circuitry also includes at least one second wire located in the backside wiring layer and connected to at least one via of the plurality of vias on a bottom side of the at least one via. The ADC is configured to output a signal representative of resistance values of the plurality of vias.

[0079] In some embodiments, the circuitry described above further includes a current source disposed in the device and wiring layer and configured to supply a constant current.

[0080] In some embodiments, the at least one second wire described above includes a plurality of second wires corresponding one-to-one to the plurality of vias.

[0081] In some embodiments, the at least one second wire described above is connected to each of the plurality of vias and further connected to a second input of the analog-to-digital converter.

[0082] The foregoing has outlined rather broadly the features of several embodiments so that those skilled in the art can better understand the spirit and scope of the application. Those skilled in the art will appreciate that they can readily apply the conception disclosed herein as a basis for the design and construction of other processes and structures for carrying out the same purposes and / or for achieving the same advantages of the embodiments introduced herein. Those skilled in the art will realize that such equivalent constructions do not depart from the spirit and scope of the application and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the application.

Claims

1. A circuit for detecting via degradation, comprising: comprises: a current source configured to deliver a constant current supply to a plurality of vias of a device under test; a plurality of switches configured to connect the current source to the plurality of vias; and an analog-to-digital converter configured to be connected to the plurality of vias via a first wiring by the plurality of switches, wherein the first wiring is connected to a first input of the analog-to-digital converter, wherein the plurality of switches are configured to connect one via of the plurality of vias to the current source and the first wiring at a time; and wherein the analog-to-digital converter is configured to output a signal representing a resistance of a via connected to the analog-to-digital converter and the current source.

2. The circuit of claim 1, wherein the plurality of vias comprises a plurality of through silicon vias.

3. The circuit of claim 1, wherein the plurality of vias comprises a plurality of super power rail bars. further comprising a plurality of second wirings connected to the plurality of vias one-to-one; and 4. The circuit of claim 1, wherein a plurality of return vias corresponding to the plurality of second wirings and the plurality of vias one-to-one. further comprising a second wiring connected to each of the plurality of vias, wherein the second wiring is configured to connect the plurality of vias to a second input of the analog-to-digital converter.

5. The circuit of claim 1, wherein 6. The circuit of claim 1, wherein the analog-to-digital converter measures a voltage across the via connected to the analog-to-digital converter and the current source and is configured to output a signal indicating whether the voltage is above or below a threshold voltage; and the threshold voltage corresponds to a resistance level of a deteriorated via. comprises a digital controller, 7. The circuit of claim 1, further comprising wherein the digital controller is configured to control the plurality of switches to connect the plurality of vias to the current source and the analog-to-digital converter in a predetermined order. comprises:

8. A test system, characterized by a device under test; and a circuit; the device under test comprises: a substrate comprising a first surface and a second surface opposite to the first surface; a plurality of vias disposed within the substrate and extending between the first surface and the second surface; a device and wiring layer disposed above the substrate; and a backside wiring layer disposed below the substrate; the circuit comprises: an analog-to-digital converter disposed in the device and wiring layer and having a first input connected to a first wiring, wherein the first wiring is configured to be connected to the plurality of vias by a plurality of switches; and at least one second wiring disposed in the backside wiring layer and connected to at least one via of the plurality of vias on a bottom side of the at least one via, wherein the analog-to-digital converter is configured to output a signal representing resistance values of the plurality of vias.

9. The system of claim 8, wherein the circuit further comprises a current source disposed in the device and wiring layer and configured to supply a constant current.

10. The system of claim 8, wherein the at least one second wiring is connected to each of the plurality of vias and further connected to a second input of the analog-to-digital converter. ​

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