Charging management module circuit for seismograph

Abstract

The utility model discloses a charging management module circuit used for a seismograph, a VCC pin of a battery charging management chip U21 is electrically connected with a charging input voltage VBUS, a VG pin is electrically connected with the charging input voltage VBUS through a capacitor C204, a GND pin is grounded, a DRV pin drives and controls on and off of a PMOS tube, a source electrode of the PMOS tube is electrically connected with the charging input voltage VBUS, and a drain electrode of the PMOS tube is electrically connected with the charging input voltage VBUS. The drain electrode is electrically connected with a battery voltage VBAT through a diode D11, an inductor L9 and a current sampling resistor R204 in sequence, a CSP pin is electrically connected with one end of the current sampling resistor R204, a BAT pin is electrically connected with the other end of the current sampling resistor R204, a DONE pin is electrically connected with a PE7 input detection pin of the MCU, the PE7 input detection pin is electrically connected with an input voltage VDD, during charging, the DONE pin is in a high-resistance state, charging is finished, and the DONE pin is in a low-resistance state. The charging circuit has the advantages that the charging efficiency and the stability of the battery are improved, the effective service time of the battery is prolonged, the service life of the battery is ensured, and the like.

Description

TECHNICAL FIELD

[0001] The utility model relates to battery charging technical field, specifically a kind of charging management module circuit for seismograph. BACKGROUND

[0002] In active-source seismic exploration with artificial seismic source to excite seismic wave, the seismograph is arranged according to predetermined line number and stake number, and at least several thousand seismographs are needed for one exploration plan, which are arranged in batches, and immediately start collecting work after arrangement is completed. Sometimes, the interval time between different batches of seismographs is relatively long, and there is a problem that the current batch of seismographs is not completed, and the last batch of seismographs has been working to the off state. Therefore, the construction personnel need to charge the last batch of seismographs in time to ensure the smooth completion of the seismic exploration task. Therefore, there is an urgent need for a charging management module that can improve the charging efficiency and stability of the battery, ensure the service life of the battery and prolong the effective use time of the battery. SUMMARY

[0003] The utility model aims at providing a charging management module circuit for seismograph, which can improve the charging efficiency and stability of the battery, prolong the effective use time of the battery and ensure the service life of the battery.

[0004] The utility model solves the technical problems by adopting the following technical scheme:

[0005] A charging management module circuit for seismograph is characterized by comprising a battery charging management chip U21, wherein the VCC pin of the battery charging management chip U21 is electrically connected with the charging input voltage VBUS, the VG pin is electrically connected with the charging input voltage VBUS through the capacitor C204, the GND pin is grounded, the DRV pin drives and controls the conduction and interruption of the PMOS tube, the source of the PMOS tube is electrically connected with the charging input voltage VBUS, the drain is electrically connected with the battery voltage VBAT in turn through the diode D11, the inductor L9 and the current sampling resistor R204, the CSP pin is electrically connected with one end of the current sampling resistor R204, the BAT pin is electrically connected with the other end of the current sampling resistor R204, the DONE pin is electrically connected with the PE7 input detection pin of the MCU, the PE7 input detection pin is electrically connected with the input voltage VDD, when charging, the DONE pin is in high resistance state, and when charging is completed, the DONE pin is pulled low to low level state.

[0006] The charging voltage is controlled in the form of PWM voltage reduction, the setting of the diode D11 with the one-way conduction characteristic can prevent current backflow and prevent the consumption of the battery energy when the input power supply is powered off, the setting of the current sampling resistor R204 can adjust the charging current during the constant current charging, the inductor L9 functions as a filter, the PE7 input detection pin is in the high level state in the default state, and is in the low level state after the charging is completed; when the PE7 pin is in the low level state, the MCU controls the end of the charging task, and the overcharge protection of the battery can be realized; and the setting of the above circuit can improve the charging efficiency and stability of the battery and prolong the service life of the battery.

[0007] The charging input voltage VBUS is grounded through an input capacitor combination, the input capacitor combination comprises capacitors C201, C202 and C203 which are arranged in parallel, the positive pole of the capacitor C201, one end of the capacitor C202 and one end of the capacitor C203 are electrically connected with the charging input voltage VBUS respectively, and the negative pole of the capacitor C201, the other end of the capacitor C202 and the other end of the capacitor C203 are grounded; the input capacitor combination can effectively filter high-frequency noise in the input power supply, and improve the stability and reliability of the circuit.

[0008] The capacitor C201 is a tantalum capacitor, the capacitor C202 and the capacitor C203 are ceramic capacitors; the capacitor C201 is a tantalum capacitor with a smaller equivalent input resistance in the charging circuit, the parallel ceramic capacitors C202 and C203 form an input capacitor combination, and the nominal value of the capacitors is selected according to the characteristics of the input voltage source, so that the high-frequency noise in the input voltage source can be effectively filtered.

[0009] The battery voltage VBAT is grounded through an output capacitor combination, the output capacitor combination comprises capacitors C205, C206 and C207 which are arranged in parallel, the positive pole of the capacitor C205, one end of the capacitor C206 and one end of the capacitor C207 are electrically connected with the battery voltage VBAT respectively, and the negative pole of the capacitor C205, the other end of the capacitor C206 and the other end of the capacitor C207 are grounded; the output capacitor combination and the cooperation of the output capacitor combination and the inductor L9 can effectively filter high-frequency noise in the output voltage.

[0010] The capacitor C205 is a tantalum capacitor, the capacitor C206 and the capacitor C207 are ceramic capacitors; the capacitor C205 is a tantalum capacitor with a smaller equivalent input resistance, the parallel ceramic capacitors C206 and C207 form an output capacitor combination, and the high-frequency noise in the output voltage can be effectively filtered.

[0011] The utility model also has diode D12, the negative pole of diode D12 is connected with the negative pole of D11, the positive pole of diode D12 is grounded, diode D12 is as freewheeling diode, when PMOS is cut off, diode D12 forward conducting freewheeling.

[0012] The diode D11 and the diode D12 are Schottky diodes.

[0013] The utility model discloses VDD3 is connected with the PE7 pin of MCU through resistance R201, the CHRG pin of battery charge management chip U21 is connected with charging input voltage VBUS through resistance R202, and the CHRG pin is high resistance state when charging is finished, and the CHRG pin is low level when charging, and the FB pin is connected with the other end of current sampling resistance R204 through resistance R205, and the COM pin is grounded through resistance R203 and capacitor C204.

[0014] The utility model discloses the power consumption calculation formula of PMOS pipe is:

[0015]

[0016] In the formula, P D Is the maximum power consumption (W) of PMOS pipe, VBUS is charging input voltage (V), VBATmax is the highest voltage of battery (V), R ds(on) Is the on-resistance (Ω) under the condition of 25 DEG C, I CH Is the charging current (A), d T It is the temperature difference value of PMOS pipe actual temperature and 25 DEG C.

[0017] Select the PMOS pipe that the package is T0-252 and on-resistance is small, low voltage drive, switching speed is fast, with the possible reduction of power consumption and benefit heat dissipation, prolong the working time of battery and improve charging efficiency.

[0018] The utility model constant current charging's charging current adjustment formula is:

[0019]

[0020] In the formula, ΔU cb Is the voltage difference (V) between CSP pin and BAT pin, R cs Is current sampling resistance (Ω).

[0021] The utility model discloses the ripple current calculation formula of inductance L9 is:

[0022]

[0023] In the formula, ΔI Lis the inductance ripple current (A), f is the switching frequency (Hz), L is the inductance nominal value (H), VBAT is the battery voltage (V);

[0024] The inductance L9 is selected as a patch inductance with a nominal value of 22uH, an equivalent resistance value of 50mΩ, a saturation current of 8A and a package type of WHC1050, so that the inductance ripple current is not too large to damage the internal structure of the battery and the electromagnetic radiation is low.

[0025] The beneficial effects of the utility model are that the circuit can improve the charging efficiency and stability of the battery, ensure the service life of the battery and prolong the effective working time of the battery. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is the charging management module circuit of the utility model.

[0027] Figure 2 is the voltage and current curve of the charging process of the utility model.

[0028] Figure 3 is the technical parameter of the lithium battery pack of the utility model. DETAILED DESCRIPTION

[0029] The utility model will be described below in combination with the drawings and examples.

[0030] As shown in the accompanying Figure 1 A charging management module circuit for a seismograph is provided with a battery charging management chip U21, the VCC pin of the battery charging management chip U21 is electrically connected with a charging input voltage VBUS, the VG pin is electrically connected with the charging input voltage VBUS through a capacitor C204, the charging input voltage VBUS is input to the VCC pin and the VG pin, and the VCC pin and the VG pin are used as the power supply voltage of the internal devices of the battery charging management chip U21 together, the GND pin is grounded, the DRV pin drives and controls the conduction and interruption of a PMOS tube, the source of the PMOS tube is electrically connected with the charging input voltage VBUS, the drain is electrically connected with a battery voltage VBAT in sequence through a diode D11, an inductance L9 and a current sampling resistor R204, the CSP pin is electrically connected with one end of the current sampling resistor R204, the BAT pin is electrically connected with the other end of the current sampling resistor R204, the FB pin is electrically connected with the other end of the current sampling resistor R204 through a resistor R205, and the COM pin is grounded through a resistor R203 and a capacitor C204 as a loop compensation input end.

[0031] The negative electrode of the diode D12 is electrically connected with the negative electrode of D11, and the positive electrode of the diode D12 is grounded.

[0032] The DONE pin is electrically connected with the PE7 input detection pin of the MCU, the PE7 input detection pin is electrically connected with the input voltage VDD3 through the resistor R201, when charging, the DONE pin is in a high resistance state, the PE7 input detection pin is pulled high to a high level state by VDD3, when charging is completed, the DONE pin is pulled low to a low level by the internal circuit of the battery charging management chip U21, and the PE7 input detection pin is in a low level state; when the PE7 input detection pin is in a low level state, the MCU controls the end of the charging task.

[0033] The CHRG pin is electrically connected with the charging input voltage VBUS through the resistor R202, and is in a high resistance state when charging is completed; when charging, the CHRG pin is pulled low to a low level by the internal circuit of the battery charging management chip U21, and the COM pin is grounded through the resistor R203 and the capacitor C204.

[0034] The charging voltage is controlled in the form of PWM voltage reduction, the unidirectional conduction characteristic diode D11 is arranged, so that the current backflow is prevented, and the energy of the battery is prevented from being consumed when the input power supply is powered off; the diode D12 is used as a freewheeling diode, and when the PMOS is cut off, the diode D12 is forwardly conducted to freewheel; the current sampling resistor R204 is arranged, so that the charging current during constant current charging can be adjusted; the inductor L9 plays a filtering role; the PE7 input detection pin is in a high level state by default, and is in a low level state after charging is completed, so that the overcharge protection of the battery can be realized; and the arrangement of the above circuit can improve the charging efficiency and stability of the battery, and prolong the service life of the battery.

[0035] In this embodiment, a three-section lithium battery series battery pack is used as a power supply battery of the seismograph, and the technical parameters of the battery pack are as shown in the attached table. Figure 3 As shown in the table, the nominal voltage of a single lithium battery is 3.6V, the charging input voltage VBUS ranges from 6.6V to 30V, and the charging input voltage needs to be 1.5V higher than the charging cutoff voltage during charging; in this embodiment, the minimum charging input voltage VBUS should be 14.1V, so as to ensure that the lithium battery is charged to a saturated state.

[0036] When the PMOS tube Q9 is turned on in this embodiment, the charging input voltage VBUS charges the inductor L9 and the output capacitor combination, the capacitor voltage and the inductor current rise, at this time the diode D12 is reverse cut-off, the charging input voltage VBUS charges the lithium battery; when Q9 is cut off, the output capacitor combination discharges to the lithium battery, the inductor L9 supplies power to the lithium battery, at this time the diode D12 is forward conducting and continues to flow; due to the characteristics of low forward voltage drop and short reverse recovery time, the Schottky diode is often used in high-frequency switching circuits, the switching frequency of the battery charging management chip U21 driving the PMOS tube is about 300 kHz, therefore, the diode D11 and the diode D12 in the embodiment adopt the Schottky diode, considering the current-carrying capacity and voltage withstand capability of the diode, the Schottky diode with insufficient current-carrying capacity and voltage withstand level will cause the device to heat and even be damaged, and the diode with too strong capacity will increase the switching loss of the charging circuit and reduce the efficiency, therefore, the SS56 Schottky diode with a current-carrying capacity of 5A, a voltage withstand value of 60V and a forward conduction voltage drop of 0.7V is selected in the embodiment.

[0037] The charging input voltage VBUS is grounded through the input capacitor combination, the input capacitor combination includes capacitors C201, C202 and C203 arranged in parallel, the positive electrode of the capacitor C201, one end of the capacitor C202 and one end of the capacitor C203 are respectively electrically connected with the charging input voltage VBUS, and the negative electrode of the capacitor C201, the other end of the capacitor C202 and the other end of the capacitor C203 are grounded; the input capacitor combination can effectively filter out high-frequency noise in the input power supply, improve the stability and reliability of the circuit.

[0038] The capacitor C201 adopts a tantalum capacitor, the capacitor C202 and the capacitor C203 adopt ceramic capacitors; in the charging circuit, the tantalum capacitor with smaller equivalent input resistance is selected for C201, the parallel ceramic capacitors C202 and C203 form an input capacitor combination, and the nominal value of the capacitor is selected according to the characteristics of the input voltage source, which can effectively filter out high-frequency noise in the input voltage source.

[0039] The battery voltage VBAT is grounded through the output capacitor combination, the output capacitor combination includes capacitors C205, C206 and C207 arranged in parallel, the positive electrode of the capacitor C205, one end of the capacitor C206 and one end of the capacitor C207 are respectively electrically connected with the battery voltage VBAT, and the negative electrode of the capacitor C205, the other end of the capacitor C206 and the other end of the capacitor C207 are grounded; the output capacitor combination and the cooperation of the output capacitor combination and the inductor L9 can effectively filter out high-frequency noise in the output voltage.

[0040] The capacitor C205 adopts a tantalum capacitor, the capacitor C206 and the capacitor C207 adopt ceramic capacitors; C205 selects a tantalum capacitor with a smaller equivalent input resistance, and the output capacitor combination is composed of the parallel ceramic capacitors C206 and C207, which can effectively filter high-frequency noise in the output voltage.

[0041] The power consumption calculation formula of the PMOS tube is:

[0042]

[0043] In the formula, P D is the maximum power consumption (W) of the PMOS tube, VBUS is the charging input voltage (V), VBATmax is the highest voltage of the battery (V), R ds(on) is the on-resistance (Ω) at 25℃, I CH is the charging current (A), d T is the temperature difference between the actual temperature of the PMOS tube and 25℃;

[0044] The PMOS tube with T0-252 package, small on-resistance, low voltage drive, and fast switching speed is selected; in order to reduce power consumption and facilitate heat dissipation, prolong the working time of the battery, and improve the charging efficiency.

[0045] The charging current adjustment formula during constant current charging is:

[0046]

[0047] In the formula, ΔU cb is the voltage difference (V) between the CSP pin and the BAT pin, R cs is the current sampling resistance (Ω);

[0048] In this embodiment, ΔU cb 0.12V is output by the internal voltage divider of the battery charging management chip U21, and when the current sampling resistance is set to 0.06Ω, the constant current charging current is 2A.

[0049] The ripple current calculation formula of the inductor L9 is:

[0050]

[0051] In the formula, ΔI L is the inductor ripple current (A), f is the switching frequency (Hz), L is the inductance nominal value (H), and VBAT is the battery voltage (V);

[0052] The ripple current of the inductor L9 increases with the decrease of the inductance value and the increase of the input voltage. A larger inductance ripple current will result in a larger ripple charging current and magnetic loss, and an excessively large ripple current will damage the internal structure of the lithium battery. Generally, the ripple current should be less than 0.3 times the charging current. In this embodiment, in order to ensure low electromagnetic radiation, the inductor L9 is selected to be a surface mount inductor with a nominal value of 22 μH, an equivalent resistance value of 50 mΩ, a saturation current of 8 A, and a package type of WHC1050. This ensures that the ripple current of the inductor will not be too large to damage the internal structure of the battery and ensures low electromagnetic radiation.

[0053] In this embodiment, the battery charging management chip U21 is a CN3763 chip.

[0054] In this embodiment, the schematic diagram of the changes of the voltage and current during the charging process is as shown in Figure 2 If the voltage of the lithium battery is lower than the low voltage threshold, the charging circuit is in a trickle charging mode, and the size of the charging current is 17.5% of the set constant current charging current. When the battery voltage is greater than the low voltage threshold, the charging circuit enters the constant current charging mode, and the size of the charging current is set by the current using a resistor. When the battery voltage rises to near the constant voltage charging voltage 12.6 V, the charging circuit enters the constant voltage charging mode, and the charging current gradually decreases. When the charging current decreases to 16% of the constant current charging current, the DRV pin of the battery charging management chip U21 outputs a high level, the PMOS tube is cut off, and the charging is completed. At the same time, the DONE pin outputs a low level, and the PE7 pin of the MCU triggers an interrupt due to the detection of the falling edge level jump, thereby achieving overcharge protection of the lithium battery.

[0055] In this embodiment, the charging management module circuit is applied to charge the battery of a seismograph, but is not limited thereto, and can also be applied to charge the battery of other devices.

Claims

1. A charge management module circuit for a seismic instrument, characterized by: Battery charging management chip U21 is provided with VCC pin and charging input voltage VBUS electric connection, VG pin through the capacitor C204 and charging input voltage VBUS electric connection, GND pin ground, DRV pin drive and control PMOS pipe's conduction and cut-off, PMOS pipe's source and charging input voltage VBUS electric connection, drain is in turn through diode D11, inductance L9, current sampling resistance R204 and battery voltage VBAT electric connection, CSP pin and current sampling resistance R204 one end electric connection, BAT pin and current sampling resistance R204 the other end electric connection, DONE pin and MCU's PE7 input detection pin electric connection, PE7 input detection pin through resistance R201 and input voltage VDD3 electric connection, when charging, DONE pin is high resistance state, charging ends, DONE pin pull low to low level state.

2. A charge management module circuit for a seismic instrument according to claim 1, wherein: The charging input voltage VBUS is grounded through an input capacitor combination, which includes capacitors C201, C202 and C203 arranged in parallel, the positive electrode of the capacitor C201, one end of the capacitor C202 and one end of the capacitor C203 are electrically connected with the charging input voltage VBUS respectively, and the negative electrode of the capacitor C201, the other end of the capacitor C202 and the other end of the capacitor C203 are grounded.

3. A charge management module circuit for a seismic instrument according to claim 2, wherein: The capacitor C201 is a tantalum capacitor, the capacitor C202 and the capacitor C203 are ceramic capacitors.

4. A charge management module circuit for a seismic instrument according to claim 1 or 2 or 3, wherein: The battery voltage VBAT is grounded through an output capacitor combination, which includes capacitors C205, C206 and C207 arranged in parallel, the positive electrode of the capacitor C205, one end of the capacitor C206 and one end of the capacitor C207 are electrically connected with the battery voltage VBAT respectively, and the negative electrode of the capacitor C205, the other end of the capacitor C206 and the other end of the capacitor C207 are grounded.

5. A charge management module circuit for a seismic instrument according to claim 4, wherein: The capacitor C205 is a tantalum capacitor, the capacitor C206 and the capacitor C207 are ceramic capacitors.

6. A charge management module circuit for a seismic instrument as claimed in claim 1 or 2 or 3 or 5, wherein: A diode D12 is further provided, the negative electrode of the diode D12 is electrically connected with the negative electrode of the diode D11, and the positive electrode of the diode D12 is grounded. The diode D11 and the diode D12 are Schottky diodes.

7. A charge management module circuit for a seismic instrument as claimed in claim 1 or 2 or 3 or 5, wherein: The CHRG pin of the battery charging management chip U21 is electrically connected with the charging input voltage VBUS through the resistance R202, the CHRG pin is in a high resistance state when charging is completed, the CHRG pin is in a low level state when charging, the FB pin is electrically connected with the other end of the current sampling resistance R204 through the resistance R205, and the COM pin is grounded through the resistance R203 and the capacitor C204.

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